8086 nitish nagar

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Intel 8086 Microprocessor

By : Nitish Nagar

6CS9(X)

A2305208383(678) Batch 2008-2012


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Intel 8086 MicroprocessorIntel 8086 Microprocessor

By

Nitish Nagar

6CS9(X)

A2305208383(678)

Batch 2008-2012


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Difference Between 8085 and 8086

The most significant difference between the Intel 8085 and 8086

microprocessors is that the 8085 is an 8-bit system, NMOS

microprocessor and the 8086 is a 16-bit system, HMOS

microprocessor. This difference allows the 8086 system to have a

much larger set of operational instructions and can make

calculations to more significant places.

8085 contains 16-bit address bus and 8-bit data bus .8086 contains

20-bit address bus and 16-bit data bus.

In 8085 the clock speed is 3MHZ where as in 8086 the clock speed

is 5MHZ.

An 8085 processor has 6,500 transistors in its programming circuit

boards, compared with 29,000 transistors in an 8086 processor. This

means there are roughly 4.5 times more transistors in an 8086

processor, leading to a much faster processing rate.


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8086 has a special concept called as memory segmentation. It

allows parallel processing, while 8085 does not.

8085 consists 74 instructions. 8086 consists 117 instructions. In 8086

four 16 bit registers are available and pin no 33- min/(~max) it selects

minimum mode when this pin is high otherwise it selects maximum mode.

8086 has 4 segment registers which are not peresent in 8085. also it has

preftech queue which stores instructions ahead of time which is not present

in 8085. The BIU and execution unit in 8086 works parallely which improves

its performance.

Pipelining concept is not seen in 8085 and

The 8086 had more registers and many more instructions.

Both processors require a 5-volt power supply and both have a 40-pin

DIP, or dual inline package, which is how they plug into the circuit board in

the computer or device where they are being used. They also are both

roughly from the same era of computing and are now outdated.


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Pin Diagram of 8086

AD15-AD0

ADDRESS DATA BUS: These lines constitute

the time multiplexed memory or i/o address

and data bus .

ALE(ADDRESS LATCH ENABLE): A HIGH on

this line causes the lower orders 16-bit address

bus can be used as data bus.READY : READY is the acknowledgement

from the addressed memory or i/o device that

will be complete the data transfer .

INTR : INTERRUPT REQUEST is a level

triggered input which is sample during the last

clock cycle of each instruction to determine if

the processor should enter into interruptacknowledgment operation .

INTA : INTERRUPT ACKNOWLEDGEMENT

from the mp.

RESET : It causes the processor to

immediately terminate its present activity.


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Pin Diagram of 8086 8086 operates in single processor (minimum mode) or multi

processor (maximum mode) configurations to achieve highperformance.

The 8086 signals can be categorized in 3 groups.

I. Signals having common functions in minimum as well asmaximum mode.

II. Signals which have special functions for minimum mode.

III. Signals which have special functions for maximum mode.

I. Signals common for both minimum & maximum mode.

1. AD15-AD0 :

These are the time multiplexed memory I/O address & data lines.

Address remains on the lines during T1 state, while the data isavailable on the data bus during T2,T3,TW,T4.

These lines are active high, and float to a tristate during interruptacknowledge and local bus hold acknowledge cycles.

2. A19/S6, A18/S4, A17/S4, A16/S3

These are the time multiplexed address and status lines. During T1,these are the most significant address lines for memory operations.

During I/O operations these lines are low.


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The status of the Interrupt Enable Flag (IF) bit (displayed on S5) is updated

at the beginning of each clock cycle.

S4, S3 : together indicates which segment register is presently being used for

memory access.

These lines float at tristate off during the local bus hold acknowledge.

S4 S3 Indications

0 0 Alternate data

0 1 Stack

1 0 Code or none

1 1 Data

3. BHE/S7: Bus High Enable/Status

The bus high enable signal is used to indicate the transfer of data over the higher order

(D15-D8) data bus.

Whole word = Upper Byte + Lower Byte

BHE A0 Indication

0 0 Whole word i.e AD15 AD0

0 1 Upper byte from or to i.e AD15-AD8

1 0 Lower byte from or to even address i.e AD7-AD0

1 1 None


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4. RD: ReadRead signal , when low, indicates the peripherals that the processor is performinga memory or I/O operation.RD is active low & shows the state for T2, T3, TW of any read cycle. The signalremains tristated during the hold acknowledge.

5. READY:This is the acknowledgement from the slow devices or memory that they havecompleted the data transfer. The signal made available by the devices issynchronized by the 8284A clock generator.6. RESET:

This input causes to processor to terminate the current activityand start execution from FFFF0H i.e reinitialize the system.7. INTR: Interrupt Request:

This signal is sampled during the last clock cycle of each instruction to determinethe availability of the request. If any interrupt request is pending the processorenters the interrupt acknowledge cycle.8. TEST:This input is examined by a WAIT instruction. If TEST=0, execution willcontinue, else processor remains in an idle state. Input is synchronized by clockcycle.9. NMI: Non-Maskable InterruptThe NMI is not maskable internally by software. A transition from

low to high initiates the interrupt response at the end of thecurrent instruction.10. CLK: Clock InputThe clock input provides the basic timing for processor Operationand bus control activity.11. Vcc:+5V power supply for the operation of the internal circuit.

12. GND:Ground for the internal circuit.


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II. Minimum mode operation of 8086

1.M/IO-:

This line becomes active in the previous T4 and remains active

till final T4 of the current cycle.When it is high CPU wants to access memory.

2. INTA: Interrupt Acknowledge

This signal is low, the processor has accepted the interrupt. It is

active low during T2, T3, Tw of each interrupt acknowledge

cycle.

3. ALE: Address Latch EnableThis output signal indicates the availability of the valid address

on the address/data lines & it is connected to latch enable input

of latches. This signal is active high and is never tristated.

4. DT/R: Data transmit/Receive

This output is used to decide the direction of data flow through

the transreceivers (i.e bidirectional buffers)

DT/R = 1 Processor sends out data

DT/R = 0 Processor receives data

DT/R = S1 in maximum mode.


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III.Maximum mode operation of 8086

1.S2, S1, S0: Status linesThese lines active during T4 of the previous cycle & remain active during T1 & T2of the current bus cycle.

2. LOCK: This output pin indicates that other system bus masters will beprevented from gaining the system bus, while the LOCK=0. The LOCK signal isactivated by the LOCK prefix instruction and remains active until the completion

of the next instruction. This floats to tri-state off during hold acknowledge.

3. QS1, QS0 : Queue status These lines give information about the status of thecode-queue. These are active during the CLK cycle after which the queueoperation is performed.The 8086 architecture has a 6-byte instruction pre-fetchqueue.

4. RQ/GT0, RQ/GT1: Request/Grant These pins are used by other local busmasters, in maximum mode, to force the processor to release the local bus at theend of the processors current bus cycle.

Each of the pins is bidirectional with RQ/GT0 having higher priority thanRQ/GT1.


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Architecture of 8086:

The 8086 is divided into two units Execution Unit (EU) & Bus Interface Unit

(BIU). Both units operate asynchronously to give the 8086 an overlappinginstruction fetch and execution mechanism which is called as Pipelining. This

results in efficient use of the system bus and system performance.

The BIU fetches instructions, reads and writes data, and computes the

20-bit address.

The EU decodes and executes the instructions using the 16-bit ALU.

Decodes instructions fetched by the BIU

Generate control signals

Executes instructions

The BIU and execution unit in 8086 works parallely which improves its

performance.

The general purpoe register, Stack Pointer, Base Pointer, Index Register, ALU, Flag

Register, Instruction Decoder, an timing and control Unit constitute Execution unit.

The segment register, instruction pointer and 6byte instructionqueueare associated

with Base Interface Unit.


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Architecture :


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The BIU contains the following registers:

CS - the Code Segment Register DS - the Data Segment Register SS - the Stack Segment Register ES - the Extra Segment Register IP - the Instruction Pointer

Segment Registers

8086 has segmented memory. 1MB memory is divided into16 logical segments (16x64K)

CS Code Segment register used for addressing a memorylocation in the code segment of the memory where theexecutable program is stored.

SS Stack Segment register refers to stack segment of stackdata

DS Data Segment register point to the data segment of thememory, where the data is resided.

ES Extra Segment register also refers to a segment whichessentially is another data segment of the memory. (It alsopoints to data segment).

Bus Interface Unit :


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Execution Unit :1. Control circuit which directs internal operations.

2. Instruction Decoder translates instructions fetched from memory into aseries of actions which the EU carries out.

3. ALU Add, sub, increment, decrement, complement, shift binarynumbers.

4. General Data Registers

AX = (AH+AL) Accumulator.

BX - used as an offset storage for forming physical address.

CX - default counter in case of string and loop instructions.

DX implicit operand or destination register in case of a few instruction.5. Pointers and Index Registers

Pointers contain offset within the particular segments.

IP Instruction Pointer register holds the 16-bit address or offset of the

next code byte within code segment .

20 bit address = offset of IP + Segment base address in CS.

BP Base Pointer contains Source Index (SI) register and DestinationIndex (DI) register.

SP Stack Pointer register in the Execution Unit holds the 16-bit offset

from the start of the segment to the memory location where a word was

most recently stored on the stack (i.e top of stack).

SP,SI,DI these 3 register are used for temporary storage of data.


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How to calculate Physical address Segment registers hold the base address of where a particular segment

begins in memory. There is the code segment (CS), data segment (DS),stack segment (SS), and extra segment (ES).

Segment registers are 16-bit registers which are ASSUMED to be holding a

20 bit number, because it is assumed you will add a zero to the end. For

example, if CS register is holding the hexadecimal value "13A6", then this

value is actually representing the address "13A60".

To calculate a physical address, you take the address (called the logical

address) and add it to the segment address.

For example, if you wanted to calculate the physical address which relates

to logical address "1356" in the stack segment - you would also need to

know what value is in the SS register, lets assume "2345":

Add the zero to the end of the segment address:

23450

Then add the two addresses together:

23450 + 1356 = 247A6


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The physical address is calculated by finding out where thesegment starts, then adding to it the offset address.

One of the segment registers will tell you where the segment

begins.

Let's assume that the segment register is holding the value

"A45C". In this case, the segment begins at the 20 bit address

"A45C0".

Add to that the offset address:

A45C0 + 4B32 = A90F2.

Therefore the address A90F2 is the 20 bit physical address

that maps to the segment, offset address A45C:4B32


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6. Flag Registers

A flag is a flip-flop that indicates some condition produced by the execution

of an instruction or controls certain operations of the EU.

A 16-bit flag register in the EU contains 9 active flags, 6 flags indicate

some condition produced by an instruction(conidtion flags), 3 flags are

control flags.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

O Overflow Flag

S Sign Flag

Z Zero Flag

Ac Auxiliary Carry Flag

P Parity Flag

Cy Carry Flag

D Direction

I Interrupt Flag

T Trap Flag

X Not used

X X X X O D I T S Z X Ac X P X Cy


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InterruptsThe processor has the following interrupts :

INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using

STI/CLI instructions or using more complicated method of updating the FLAGS register

with the help of the POPF instruction. When an interrupt occurs, the processor stores

FLAGS register into stack, disables further interrupts, fetches from the bus one byte

representing interrupt type, and jumps to interrupt processing routine address of which

is stored in location 4 * . Interrupt processing routine should return with

the IRET instruction.

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTRinterrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is

stored in location 0008h. This interrupt has higher priority then the maskable interrupt.

Software interrupts can be caused by:

INT instruction - breakpoint interrupt. This is a type 3 interrupt.

INT instruction - any one interrupt from available 256 interrupts.

INTO instruction - interrupt on overflow Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When

the CPU processes this interrupt it clears TF flag before calling the interrupt processing

routine.

Processor exceptions: divide error (type 0), unused opcode (type 6) and escape

opcode (type 7).

Software interrupt processing is the same as for the hardware interrupts.


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Addressing Modes of 8086 :The way in which an operand is specified is called its addressing mode.

I. Data-related addressing modes

II. Branch addressing modes

I. Data-related addressing modes :

1. Immediate addressing mode

The datum is either 8 bits or 16 bits long and is part of the instruction.

2. Direct addressing modes

The 16 bit effective address (EA) of the datum is part of the instruction

3. Register addressing modes

The datum is in the register that is specified by the instruction.

4. Register Indirect

The effective address of the datum is in the base register BX or an index register that is

specified by the instruction.

5. Register RelativeThe effective address is the sum of an 8 or 16 bit displacement and the contents of

base register or an index register.

6. Based Indexed

The effective address is the sum of a base register and an index register.

7. Relative Based Indexed

The effective address is the sum of an 8 or 16-bit displacement and a based indexedaddress.


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Instruction SetInstruction Set

Instruction set of Intel 8086 processor consists of the following

instructions:

1) Data moving instructions.

2) Arithmetic - add, subtract, increment, decrement, convert

byte/word and compare.

3) Logic - AND, OR, exclusive OR, shift/rotate and test.

4) String manipulation - load, store, move, compare and scan for

byte/word.

5) Control transfer - conditional, unconditional, call subroutine

and return from subroutine.

6) Input/Output instructions.

7) Other - setting/clearing flag bits, stack operations, software

interrupts, etc.


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ASSEMBLER DIRECTIVES

An assembler is a program used to convert an assembly languageprogram into the equivalent machine code modules which mayfurther be converted to executable codes.

It decides the address of each label and substitutes the values for eachof the constant and variables.

It then forms the machine code for the mnemonics and data in theassembly language program (ALP).

The logical errors or other programming errors are not found out bythe assembler.To know errors hints are required from the programmer.

The hints are given to the assembler using some predefinedalphabetical strings called Assembler Directives, which help theassembler to correctly understand the ALPs to prepare the codes.


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MACROS

A macro is group if instructions we bracket and give a name to atthe start of our program. Each time we call the macro in ourprogram, the assembler will insert the defined group of instructionsin place of the call.

Every time a macro name in the program, replace it with the groupof instructions defined as that macro at the start of the program.This process is known as expanding the macro or macro expansion.

Using a macro avoids the overhead time involved in calling,returning from a procedure.

A disadvantage of generating in-line code each time a macro iscalled is that this will make the program take up more memory thanusing a procedure.


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Nitish Nagar

6CS9(X)

A2305208383

Batch 20082012

ENDBy :

8086 nitish nagar

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