8255 8251 8279

Advanced Microprocessors & Peripherals

Module I

Study of Interfacing ICs - 8255, 8251, 8279

8255 – Programmable Peripheral Interface(PPI)

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Widely used, programmable , Parallel I/O Device

It is flexible, versatile, and economical

It can be used with almost any microprocessor

8255 – Programmable Peripheral Interface

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Pin Details


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24 I/O pinsGrouped into two 8-bit parallel ports(A,B)Remaining 8-bit as port C

Used as individual bits or 4-bits(CUPPER, CLOWER)Control Word in Control Register

ww

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ctno

te.b

logs

pot.c

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Figure 1.1


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ModesBit Set/Reset(BSR) Mode

Set/Reset bits in Port CI/O Mode

Mode 0Mode 1(Handshake mode)Mode 2


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Blo

ck D

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am


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Control LogicRD(Read)

Reads data from I/O Port of 8255 to MicroprocessorWR(Write)

MPU writes into a selected I/O Port or Control Register

RESET(Reset)Clears the Control Register&Sets all ports in input

modeCS, A0, A1

Device select Signals


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Control Logic Contd……

•CS signal is the master Chip Select•A0 and A1 specify one of the two I/O Ports


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Control WordContents of Control Register :- Control WordThis register is used to write control word

when A1 & A0 at logic 1Not accessible for a read operation

Bit D7 specifies either I/O function or BSR function

D7=1, bits D6-D0 determine I/O functionsD7=0, Port C operates in BSR mode


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Control Word contd….To communicate with peripherals through

8255Determine the addresses of Ports A,B and C

and of control register according to the chip select logic and address lines A0 and A1

Write a control word in the control registerWrite I/O instructions to communicate with

peripherals through ports A,B and C


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Control Word

D7 D6 D5 D4 D3 D2 D1 D0

0/1

BSR Mode(Bit Set/Reset)

I/O Mode

Mode 0

Simple I/Ofor ports A,B and C

Mode 1

Handshake I/Ofor ports A and or B

Port C bits are used for handshake

Mode 2

Bidirectional data bus for Port A

Port B: either in Mode 0 or 1

Port C bits are used for handshake

Control Word


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Modes of operationI/O Mode

Mode 0: Simple Input or OutputPorts A and B are used as Simple I/O PortsPort C as two 4-bit portsFeatures

Outputs are latched Inputs are not latchedPorts do not have handshake or interrupt

capability


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Mode 1: Input or Output with HandshakeHandshake signals are exchanged between MPU &

Peripherals

FeaturesPorts A and B are used as Simple I/O PortsEach port uses 3 lines from Port C as handshake

signals Input & Output data are latched interrupt logic supported


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Mode 2: Bidirectional Data TransferUsed primarily in applications such as data transfer

between two computers

FeaturesPorts A can be configured as the bidirectional PortPort B in Mode 0 or Mode 1.Port A uses 5 Signals from Port C as handshake

signals for data transferRemaining 3 Signals from Port C Used as – Simple

I/O or handshake for Port B


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Modes of operationBSR(Bit Set/Reset) Mode

Concerned only with the 8-bits of Port C.Set or Reset by control word Ports A and B are not affected


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Serial Data Communication Serial Data FormatThe serial data format includes one start bit, five or eight data bits, one stop bit. A parity bit and an additional stop bit

might be included in the format as well.

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Methods of Data Communication

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Modes of data transmissionSimplex

Data is transmitted only in one direction over a single communication channel.

DuplexData may be transferred between two

transivers in both directions simultaneously.Half Duplex

Data transmission may take place in either direction, but at a time data may be transmitted only in one direction

8251 – UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)04/11/2321

Programmable chip designed for synchronous and asynchronous data transmission

28 pin DIPCoverts the parallel data into a serial

stream of bits suitable for serial transmission.

Receives a serial stream of bits and convert it into parallel data bytes to be read by a microprocessor.

8251 – UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER

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Block Diagram

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Five SectionsRead/Write Control Logic

Interfaces the chip with MPUDetermine the functions according to the control word Monitors data flow

TransmitterConverts parallel word received from MPU into serial

bitsTransmits serial bits over TXD line to a peripheral.

ReceiverReceives serial bits from peripheralConverts serial bits into parallel wordTransfers the parallel word to the MPU

Data Bus BufferModem Controller

Used to establish data communication modems over telephone line


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Read/Write Control Logic and Registers

This section includesR/W Control LogicSix input signalsThree buffer registers

Data registerControl RegisterStatus Register


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Input SignalsCS – Chip Select

When this signal goes low, 8251 is selected by MPU for communication

C/D – Control/DataWhen this signal is high, the control register

or status register is addressedWhen it is low, the data buffer is addressedControl and Status register is differentiated

by WR and RD signals, respectively


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WR – WriteEither writes in the control register or sends

outputs to the data buffer.This connected to IOW or MEMW

RD – ReadEither reads a status from status register or

accepts data from the data buffer This is connected to either IOR or MEMR

RESET - ResetCLK - Clock

Connected to system clockNecessary for communication with

microprocessor.


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CS C/D RD WR Function

0 1 1 0 MPU writes instruction in the control register

0 1 0 1 MPU reads status from the status register

0 0 1 0 MPU outputs the data to the Data Buffer

0 0 0 1 MPU accepts data from the Data Buffer

1 X X X USART is not Selected


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Control Register16-bit registerFirst byte is called mode instructionSecond byte is called command instructionThis register can be accessed an output port

when the C/D pin is highStatus Register

Checks ready status of a peripheralData Buffer


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Expanded Block Diagram of Transmitter and Receiver Section04/11/2330

Transmitter SectionAccepts parallel data and converts it into

serial dataTwo registers

Buffer RegisterTo hold eight bits

Output RegisterConverts eight bits into a stream of serial bits

Transmits data on TxD pin with appropriate framing bits(Start and Stop)


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Signals Associated with Transmitter Section

TxD – Transmit DataSerial bits are transmitted on this line

TxC – Transmitter ClockControls the rate at which bits are transmitted

TxRDY – Transmitter ReadyWhen it is high, it indicates that buffer register is emptyCan be used either to interrupt the MPU or indicate the

statusThis signal is reset when a data byte is loaded into the

bufferTxE – Transmitter Empty

Logic 1 on this line indicate that the output register is empty

This signal is reset when byte is transferred from buffer to the output registers


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Receiver Section

Accepts serial data from peripheral and converts it into parallel data

The section has two registersInput RegisterBuffer Register


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Signals Associated with Receiver SectionRxD – Receive Data

Bits are received serially on this line and converted into parallel byte in the receiver input

RxC – Receiver ClockRxRDY – Receiver Ready

It goes high when the USART has a character in the buffer register and is ready to transfer it to the MPU


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Signals Associated with Modem ControlDSR- Data Set Ready

General purpose one bit inverting input portNormally used to check if the Data Set is ready when

communicating with a modemDTR – Data Terminal Ready

device is ready to accept data when the 8251 is communicating with a modem.

RTS – Request to send Data the receiver is ready to receive a data byte from modem

CTS – Clear to Send


8279 – Programmable Keyboard/Display Interface

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The keyboard display controller chip 8279 provides:

a set of four scan lines and eight return lines for interfacing keyboards

A set of eight output lines for interfacing display.

8279 – PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE

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I/O Control The I/O control section controls the flow of

data to/from the 8279Data Buffers

The data buffers interface the external bus of the system with internal bus of 8279.

The I/O section is enabled only if CS is low. The pins A0,RD and WR select the

command, status or data read/write operations carried out by the CPU with 8279.


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Control and Timing Register and Timing Control

These registers store the keyboard and display modes and other operating conditions programmed by CPU

The Timing and control unit controls the basic timings for the operation of the circuit.


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Scan Counterhas two modes to scan the key matrix and refresh

the displayEncoded Mode

the counter provides binary count that is to be externally decoded to provide the scan lines for keyboard and display

Decoded Modethe counter internally decodes the least significant 2

bits and provides a decoded 1 out of 4 scan on SL0-SL3

The keyboard and display both are in the same mode at a time.


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Return Buffers and Keyboard Debounce and ControlScans for a key closure row wiseThe code of key is directly transferred to the

sensor RAM along with SHIFT and CONTROL key status.

FIFO/Sensor RAM and Status Logic8-byte first-in-first -out (FIFO) RAMEach key code of the pressed key is entered in

the order of the entryThe status logic generates an interrupt after

each FIFO read operation till the FIFO is empty


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Display Address Registers and Display RAM

holds the address of the word currently being written or read by the CPU to or from the display RAM

The contents of the register are automatically updated by 8279


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Modes of Operation of 8279The modes of operation of 8279 are as follows

:1. Input (Keyboard) modes.2. Output (Display) modes.

Input ( Keyboard ) Modes : 8279 provides three input modes. These modes are as follows:

1.Scanned Keyboard Mode2.Scanned Sensor Matrix3.Strobed input


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Scanned Keyboard ModeThis mode allows a key matrix to be

interfaced using either encoded or decoded scans

In encoded scan, an 8*8 keyboard or in decoded scan, a 4*8 keyboard can be interfaced

The code of key pressed with SHIFT and CONTROL status is stored into the FIFO RAM.


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Scanned Sensor MatrixIn this mode, a sensor array can be interfaced

with 8279 using either encoded or decoded scans

With encoded scan 8*8 sensor matrix or with decoded scan 4*8 sensor matrix can be interfaced

The sensor codes are stored in the CPU addressable sensor RAM

Strobed inputif the control lines goes low, the data on return

lines, is stored in the FIFO byte by byte


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Output (Display) Modes : 8279 provides two output modes for selecting the display options

Display Scan In this mode 8279 provides 8 or 16 character

multiplexed displays those can be organized as dual 4- bit or single 8-bit display units.

Display Entry : ( right entry or left entry mode ) 8279 allows options for data entry on the displays.

The display data is entered for display either from the right side or from the left side.


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Keyboard ModesScanned Keyboard mode with 2 Key

LockoutScanned Keyboard with N-Key RolloverScanned keyboard special error modeSensor matrix modeDisplay ModesLeft Entry mode(Type writer mode)Right Entry mode(Calculator mode)


Interfacing with 8085 - Interfacing keyboard – Hardware and Software approach –

Interfacing seven segment displays - Interfacing D/A and A/D converters - Micro

controllers

Module II

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Scanned Keyboard mode with 2 Key Lockout

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Interfacing Matrix keyboard

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Steps

Ground all the rows by sending logic 0 through the output port

Check the columns by reading the input port. If no key is pressed , all columns remains high.

When one key is pressed, corresponding column goes low; identify and decode the key.

Program

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Check whether all keys are openNecessary to avoid misinterpretation if a key is

held for a long timeCheck a key closure

D3-D0 should be 1111Identify the key

Complex procedureGrounding one row at a time and checking each

column for zeroFind the binary key code for the key

Counter ProcedureFor 5 Rows counter is incremented from 0 to 13H

Interfacing Key Board Hardware Approach

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Interfacing circuit of a six – seven- segment LED display using the technique of multiplexing.

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4x4 MATRIX KEYBOARD & 4 DIGIT 7 SEGMENT DISPLAY INTERFACE

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FLOWCHARTS Source Program and Interrupt Service Routine

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Source program:

MVI A, 00H : Initialize keyboard/display in encoded

OUT 81H : scan keyboard 2 key lockout mode

MVI A, 34H OUT 81H : Initialize prescaler countMVI A, 0BH : Load mask pattern to enable

RST 7.5SIM : mask other interruptsEI : Enable InterruptHERE: JMP HERE : Wait for the interrupt

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Interrupt service routine

MVI A, 40H : Initialize 8279 in read FIFO RAM mode

OUT 81H IN 80H : Get keycode MVI H, 62H : Initialize memory pointer to

point MOV L, A : 7-Segment code MVI A, 80H : Initialize 8279 in write display

RAM mode OUT 81H MOV A, M : Get the 7 segment code OUT 80H : Write 7-segment code in display

RAM EI : Enable interrupt RET : Return to main program

Digital-To-Analog(D/A) Converters

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Interfacing AD558 with 8085

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Interfacing a 10-bit D/A Converter

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In many D/A converter application 10-bit or 12-bit is required.

The 8-bit microprocessor has only 8-bit data lines.

To transfer 10-bits, the data bus is time-shared by using two output ports: one for first 8-bit and second for remaining two bits.

AD7522 is a CMOS 10-bit D/A converter with an input buffer and a holding register.

The ten bits are loaded into the input register in two steps using two output ports.


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The low-order eight bits are loaded with the control line LBS and the remaining two bits are loaded with HBS.

Then all ten bits are switched into a holding register for conversion by enabling the line LDAC.


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Analog-To-Digital(A/D) converter

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Interfacing 8-bit A/D Converters

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A pulse to START pin begins the conversion process and disables the tri-state output buffer.

At the end of the conversion period DATA READY becomes active and the digital output is made available at the out put buffer.

To interface an A/D converter with the microprocessor, the microprocessor should

1. Send a pulse to START pin. This can be derived from a control signal such as Write(WR).


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2. Wait until the end of conversion. The end of conversion period can be verified either by status checking(Polling) or by interrupt.

3. Read the digital signal at an input port.

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8255 8251 8279

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