Input/ OutputIsaac Asimov, Salvor Hardin in "Foundation"
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1. physical I/O devices
2. virtual (logical) I/O devices: operating system abstractions eg. spooled print file, files vs. sectors on disk
Telephony Application Programmed Interface (TAPI)
Telephony Service Provider Programming Interface (TSPI)
Physical I/O
To transfer information between CPU and physical I/O devices, one may use the following techniques:
1. programmed I/O
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eg. Intel
In and OUT instructions
pin on CPU chip indicates whether IO or memory address space being used. [See next slide]
2. memory-mapped I/O address space
eg. Motorola
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# I/O ports is unlimited
I/O interfaces may need more circuitry to recognize larger addresses.
possible slow down in bus performance.
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1. unconditionally – CPU sends data to device at any time
2. conditionally – checking the status of the device before the operation (i.e. handshaking).
CPU may have to poll and wait for device -> inefficient
The CPU communicates with an I/O devices via one or more registers called I/O ports.
Bit-serial ports
Every bit in the port may be configured as either input or output.
0
1
1
0
0
1
1
0
COSC 3P92
Parallel ports
Each I/O port (as a whole) may be configured as either input or output.
I/O port A (output)
COSC 3P92
Interrupt I/O
When an I/O device is ready to send (receive) data to (from) the CPU, it signals (or interrupts) the CPU for its attention.
No need to poll device status.
As soon as the CPU finishes the current instruction, it transfers its execution to an interrupt-service routine which responds to the external interrupt.
Q. How does the CPU know which one of the ISRs to execute when there is more than one?
Interrupt Service Vectors: address of interrupt service routines, commonly kept in special jump table.
Current execution path
move.b #$00, DDRB ; registers
...
transaction...
rte
Direct Memory Access (DMA)
It is a technique of transferring data between memory and I/O devices without CPU intervention.
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meanwhile
does a DMA while CPU frozen
- word-by-word transfer
3. Interleaved
using the bus, letting DMA xfers and CPU
alternate use of the bus
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Independent dedicated I/O processors (smart DMA controllers) are used in mainframe computer systems to communicate with I/O devices.
4.bin
Some considerations:
priority system for devices on one IO bus
IOP requires software or hardware to manage different devices
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