9.sequential+circuits part+1
TRANSCRIPT
James Morizio 1
Sequential Circuit Design: Part 1
• Design of memory elements– Static latches
– Pseudo-static latches
– Dynamic latches
• Timing parameters• Two-phase clocking• Clocked inverters
James Morizio 2
Sequential Logic
2 s torage mechanis ms
• pos itive feedback
• charge-bas ed
LOGIC
tp,combInOut
FFs
James Morizio 3
Sequencing• Combinational logic
– output depends on current inputs
• Sequential logic– output depends on current and previous inputs
– Requires separating previous, current, future
– Called state or tokens
– Ex: FSM, pipeline
CL
clk
in out
clk clk clk
CL CL
PipelineFinite State Machine
James Morizio 4
Sequencing Cont.
• If tokens moved through pipeline at constant speed, no sequencing elements would be necessary
• Ex: fiber-optic cable– Light pulses (tokens) are sent down cable
– Next pulse sent before first reaches end of cable
– No need for hardware to separate pulses
– But dispersion sets min time between pulses
• This is called wave pipelining in circuits
• In most circuits, dispersion is high– Delay fast tokens so they don’t catch slow ones.
James Morizio 5
Sequencing Overhead
• Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.
• Inevitably adds some delay to the slow tokens• Makes circuit slower than just the logic delay
– Called sequencing overhead
• Some people call this clocking overhead– But it applies to asynchronous circuits too
– Inevitable side effect of maintaining sequence
James Morizio 6
Sequencing Elements• Latch: Level sensitive
– a.k.a. transparent latch, D latch
• Flip-flop: edge triggered– A.k.a. master-slave flip-flop, D flip-flop, D register
• Timing Diagrams– Transparent
– Opaque
– Edge-trigger
D
Flo
p
Latc
h
Q
clk clk
D Q
clk
D
Q (latch)
Q (flop)
James Morizio 7
Flip-Flop: Timing Definitions
DATA
STABLE
In
t
tsetup thold
DATA
STABLE
Out
t
tpFF
t
James Morizio 8
Maximum Clock Frequency
LOGIC
tp,comb
FFs
James Morizio 9
Latch Design
• Pass Transistor Latch• Pros
+ Tiny+ Low clock load
• Cons– Vt drop– nonrestoring– backdriving– output noise sensitivity– dynamic– diffusion input
D Q
Used in 1970’s
James Morizio 10
Latch Design
• Transmission gate+ No Vt drop
- Requires inverted clock
D Q
James Morizio 11
Latch Design
• Inverting buffer+ Restoring
+ No backdriving
+ Fixes either
• Output noise sensitivity
• Or diffusion input
– Inverted output
D
XQ
D Q
James Morizio 12
Latch Design
• Buffered input+ Fixes diffusion input
+ Noninverting
QDX
James Morizio 13
Latch Design
• Buffered output+ No backdriving
• Widely used in standard cells+ Very robust (most important)- Rather large- Rather slow (1.5 – 2 FO4 delays)- High clock loading
Q
D X
James Morizio 14
Latch Design
• Tristate feedback+ Static
– Backdriving risk
• Static latches are now essential
QDX
James Morizio 15
Latch Design
• Datapath latch+ Smaller, faster
- unbuffered input
Q
D X
James Morizio 16
Design of Memory Elements
Q
C
C
C
C
D
Q
Positive edge-triggered D flip-flopWhy use inverters on outputs?
Skew Problem : may be delayed with respect to (both may be 1 at the same time)
This is what happens-
Q
QD
C
in
1 Transmission gate acts a buffer, should have samedelay as inverter
Eliminating/Reducing skew:
James Morizio 17
Latch design
Static D latch “Jamb” latch Weak inverter
C
C
C
D
DQ Q
James Morizio 18
Latch Design
CD
C
Q
Variant of D latch
D
Q
James Morizio 19
Flip-Flop Design• Flip-flop is built as pair of back-to-back latches
D Q
X
D
X
Q
Q
James Morizio 20
Enable• Enable: ignore clock when en = 0
– Mux: increase latch D-Q delay
– Clock Gating: increase en setup time, skew
D Q
Latc
h
D Q
en
en
Latc
hDQ
0
1
en
Latc
h
D Q
en
DQ
0
1
enD Q
en
Flo
p
Flo
p
Flo
p
Symbol Multiplexer Design Clock Gating Design
James Morizio 21
Reset• Force output low when reset asserted• Synchronous vs. asynchronous
D
Q
Q
reset
D
Q
D
reset
Q
Dreset
reset
reset
Synchronous R
esetA
synchronous Reset
Sym
bol Flo
p
D Q
Latc
h
D Q
reset reset
Q
reset
James Morizio 22
Set / Reset
• Set forces output high when enabled• Flip-flop with asynchronous set and reset
D
Q
reset
setreset
set
James Morizio 23
Dynamic Latches
• So far, all latches have been static-store state when clock is stopped but power is maintained
• Dynamic latches reduce transistor count• Eliminate feedback inverter and transmission gate• Latch value stored on the capacitance of the input
(gate capacitance)
James Morizio 24
Dynamic Latch and Flip-Flop
• Difficult to ensure reliable operation
• Similar to DRAM
• Refresh cycles are required
CD
QC
Data stored asCharge on gate capacitance
Dynamic D latch
CD
QDynamic negativeedge-triggered D flip-flop
C
James Morizio 25
Charge-Based Storage
Schematic diagram
Non-overlapping clocks
P s e u do -s ta tic Latc h
QD
Q
James Morizio 26
Master-Slave Flip-Flop
A
B
Overlapping Clocks Can Caus e
• Race Conditions
• Undefined Signals
D
Q
To reduce skew: generatecomplement of clock within the cellExtra inverter per cell
James Morizio 27
Two-Phase Clocking
• Inverting a single clock can lead to skew problems
• Employ two non-overlapping clocks for master and slave sections of a flip-flop
• Also, use two phases for alternating pipeline stages
James Morizio 28
Two-Phase Clocking
1(t) . 2(t) = 02
1=1, 2 = 0
1
2
CD
QC
1
D Q
1=0, 2 = 1D Q
James Morizio 29
2-phase non-overlapping clocks
1
2
t
Important:Non-overlap time t must bekept small
2
1
1
2
Q
D
Pseudo-staticD flip-flop
James Morizio 30
2-phase dynamic flip-flop
Input Sampled
Output Enable
D Q
James Morizio 31
Use of “p” Leakers
Q
Degraded voltage VDD-Vt
Flip-flopbased on nMOSpass gates
1 2
D
Q
1 2
D
No need to route signals
pMOS leaker transistorsprovide full-restored logiclevelsProblem: Increased delay
(extra inverter)
James Morizio 32
Clocked Inverters
Q
Similar to tristate buffer = 1, acts as inverter
= 0, output = Z
D
i1 i2 i3Q
D
D Latch
James Morizio 33
Flip-flop insensitive to clock overlap
DIn
VDDVDD
M1
M3
M4
M2 M6
M8
M7
M5
section section
CL1 CL2
X
C2MOS flip-flop
James Morizio 34
C2MOS avoids Race Conditions
DIn
1
M1
M3
M2 M6
M7
M5
1
DIn
VDDVDD
M1
M4
M2 M6
M8
M5
0 0
VDDVDD
(a) (1-1) overlap (b) (0-0) overlap
X X