ENG241 ENG241 Digital DesignDigital Design

Week #6 Sequential Circuits (Part A)

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Week #6 TopicsWeek #6 Topics

Sequential Circuit Definitions Latches Flip-Flops Delays in Sequential Circuits Clock Gating

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ResourcesResources

Chapter #6, Mano Sections 6.1 Sequential Circuit Definition 6.2 Latches 6.3 Flip-Flops

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Combinational/Sequential CircuitsCombinational/Sequential Circuits

Combinational logic are very interesting and useful for designing arithmetic circuits (adders, multipliers) or in other words the Data Path of a computer.

Combinational circuits cannot remember what happened in the past (i.e. outputs are a function of current inputs).

In certain cases we might need to store some info before we proceed with our computation or take action based on a certain state that happened in the past.

Sequential circuits are capable of storing information between operations. They are useful in designing registers, counters, and CONTROL Circuits.

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Remembering StatesRemembering States

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Sequential CircuitsSequential Circuits

Information that is stored in the storage elements represent the state of the system.

The outputs will depend on the inputs and present state of the storage elements.

Storage

Elements

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Types of Sequential CircuitsTypes of Sequential Circuits

Two main types and their classification depends on the times at which their inputs are observed and their internal state changes. Synchronous

State changes synchronized by one or more clocks

Asynchronous Changes occur independently

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Signal Examples Over TimeSignal Examples Over Time

Analog

Asynchronous

Synchronous

Time

Continuous in value &

time

Discrete in value & continuous

in time

Discrete in value &

time

Digital

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Clocking of Synchronous CircuitsClocking of Synchronous Circuits

Changes enabled by clock

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ComparisonComparison

Synchronous Easier to analyze because can factor out gate

delays Speed of the system is determined by the

clock (maybe slowed!) Asynchronous

Potentially faster Harder to analyze

We will look mostly at synchronous

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Basic Storage (How?)Basic Storage (How?)

1. Apply low or high for longer than tpd But we are interested in storing information indefinitely!

2. Feedback will hold value However we want inputs to our circuitry!

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LatchesLatches

Are storage elements that can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directed by an input signal to switch states. Latches are asynchronous circuits Latches are used to build more

complex synchronous circuits such as Flip Flops.

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SR (set-reset) Latches: SR (set-reset) Latches:

Replace the inverters with NAND, NOR Gates Basic storage made from gates The information can be changed

S & R both 0 in “resting” state Have to keep both from 1 at same time

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OperationOperation

Reset, Q=0

Keep State

Set, Q=1 Undefined!

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Latch

Similar – made from NANDs

RS

• S & R both 1 in “resting” state• Have to keep both from 0 at same time

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Add Control Input: SR LatchAdd Control Input: SR Latch

An additional input determines when the state of the latch can be changed!

Can we avoid the undefined state?

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D-type LatchD-type Latch

No illegal state

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Transparency of LatchesTransparency of Latches

The state of a latch is allowed to switch by a momentary change in value on the control input. As long as C (the trigger ) is high, state can

change! This is called transparencytransparency

What is wrong with transparency?

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Effects of TransparencyEffects of Transparency

Output of one latch may feedback As soon as the input changes, shortly thereafter

the corresponding output changes to match it. The final state will depend on how long the

clock pulse stays at level logic 1! (unreliable) We need to predict the outputs at a certain

moment in time!o Want to change latch state once

Depending on inputs at time of clock

Storage Element

Clock

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Flip-FlopsFlip-Flops

Ensure only one transition Two major types

1. Master-Slave (level triggered) Two stage Output not changed until clock

disabled

2. Edge triggered Change happens when clock level

changes

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Master-Slave SR Flip-FlopMaster-Slave SR Flip-Flop

When Master is enabled, Slave is disabled! Output Q will not change when inputs change

S

C

R

S

C

R

S

C

R

SR LatchMaster

Slave

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Timing DiagramTiming Diagram

Trace the behavior Note the illegal state Is it transparent?

1

00

1

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Have We Fixed the Problem?Have We Fixed the Problem?

Output no longer transparent Combinational circuit can use last values New inputs appear at latches Not sent to output until clock low In one clock cycle we can predict what will happen

Note: Master-Slave = pulse triggered

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JK Flip FlopJK Flip Flop

The JK Flip Flop is a modified version of the SR Flip Flop which eliminates the undesirable condition that leads to undefined outputs.

The JK flip flop performs three operations:1. Set Q to 12. reset Q to 03. complement the output

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Master-Slave JK Flip Flop Master-Slave JK Flip Flop

The J input sets the flip flop to 1.The K input resets the flip flop to 0.When both J and K are enabled, the

output is complemented.

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Edge-Triggered Flip-FlopsEdge-Triggered Flip-Flops

An Edge Triggered Flip-Flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal. New state latched on clock transition Low-to-high or high-to-low

Changes when clock high are ignored

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Clock ResponsesClock Responses

We can classify Flip/Flops according to the response to the clock.

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Edge Triggered D-Flip-FlopEdge Triggered D-Flip-Flop

D

C

S

C

R

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Characteristic TablesCharacteristic Tables

Define the logical properties of a flip flop by describing its operations in tabular form. They define the next state as a function of the inputs

and the present state. Q(t) refers to the present state prior to the application

of a clock edge. Q(t + 1) refers to the next state one clock period later. Clock edges are not listed as inputs but are implied by

the transition from t to t + 1.

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D FF Characteristic TableD FF Characteristic Table

The Characteristic Equation:Q(t + 1) = D(t)

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Edge-Triggered D Flip Flop: Edge-Triggered D Flip Flop: Graphic Symbols Graphic Symbols

The triangle is called: dynamic indicator

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Other Flip FlopsOther Flip Flops

Other types of flip flops can be constructed by using the D flip flop and external logic. The two most commonly used are:

1. Edge triggered JK flip flops2. T flip flops

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JK Characteristic TableJK Characteristic Table

Characteristic Equation:Q(t+1) = J(t) Q’(t) + K’(t)Q(t)

Utilize the equation to create a JK flipflop from an existing D flipflop

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Edge-Triggered JK Flip Flop Edge-Triggered JK Flip Flop

Q(t+1) = J(t) Q’(t) + K’(t)Q(t)

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Analysis of the JK CircuitAnalysis of the JK Circuit

The circuit applied to the D input is D = JQ’ + K’Q

I. If J = 1 and K = 0, D = Q + Q’ = 1 (Set)II. If J = 0 and K = 1, D = 0 (Reset)III. If J = K = 0, D = Q, (No Change)IV. If J = K = 1, D = Q’ (Complement)

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T Flip Flop T Flip Flop

T

The T Flip Flop is a complementing flip flop.

How can we obtain a T Flip Flop from a JK Flip Flop or D Flip Flop?

Q(t+1) = TQ’(t) + T’Q(t)

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T Flip FlopT Flip Flop

The T flip flop can be obtained from a JK flip flop when inputs J and K are tied together.

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Characteristic EquationsCharacteristic Equations

The D flip flop can be expressed as: Q(t + 1) = D

The JK flip flop can be expressed as: Q(t + 1) = JQ’ + K’Q

The T flip flop can be expressed as: Q(t + 1) = TQ’ + T’Q

Characteristic Tables are used to1. Derive the characteristic equations,2. Analyze Sequential Circuits.

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JK- Characteristic Equation JK- Characteristic Equation

Q(t+1) = J(t) Q’(t) + K’(t)Q(t)

0 0 0 ^ 0

0 0 1 ^ 1

0 1 0 ^ 0

0 1 1 ^ 0

1 0 0 ^ 1

1 0 1 ^ 1

1 1 0 ^ 1

1 1 1 ^ 0

J K Q CLK Q+

0 0 1 1

1 0 0 1

QJK

0

1

00 01 11 10

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Standard Symbols – LatchesStandard Symbols – Latches

Circle at input indicates negation

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Symbols – Master-SlaveSymbols – Master-Slave

Inverted L indicates postponed output Circle indicates whether enable is

positive or negative

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Symbols – Edge-TriggeredSymbols – Edge-Triggered

Arrow indicates edge trigger

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Direct InputsDirect Inputs

Set/Reset independent of clock Direct set or preset Direct reset or clear

Often used for power-up reset

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VHDL Design StylesVHDL Design Styles

Components andinterconnects

structural

VHDL Design Styles

dataflow

Concurrent statements

behavioral(algorithmic)

• Registers• State machines• Test benches

Sequential statements

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VHDL For Sequential CircuitsVHDL For Sequential Circuits

Several techniques have been discussed in class to describe the architecture of combinational logic circuits:

1. Data Flow2. Structural

Statements used in “Data Flow” and “Structural” descriptions can be executed in parallel i.e. concurrently.

Another technique to describe the architecture of any circuit is to use Behavioral description.

The process statement is usually used to describe sequential designs.

The process statement consists of only sequential statements

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VHDL For Sequential CircuitsVHDL For Sequential Circuits

To describe sequential circuits we usually use the “process” statement.

A process statement consists of 1. Sensitivity list Process (CLK, RESET)

This list enumerates exactly which signals causes the process statement to be executed. (Only events on these signals cause the process statement to be executed!)

2. Declarative region Process (CLK, RESET) …… (declare local vars) Begin ….. END

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VHDL for Positive Edge Triggered D-FFVHDL for Positive Edge Triggered D-FF

-- positive Edge-Triggered D flip-flop with reset-- VHDL Process Descriptionlibrary ieee;use ieee.std_logic_1164.all;entity dff is port (CLK, RESET, D : in std_logic; Q : out std_logic);end dff;

architecture pet_pr of dff isbegin process (CLK, RESET) begin if (RESET = `1’) then Q <= `0’; elsif (CLK’event and CLK = `1’) then - - you can use rising_edge(CLK) instead! Q <= D; end if; end process;end;

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Flip-Flop TimingFlip-Flop Timing

• Setup time (ts)– time that D must be available before clock edge

• Hold time (th)– time that D must be stable after clock edge

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SummarySummary

Combinational logic are very interesting and useful for designing arithmetic circuits (adders, multipliers) or in other words the Data Path of a computer.

Sequential circuits are capable of storing information between operations. They are useful in designing registers, counters, and CONTROL Circuits.

Latches are storage elements that are asynchronous, transparent and are used to build more complex synchronous circuits such as Flip-Flops.

Flip-flops avoid the transparency problem faced by latches and are either Master-Slave pulse active or edge triggered.

Characteristic tables will be used to analyze the behavior of sequential circuits.

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Propagation Delay

Propagation delay – time after edge when output is available

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Positive D-Type Edge Triggered

D

C

S

C

R

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Have We Fixed the Problem?

Output no longer transparent Combinational circuit can use last values New inputs appear at latches Not sent to output until clock low In one clock cycle we can predict what will happen

But changes at input of FF when clock high trigger next state Transient state where S goes high caused by gate

delays As clock faster, more problems Have to guarantee circuit settles while clock low

Note: Master-Slave = pulse triggered

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Clock Pulse Requirements

Basically a max clock frequency

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Clock Gating

Can gate clocks (to keep any FF from changing states, for example) Clock gating used to reduce power drain

However, can cause clock skew Clock edges at different times on different

FFs Clock skew also caused by wire lengths

over chip

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T Flip Flop

The T flip flop can also be obtained from a D flip flop by using an XOR as the input for D.

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Master-Slave JK Flip Flop

Q(t+1) = J(t) Q’(t) + K’(t)Q(t)