A 16 Kb Spin-Transfer Torque Random Access Memory With Self-Enable Switching and Precharge Sensing Schemes

A Survey of Spin-Transfer Torque Magnetic Random Access Memory and Sensing Circuit Improvements Arielle WalkerDecember 5, 2014VLSI Design Final Project

OutlineIntro to STT-MRAMComparison to different memory typesMRAM physics and the Magnetic Tunnel JunctionMTJ Electrical PropertiesSTT Switching TechniquesIntegration of STT-MRAM with CMOS systemsRead/Write Circuit Schematics Memory ArchitectureLow Power and High Reliability Design Improvements

Spin-Transfer Torque MRAMNon VolatileSpeed of SRAMMemory density of DRAMNo degradationPromising results to be the first universal memory system

Comparison of Different Memory TypesSRAM = good read/write speeds, bad cell sizeDRAM = good high memory density, bad high power consumption (due to refresh cycle from charge leak)Flash = good non-volatility, bad slow write speeds and endurance. STT-MRAM = good everywhere!

MRAM and Magnetic Tunnel JunctionUtilizes magnetic field direction to store binary data and reads it by exploiting magneto-resistive propertiesMTJ = building block of MRAM systemThe MTJ: Two ferrous layers separated by an insulating layer1, Low Resistance0, High Resistance

Free Layer

Fixed Layer

Fixed layer can be either sufficiently thick or attached to an anti-ferrous layer to avoid re-orientation

MRAM and Magnetic Tunnel JunctionInstead of traditional electronic device where information processing is controlled by flow of charge, MRAM stores information by forcing electron spinFirst layer acts as a spin-polarizer, second layer acts as a spin-filterTogether these form a spin-valve operationSpin-polarized electrons tunnel though the insulating barrier on the nanoscale

MTJ Electrical Properties

STT-MRAM and MTJ Electrical PropertiesImproved resistance hysteresis Better properties seen with MgO as insulator

Compared to traditional MRAM:Lower switching current is neededSimpler/smaller cell architectureLower manufacturing costsImproved scalability

Conventional MRAM vs. STT-MRAM Design

Spin-Transfer Torque SwitchingSpin-Polarized Electrons exert a torque on the second ferrous layer (the filter)Angular Momentum is only conserved if no net torque; angular momentum is changingThis net torque, if strong enough, can change the orientation of the magnetic fieldThe value can be computed by considering the net change in spin current before/after the interactionThree Ways(1) Precessional, (2) Dynamic, (3) Thermal Agitation

STT-MRAM Integration with CMOS Physics are fully compatibleSome manufacturability and layout constraints present a current design challengeCurrent goes directly through MTJ, unlike traditional MRAMSharedStacked

Parasitic current paths can accidentallyFlip a MTJ and lower TMR

Each MTJ cell would need sufficiently different critical writing current. Read/write would require multiple cycles

Write and Read CircuitsWriteReadCurrents > thresholdCurrent < threshold

Memory Architecture: Three Ways

One storage bit is represented by several complementary MTJsFast Speed, Good SensingHigh Area Overhead, Low power efficiency during write operation

B) Each storage bit is represented by one MTJ and connected to one reference cellLower Power High Cell Array Area

C) Each storage bit has one MTJ and each column of bits has one reference cellReduced Cell Array AreaSome parasitic resistances reduce sensing ability

Design Optimization to Overcome Reliability Issues and Improve Power ConsumptionWriting Circuit with Low Power Supply VoltageEffectively reduced the power consumption by reducing the switching energy of a conventional writing circuit from 6.0pJ/bit to 4.0pJ/bit. Self-Enable Switching CircuitSucceeded in saving even more energy, reducing the switching energy to only 1.6pJ/bit.Improved the lifetime of the MTJ by reducing MTJ operationsFore-Placed SA in the Read CircuitImproved the robustness of process variation.

Writing Circuit with Low Power Supply Voltage: Conventional Way

Writing Current depends on the resistances of N1-N4 and supply voltage at tend of writing branch.A low Iwrite, which minimizes power consumption, requires either reducing those resistances or increasing the power supply voltageStandard power supply voltage is typically at Vdda, slightly above Vdd

Writing Circuit with Low Power Supply Voltage: Improved WayDifferent column selected gates used in read/write operationsSeparates read/writing operations completelyReduces transistors (and resistance) from 6 to 4. Makes the critical current density much smallerAllows for a lower power supply voltage to be supplied

Self-Enable Switching CircuitSTT Switching pulse can occasionally happen too fast to accurately record dataExploiting this stochastic behavior to implement into a sensing circuit to avoid having to extend the write timeUtilizes one short write pulseSelf enable logic is 1 when different signal, 0 when same.If self enable is off, circuit does not sense, even if W-enable is on, reducing the number of cycles and saving power

SummarySTT MRAM is a promising new technologySome manufacturing challenges currently consist, but are being actively researched

Questions?