A leap ahead in mixed signal

Statistical SPICE modeling for analog circuit design

Gerhard Rappitsch

MOS-AK: Advanced Compact Modeling Workshop (ESSCIRC), Estoril

19 September 2003

2

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

SPICE MODELING Simulator Integration

Spectre, Eldo, ..

Testchips, SLM

DESIGNHIT-Kit, Customer

Process Characterisation

Device ModelsMeasurement

Parameter ExtractionStatistical Modelling

Statistical Process Data

MAP-Parameters

Process

SPICE modeling

3

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

SPICE Models for Circuit Simulation

– Device models are complex analytical model (BSIM3v3, EKV etc.).

– Parameters are determined by optimisation.

– Model Parameters = Typical SPICE parameters.

– Measurement and extraction are time-consuming.

Ids = f(vth,u0,tox,xl, ...,vgs, vds, w, l )Cgg=f(vth, tox, dlc, …, vgs, vds, w, l)

Devices are measured on a single golden wafer

4

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

MAP (Production Control) Parameters

– Measured on each wafer during production

– Pass/Fail - Parameters

– Monitor process variation

– simplified equations (fast)

– Statistics available (database)

– Used for yield analysis

Parametric variation of devices is controlled during production

LCL UCL

NMOS treshold variation

5

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Robust Design

– temperature range (-40 to 125 deg.)

– supply voltage range (5 ± 0.5V)

– Parametric process variation

– Local variations (mismatch)

Process variations and local mismatch effects must be considered during the design phase (design centering)

Corner “slow”Overall yield is affected by:

LCL UCL

P

Performance Corner “fast”

Typical

A

6

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

CheckProcess Variation

and Mismatch

Typical Designand Simulation Change Design

Parameters

Shift Typical Design

Not O.K.

RobustDesign

O.K.

Design for Manufacturability

Fail

LCL UCL

Performance

P

7

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Predict Performance Yield: Simulation Methods

SimulationMethod

Result Model Set Modelextraction

Simulationtime

Worst CaseCorner

pass/failpessimistic

discrete,artificial

easy fastmoderate

StatisticalCorner

pass/failrealistic

discrete,wafer data

complex moderate

Monte Carlo yield mismatch

distribution moderate long

8

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

1 Worst Case Corner Modeling

– MOS transistors (BSIM3V3) wp (fast NMOS, fast PMOS) ws (slow NMOS, slow PMOS) wo (fast NMOS, slow PMOS) wz (slow NMOS, fast PMOS)

– Bipolar (VBIC, SGP) hs (high speed, high beta), lb (low speed, low beta ) hb (low speed, high beta)

– Resistors/Capacitors wp (worst power), ws (worst speed)

– Inductors lq (low q-factor), hq (high q-factor)

wp

ws

Device performance variation is described by SPICE models

LCL UCL

LCL

UCL

9

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Maximization of IDS

Worst Case Corner Models: MOS Transistor

Parameter WP WStox min maxxl min maxxw max minvth0 min maxu0 max minnsub min maxnch min maxrsh min max

Worst Case Power (max. IDS)Worst Case Speed (min. IDS)

20

)(

)(

2vthoVGS

xlL

xwW

tox

uIDS

SPICE parameter limits must correspond to pass/fail MAP parameter limits of the process

A design must only rely on pass/fail parameters

(100 % statistical control)

10

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Design Kit Integration - Corner Analysis Tool

Parametric Corner

Temp. and Supply

Total: 5 x 4 x 3 x 3 =180 parametric corner combinations

(room temp. and typical supply)

11

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Application Corner Simulation

C35, BUF 2, Chain delay

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

delay [pS]rise/ns

fall/ns

rise/ns 58.1 75.0 45.0 122.6 73.2 74.1

fall/ns 86.1 90.0 53.7 148.0 97.8 79.6

measured spectre(tm) spectre(wp) spectre(ws) spectre(wo) spectre(wz)

Digital standard cell (buffer): rise and fall time variation,calculation of derating factors (digital timing model)

12

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

2 Statistical Corner Modeling

– IC-Cap, Non-Parametric Boundary Analysis (D. Stoneking): non-parametric, boundary points in MAP parameter or

SPICE parameter space, multi-variate density estimation

– WiCkeD (MunedaTM): find worst case point of a circuit,analytic linear performance model, linear variance model,parametric density estimation. Application specific (yield optimisation tool)

– Location Depth Corner Models (LDCM): corner points in MAP parameter space, ranking of points (robust in higher dimensions), extension of corner cloud (increase robustness)Enables process modeling for foundry customers

13

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

New Concept: Statistical Corner Models

- Multivariate Ranking Algorithm Determine process corner wafersbased on selected MAP parameter data setCorner = Wafer

- Mapping e2SPICE: Transfer MAP Parameters SPICE Parameters (Wafer Parameters)

fast (moderate number of corner points) and realistic (no artificial correlations introduced) simulation setup for integrated circuits

wp

wo ws

wz

14

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Multivariate Ranking: Location Depth

–Nonparametric approach

–How deep is a data point in the data cloud?

–Allows to identify corner points

–Original idea: J. Tukey (1997)

–Extendable to higher dimensions, no density estimation needed

–Algorithm for higher dimensions:P.J. Rousseeuw and A. Struyf (1998)

θx;#min);θ(

,,...,1;,...,x,,...,θ

1

11

Ti

T

u

ipiip

p

uuiZldepth

nixxZR

15

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Visualization: Location Depth

Example: LEFF variation (NMOS, PMOS)

16

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

The Location Depth Corner Method (LDCM)

MAP Parameter Vectors

Location Depth

Corner Selection

Transformation

Simulation Setup

Select data set of MAP parameter vectors

Compute location depth of parameter vectors

Determine corner vectors (=corner wafers):

Transform MAP to SPICE parameters

)2,1(max ldldi

SPICE models for corner wafers

17

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

LDCM example: Ring Oscillator Delay

- Dataset: n = 48 wafers, BSIM3v3 (NMOS,PMOS):14 statistical parameters12 corner wafers determined 12 SPICE models generated

- Standard worst case limits pessimistic

- Limits of LDCM map range of data set

- Extend corner region:Robustness against moderate process shifts.

LDCM Corner “max”

LDCM Corner “min”

worstpower

worstspeed

18

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Algorithm:

– Draw line from deepest location to each boundary point

– Extend length of line by a factor q

The Extended Location Depth Corner Method (ELDCM)

)()()( wdqwtwt decrext

dldecrb twtwdWw )()(:

– Safety Margin– Robust extension of the simulation region– Extension factor q: Backward validation ( 0.2 .. 0.5 )

19

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

ELDCM example: Ring Oscillator Delay

–NMOS/PMOS transistor models:

BSIM3V3 model (NMOS,PMOS) 14 statistical SPICE parameters12 corner wafers by LDCM

– ELDCM: extension factors q = 0.1, .., 0.5

– Extended corners are in the electrical neighbourhood of original corners

50%10%

20

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Typical Wafer Determination: Deepest Location Depth

– Standard method (univariate):Typical wafer = wafer with MAP parameters (univariate) near centre value (not related to multi-variate distribution).

Misleading design centering ?

– New method (multivariate):Deepest Wafer =wafer with maximum location depth(large data set assumed)

based on multidimensional vector of allrelevant parameters (e.g. m=30)Equivalent to multi-dimensional median.

21

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Design-Framework: CAD Integration

– CadenceTM analog simulation environment

– CadenceTM AffirmaCorner Tool

– Corner definition file generated automatically

Push-Button Solution for Designer

22

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Application: Operational Amplifier

– Standard Library OpAmp (Operational Amplifier)

– Analog performances analyzed:bandwidth, open loop gainphase margin, gain bandwidth

– Dataset: n = 521 wafersm=14 MAP parameters (NMOS, PMOS)Corner determination: md = 10 |Wb| = 17 corner wafers

– Resulting SPICE models:17 Corners, 1 Deepest Wafer Model

23

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Worst Case Models vs. LDCM

24

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Results for ELDCM

25

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

ELDCM: How many corners are needed ?

)()(

)),(()),((

minmax

minmax

allall

dd

ScSc

qmScqmSc

md # Corner Wafers2 45 910 1712 1915 2520 3025 37

Coverage:

17 Corners

26

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

3 Monte Carlo modeling

Typical Mean

SPICE parameters have a global and a local distribution function

STEP 1: Process Variation (Lot Variation)

STEP 2: Mismatch variation (Local variation)

lwσ~,N(~mvth

1

)0_

max)(min,~_ Upvth

VTH = vth_p + vth_m

27

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Monte Carlo Models: Device Correlations

NMOSPMOS

RPOLYcd ~ U(-0.1u,0.1u)Leff = L+ cd, Wpoly = W + cd

=0.6

=0.65

28

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Special Testchip Layout

- Extract parameter variances: ,2TΔVσ

Δθσ

Δθ

Δ

ΔκσΔκ

Δ

ΔσΔ

Δ

Δσ I

III

VVII

II D

D

D

D

TT

D

D

D

D 2

2

2

2

2

2

2

Linear variance model:

Mismatch Modeling

),0(~01 IdD NIII

D

D

I

I - Measurements:

29

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Mismatch Modeling: Extraction results

LWAVT VT /)(

Area Scaling: Pelgrom LawMismatch: NMOS transistor

voltage dependence + area depence

30

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

// format : Spectre (Spectre Direct)// process : C35A3B1,B3C1,B3C3,A4B1,A4C1,B4C3// ----------------------------------------------------------------------// MONTE-CARLO SIMULATION// ----------------------------------------------------------------------inline subckt modnm ( d g s b )parameters w=1.0e-6 l=1.0e-6 nrd=0.0 nrs=0.0 ad=0.0 as=0.0 pd=0.0 ps=0.0 ng=1+ dvthmat=mv_modnm53*(0.92e-08/sqrt(l*w*ng)) dumat=mu_modnm53*(2.3e-7/sqrt(l*w*ng))//nch=npeak46 vth0=6.593e-01+delvton+dvthmat \……….

(Spectre Sub-Circuit):(Spectre Sub-Circuit):

Monte Carlo: Simulator Implementation

Matching

Process Variation

31

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Monte Carlo Simulation - Applications

Offset Simulation (Chopper OpAmp, 0.35 um CMOS)

5GHz Dual Modulus Prescaler ( 0.35 um SiGe ECL)Current through divider

32

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Statistical Analog/Mixed Signal Process Modeling– Close link between process characterisation (SPICE modeling) and fabrication unit (operations)

– Analog device control parameters

– Verified mapping: control parameters - SPICE parameters

– Device control parameters and circuit control parameters (Bandgap, OpAmp, Ring-Oscillators, …)

– Verification: Create SPICE parameters for any wafer, compare simulation results of benchmark design to measurements.

– Continous tracking of process history, ongoing adaption of corner models (windowing).

Simulation follows split (PMOS LDD)

33

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Conclusion

References:

1) E. Stadlober, M. Kocher and G. Rappitsch, “Simulation Models for Robust Design Using Location Depth Methods”, Quality and Reliability Engineering International (QREI), John Wiley&Sons, Vol. 19 - 2003, pp. 317-326, August 2003.

2) D. Stoneking, “Statistical Circuit Design and IC-CAP’s non-parametric boundary analysis”,Solutions from HP Eesof, Vol. 2, No. 2, pp. 1-13, 1997.

3) Kurt J. Antreich, Helmut E. Graeb and Claudia U. Wieser, “Circuit Analysis and Optimization Driven by Worst-Case Distances”. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, 13(1), pp. 57-71, 1994.

– Accurate statistical modeling needs: physical device models, MAP parameters that cover all relevant device performances (e.g. DC, AC, tran)

– Improved statistical modeling needs: control of second order parameters (matching, noise, S-parameters)

– Encourage designers to use the tools Emphasize the importance of Design for Manufacturability

34

stric

tly c

onfid

entia

l cop

yrig

ht ©

2003

aus

triam

icros

yste

ms

AG

Importance of DFM

Statistical ModelingRobust Design