a3 computer architecture - robots.ox.ac.uk

Computer Architecture MT 2011

A3 Computer Architecture

Engineering Science

3rd year A3 Lectures

Prof David Murray

[email protected]/∼dwm/Courses/3CO

Michaelmas 2000

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2: Introduction to the CPU

3A3 Michaelmas 2000

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What is a computation?

Simply the evaluation of some output O, given some input I.O and I are a collections of symbols of some sort— in a binary computer we would have them as strings of 0’s and1’s

Denoting a computation f as O = f (I), it can be broken down intoelemental steps:O1 = f1(I)O2 = f2(O1). . .O = fn(On−1)

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Can everything be computed?

First impose two constraints on a reasonable computing machine

1 It should not “merely” store the answers to all possible problems2 It should not compute at infinite speed.

Godel showed that there were very reasonable questions towhich the reasonable computer could not give answers.

Turing devised a model reasonable computer that he provedcould compute anything that was computable.

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The Turing Machine

Processor R/W Tape

The machine comprises:a sectioned tapea processor — can movetape right or left and canread and write from a finiteset of symbols σ off andonto the tape. Theprocessor itself has a finitenumber of of states s.

With the processor in some state sa, and the symbol σb underthe read/write head, the processor takes one of a finite numberof actions:

f1: write a symbol σc onto the tapef2: move the tape left one sectionf3: move the tape right one sectionf4: halt

and then sets itself into some other state sd .

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The Turing MachineEg adding two numbers:

State Tape f New state Comment

Moving right from

Moving right from

ditto

Replace in middle

Moving left

ditto

Gone too far

Delete leftmost

Halt

s0

s0

s1

s1

s2

s2

s2

s3

s4

s0

s1

s1

s2

s2

s2

s3

s4

s0

R

R

R

L

L

R

H

Before

After

Several things to note here:The notion of storage on the tapeThe notion of processes f — the elemental operationsThe processor has a finite number of states (a fsm)Data on the tape is separate from control processesComputation takes place with symbols

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von Neumann Architecture

The work of Turing and others laid the foundation for thedevelopment of computers in the early 1940’s ...... within the framework of the von Neumann architecture, adigital binary machine with cpu and memory separated by a busalong which data flows.

ALU

Registers

Controller

Central Processor Main Memory

Bus

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Data, Control; what about the program?A Problem: Our computer has to be general purpose, butelectronics have to do something specific ...

The Solution: is to make the control stage run a bland loop ofRTL. The loop

Fetches instructions from memoryExecutes instructions by configuring the data section appropriately.

This set of instructions is the program. So, the program is data— but data which is pulled in to the control section to affect itsoperation.

Registers

Controller

Central Processor Main Memory

Bus

ALU

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Our Bog Standard Architecture

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

Inc(PC)

SPPC

IR(address)

Status

MBR

IR

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Principal Registers on the CPU

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

Inc(PC)

SPPC

IR(address)

Status

MBR

IR

MAR The two memory regis-ters, MAR and MBR, are“gatekeepers” for the twobuses to the memory. TheMemory Address Regis-ter is used to store the ad-dress that is currently be-ing accessed in memory.

MBR The Memory BufferRegister (also sometimescalled the memory dataregister MDR or MD)stores information that isbeing sent to or receivedfrom the memory alongthe data bus.

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Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

Inc(PC)

SPPC

IR(address)

Status

MBR

IR

AC The Accumulator is usedto store data that is be-ing worked on by the ALU,and is the key register inthe data section of thecpu. Notice that the mem-ory can’t access the AC di-rectly. The MBR is an in-termediary.

PC Connected to the ad-dress bus, the ProgramCounter holds the ad-dress in memory of thenext program instruction.Notice that it doesn’tconnect directly to thememory, but must go viathe the MAR.

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Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

Inc(PC)

SPPC

IR(address)

Status

MBR

IR

IR When memory is ad-dressed, the data firstgoes to the MBR. If thedata is an instruction itgets moved to the In-struction Register. Theinstruction register hastwo parts.

1 IR (opcode). The most significant bits of the instruction tell thecpu what to do. IR (opcode) gets decoded and executed by thecontrol unit, CU.

2 IR (address). The least significant bits of the instruction areactually data. They get moved to IR (address). As the namesuggests they (usually) form all or part of an address for later usein the MAR.

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Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

Inc(PC)

SPPC

IR(address)

Status

MBR

IR

SR The Status Register or Condi-tion Control Word or Status Wordis not quite the same as the otherregisters in that it really just acollection of 1bit flags that indi-cate the outcome of operationsthat the ALU has just carried out.There are the Carry C, and Over-flow V flags you have alreadymet, a negative flag N, and azero flag Z. These are monitoredby the CU.

SP The Stack Pointer is connectedto the address bus is used tohold the address of a specialchunk of memory used for tem-porary storage during programexecution. (Lecture 6.)

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CPU Registers are nothing too fancy ...

They are just registers on the CPU

CK

Q3 Q2 Q1 Q0

D3 D2 D1 D0

QD QD QD QD

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CU and ALU

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

Inc(PC)

SPPC

IR(address)

Status

MBR

IR

CU The Control Unit is the nerve cen-tre of the cpu, responsible for the tim-ing and execution of the various reg-ister transfers required to fulfill an in-struction held in the IR. It has a num-ber of control lines coming out of it,which transmit CSL and CSP levelsand pulses to the various registers andlogic units.

ALU The Arithmetic Logic Unit is where bit crunching iscarried out. It is responsible for bit operations on data heldin the AC and MBR and for storing the results. We shallsee that is contains arithmetic adders, logical OR-ers andso on.

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Main memory.

The memory comprises mostly RAM with some ROM.It is not on the the cpu chip, but is connected to the cpu viatwo buses, the data bus and the address bus.

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

Inc(PC)

SPPC

IR(address)

Status

MBR

IR

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Buses

The buses carry words of information which are many bits wide.The data bus

The data bus width ranges from 4bits for the simplest controlmicroprocessor to 64bits the most sophisticated cpu.The width in the standard desktop micro has increased from 8bits,through 16bits and is now 32bits.Register and bus widths are same ideally, but this is sometimes notthe case. (Recall 386’s — 32bit cpu sitting on a 16bit bus)

Address BusSends memory addresses to memory.No need to have same width as the data bus.Again the size has increased — figures between 24 and 32 arenow commonplace.

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Some important points ...

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

Inc(PC)

SPPC

IR(address)

Status

MBR

IR

Our architecture is a muchsimplified version of thereal thing. However, noneof the principle has beenlost.We will sometimes choosespecific widths for variousbuses and registers.

Eg, we shall often assumethat the data bus is 16bits(= 2Bytes) wide. All theregisters on the data sideare 16bits wide, except theIR. The IR (opcode) partshould be wide enough totake the largest opcode.We assume the opcode isa fixed 8bits wide. The IR(address) part has to havethe same width as theaddress bus. We shall usean address bus which is24bits wide, so the MAR,IR (address) PC and SPare 24 bits wide.

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The overall aim is simply ...

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

Inc(PC)

SPPC

IR(address)

Status

MBR

IR

to move information frommemory to registerto move it betweenregisterssometimes pass it throughthe ALU

and then to stuff it backinto the memory all insome nicely orderedsequenceHelpful analogy? We wantto play trains with chunksof information.We, or rather the controlsection, needs to set thepoints so that theinformation is correctlyrouted.

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Instruction Fetch: Step 1

To start, an instruction has to be read from memory.

Instruction Fetch: step 1

The PC is the important register in fetching the instruction.It holds the address of the next program instruction in memory.It is said to point to the next instruction. (Any memory addresspoints to the memory contents at that address.)Remember though that the memory address register acts as agatekeeper to the memorySo! the first thing to happen is that the program counter getscopied into the memory address register.Using RTL we have

MAR←PC

Remember that this transfer leaves PC unaltered.

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MAR←PC

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

SPPC

IR(address)

Status

MBR

IR

Inc(PC)

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Instruction Fetch: step 2

Now we read the memory.MBR←〈MAR 〉

where 〈x 〉 denotes the contents pointed to by x.

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

SPPC

IR(address)

Status

MBR

IR

Inc(PC)

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Instruction Fetch: Step 3The next step is to move the instruction to the instruction register.

IR←MBR

In the BSA, IR is split into two parts, IR (opcode) and IR(address). As far as the instruction fetch is concerned it the IR(opcode) that is important. The opcode is decoded by the controlunit

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

SPPC

IR(address)

Status

MBR

IR

Inc(PC)

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Memory

MAR

ALU

CUAC

Control Lines

SPPC

IR(address)

Status

MBR

IR

Inc(PC)

IR(opcode)

Finally we do a touch ofhousekeeping. It is areasonable assumptionthat the next instructionthe cpu will fetch is in thenext memory location, sothe program counter isincremented.PC←PC + 1NB This incrementation isin units of the memoryword length.

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The Instruction Fetch

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

SPPC

IR(address)

Status

MBR

IR

Inc(PC) SummaryMAR ← PCMBR ← MAR

IR ← MBR; PC←PC + 1decode IR (opcode)

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The example instruction setWe give a few members of a model instruction set usingAssembler Language mnemonics, together with overall RTL-ishdescription and binary value of the opcode.

Instruction Description Opcode MeaningLDA x AC←〈x 〉 00000000 Load the accumulator with contents of xSTA x 〈x 〉 ←AC 00000001 Store accumulator in memory at address xADD x AC←AC + 〈x 〉 00000010 Add mem contents at x to ACAND x AC =AC ∧ 〈x 〉 00000011 Logical and ...JMP x PC←x 00000100 Jump to instruction at xBEQ x if Z-flag=1 then PC←x 00000101 if Z-flag is set then jumpCMP AC←AC 00000110 Two’s complement the ACRSH AC←RightShift(AC) 00000111 Shift the AC 1bit to right

Assembler Language is a language designed around a particularcpu, and so there is no standard set of mnemonics.However, once you understand the purpose of the instructions, itis trivial to convert between languages.For example, the above set is similar to those you will use on a6502 cpu on the computing lab course, but had we chosen to useMotorola 68000 assembler we would use the following.

6502 MC680000 MeaningLDA x MOVE x,D0 Load the accumulator (D0) with contents of xSTA x MOVE D0,x Store accumulator in memory at address xADD x ADD x,D0 Add mem contents at x to ACAND x AND x,D0 Logical and ...JMP x JMP x Jump to instruction at xBEQ x BEQ x if Z-flag is set then jumpetc

Note, that you do not have to learn a specific assemblerlanguage, but you should feel comfortable with the interpretationof any.

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Executing an instruction

Let us look at LDA x . The opcode is %00000000. During theinstruction fetch this opcode gets places in the IR (opcode), andis decoded by the control unit (CU).

The CU then tweaks its output control lines to effect the desiredthe register transfers etc.

Its action is to copy the contents of memory at address x into theaccumulator. The variable x is called the operand. At its simplestin our BSA, the operand comprises the remaining 8 bits of the 16bit instruction after removing the 8 bit opcode. These are the 8bits in IR (address).In detail:

LDA xMAR ← IR (address)MBR ← 〈MAR 〉

AC ← MBR

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Example of LDA

LDA xMAR ← IR (address)MBR ← 〈MAR 〉

AC ← MBR

Memory

MAR

ALU

CUAC

Control Lines

IR(opcode)

SPPC

IR(address)

Status

MBR

IR

Inc(PC)

Note that no computation has been done by this instruction.Information has been moved around, from memory toaccumulator, but not altered. The only part of the cpu that canalter data is the ALU.

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Example of LDA

The figure gives an example of the information flows in the entirefetch and execute of LDA x , where we assume that an 8bitoperand is sufficient. It starts with PC =2.

0

1

2

3

4

5

PC=3

INC

PC=2 MAR=2

MAR=5

a b

e2

f

c c00000000 00000101

00000000

00000010 00001111

MBR

AC=527 dec

00000101

00000010 00001111

MBR

g

AC<−MBR

h

Memory

0000010100000000

IR(opcode) IR(address)

LDA x d

So, MAR<−IR(address)

e1

MBR<−M<MAR>

AC<−MBR

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Lengths of operandsA ProblemAt its simplest in our standard architecture, the operandcomprises the least significant 8bits originally in the MBR andthen transferred to IR (address) at the same time that the mostsignificant bits were transferred to IR (opcode).But this appears to restrict operands in general to 8 bits, and torestrict the available range of addresses to 0–255 — which isobviously non-sensical, given that the address bus is 24bits wide!

A SolutionIn our architecture the obvious solution is to make the LDAinstruction read the next word of memory into the MBR, and theninto the IR (address), building up a 24 bit address for transferralto the MAR.The detail of this step is often missed out in the ‘simplified’explanations given in books, and the recommended text is noexception. It is just assumed in the first line of the execute phasethat the operand in IR (address) has the required length.

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Lengths of operands/ ctd

The reason for this sleight is to avoid blurring the distinctionbetween instruction fetch and instruction execute.

Clearly, because many instructions don’t require long operands itwould be very wasteful if every instruction had to make an extramemory read to generate a redundant 24bit operand. This couldbe solved by opcodes containing a bit that indicated that a futherread should be made to complete the operand.

Unfortunately it then appears that part of the instruction executephase is being used to complete the instruction fetch, andimmediately the neat distinction is lost.

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Summary: We have seen ...

1 that computation required transferring wordsfrom memory to registerbetween registerssometimes via the ALUthen back to memory.

2 how transfers of information in our BSA could be described usingassembler mnemonics which described several lines of RTL

3 how the Instruction Fetch sequence was described, and how theLDA operation was executed.

4 an 8-membered toy instruction set

5 that the Control Unit (CU) is responsible for generating the CSLsand CSPs

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