a/d converter control
DESCRIPTION
A/D Converter Control. Discussion D8.6. Analog-to-Digital Converters. Converts analog signals to digital signals 8-bit: 0 – 255 10-bit: 0 – 1023 12-bit: 0 – 4095 Successive Approximation. Method of Successive Approximation. Implementing Successive Approximation. - PowerPoint PPT PresentationTRANSCRIPT
A/D ConverterControl
Discussion D8.6
Analog-to-Digital Converters
• Converts analog signals to digital signals– 8-bit: 0 – 255– 10-bit: 0 – 1023– 12-bit: 0 – 4095
• Successive Approximation
Method of Successive Approximation
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
Control
D/A Converter
V
V
in
DA
Binary OutputC+
-
Implementing Successive Approximation
Control
D/A Converter
V
V
in
DA
Binary OutputC+
-
Implementing Successive Approximation
2R
2R
2R
2R
2R
R
R
R
VB3
B2
B1
B0
ControlUnit Datapath
sarCPLD
Vin
gt
adstart
adflg adreg
Analog in
Digital out
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
2R
2R
2R
2R
2R
R
R
R
VB3
B2
B1
B0
ControlUnit Datapath
sarCPLD
Vin
gt
adstart
adflg adreg
Analog in
Digital out
A/D CPLD Control
DatapathControl Unit
done
clr clk reset clk
sarld
adreg[3:0]
sar[3:0]
adld
sh
adstart
gt
msel
DatapathControl Unit
done
clr clk reset clk
sarld
adreg[3:0]
sar[3:0]
adld
sh
adstart
gt
msel
Use Mealy Machine
Inputs to C1:adstart, gt, done
Outputs from C2:sarald, sh, adld, msel
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
egis
ter
C1
C2
2R
2R
2R
2R
2R
R
R
R
VB3
B2
B1
B0
ControlUnit Datapath
sarCPLD
Vin
gt
adstart
adflg adreg
Analog in
Digital out
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
A/D Control Unit
sarReg
sarReg
Done
clk
msel
resetsarld maskR
clk
resetsh
clk
resetadld
adreg
mux1
sarin
SARmask
A B
hex7seg
AtoG[6:0]
LEDR[3:0]
LEDR[7:4]
LEDG[3:0]LEDG[7:4]
SW[7]
SW[6] SW[5]
SW[4]
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
A Mealy state machine
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
eg
iste
r
C1
C2
ADctl adflg = done;msel = ~gt;adld = done;sarld = ~done;sh = ~done;
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
sarReg
sarReg
Done
clk
msel
resetsarld maskR
clk
resetsh
clk
resetadld
adreg
mux1
sarin
SARmask
A B
hex7seg
AtoG[6:0]
LEDR[3:0]
LEDR[7:4]
LEDG[3:0]LEDG[7:4]
SW[7]
SW[6] SW[5]
SW[4]
DatapathControl Unit
done
clr clk reset clk
sarld
adreg[3:0]
sar[3:0]
adld
sh
adstart
gt
msel
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
A Mealy state machine
Use one-hot encoding: one flip-flop per state
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
egis
ter
C1
C2
module DFF (D, clk, clr, Q);
input clk, clr ;wire clk, clr ;input D ;wire D ;
output Q ;reg Q ;
always @(posedge clk or posedge clr)if(clr == 1)
Q <= 0;else
Q <= D;endmodule
CLK
D Q
~Qclk
D Q
clr
DFF
module DFF1 (D, clk, reset, Q);
input clk, reset;wire clk, reset ;input D ;wire D ;
output Q ;reg Q ;
always @(posedge clk or posedge reset)if(reset == 1)
Q <= 1;else
Q <= D;endmodule
CLK
D Q
~Qclk
D Q
reset
DFF1
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
eg
iste
r
C1
C2
// adconv controlmodule ADctrl(Clk, Clear, gt, adstart, done, msel, sarld, sh,
adld, adflg); input Clk, Clear, gt, adstart, done;
output msel, sarld, sh, adld, adflg;wire msel, sarld, sh, adld, adflg;
wire start, keep, remove; wire startD, keepD, removeD;
assign startD = start & ~adstart | keep & done | remove & done;assign keepD = start & adstart & gt | keep & gt & ~done
| remove & gt & ~done;assign removeD = start & adstart & ~gt | keep & ~gt & ~done
| remove & ~gt & ~done;
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
DFF1 startFF(.D(startD), .clk(Clk), .reset(Clear), .Q(start));DFF keepFF(.D(keepD), .clk(Clk), .clr(Clear), .Q(keep));DFF removeFF(.D(removeD), .clk(Clk), .clr(Clear), .Q(remove));
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)S
tate
Reg
iste
r
C1
C2
// C2 Outputsassign adflg = done;assign msel = ~gt;assign adld = done;assign sarld = ~done & keep | ~done & remove | adgo & start;assign sh = ~done & keep | ~done & remove | adgo & start;
endmodule
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
eg
iste
r
C1
C2
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
// Title : A/D convertermodule adconv(clock, clear, adstart, gt, adflg, sar, adreg); input clock, clear, adstart, gt; output adflg; output [3:0] sar, adreg; wire adflg, msel, sarld, adld, sh, done; wire [3:0] sar, adreg;
ADpath adc1(.clk(clock),.reset(clear),.msel(msel),.sh(sh),.sarld(sarld),.adld(adld),.sar(sar),.ADR(adreg),.done(done));
ADctrladc2(.Clk(clock),.Clear(clear),.gt(gt),.adstart(adstart),.done(done),.msel(msel),.sarld(sarld),.sh(sh),.adld(adld), .adflg(adflg));
endmodule
DatapathControl Unit
done
clr clk reset clk
sarld
adreg[3:0]
sar[3:0]
adld
sh
adstart
gt
msel
A Mealy state machine
Use binary encoding: two flip-flops
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
egis
ter
C1
C2
// adconv controlmodule ADctrl(Clk, Clear, gt, adstart, zero, msel, sarld, sh, adld, adflg); input Clk, Clear, gt, adstart, zero; output msel, sarld, sh, adld, adflg; reg msel, sarld, sh, adld, adflg; reg[2:0] present_state, next_state; parameter start = 2'b00, keep = 2'b01, remove = 2'b11;
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
always @(posedge Clk or posedge Clear) begin if (Clear == 1) present_state <= start; else present_state <= next_state; end
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)S
tate
Re
gis
ter
C1
C2
always @(present_state or adstart or gt or done)begin case(present_state) start: if(adstart == 1)
next_state <= load; else if(gt == 1)
next_state <= keep; else next_state <= remove;
keep: if(done == 1) next_state <= start; else if(gt == 1)
next_state <= keep; else next_state <= remove;
remove: if(done == 1) next_state <= start; else if(gt == 1)
next_state <= keep; else next_state <= remove;
default next_state <= start; endcaseend
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
sarReg
sarReg
Done
clk
msel
resetsarld maskR
clk
resetsh
clk
resetadld
adreg
mux1
sarin
SARmask
A B
hex7seg
AtoG[6:0]
LEDR[3:0]
LEDR[7:4]
LEDG[3:0]LEDG[7:4]
SW[7]
SW[6] SW[5]
SW[4]
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
eg
iste
r
C1
C2
// C2 Outputsassign adflg = done;assign msel = ~gt;assign adld = done;assign sarld = ~done & keep | ~done & remove | adgo & start;assign sh = ~done & keep | ~done & remove | adgo & start;
endmodule
2R
2R
2R
2R
2R
R
R
R
VB3
B2
B1
B0
ControlUnit Datapath
sarCPLD
Vin
gt
adstart
adflg adreg
Analog in
Digital out
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
A/D Control Unit
sarReg
sarReg
Done
clk
msel
resetsarld maskR
clk
resetsh
clk
resetadld
adreg
mux1
sarin
SARmask
A B
hex7seg
AtoG[6:0]
LEDR[3:0]
LEDR[7:4]
LEDG[3:0]LEDG[7:4]
SW[7]
SW[6] SW[5]
SW[4]
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
// Title : A/D convertermodule adconv(clock, clear, adstart, gt, adflg, sar, adreg); input clock, clear, adstart, gt; output adflg; output [3:0] sar, adreg; wire adflg, msel, sarld, adld, sh, done; wire [3:0] sar, adreg;
ADpath adc1(.clk(clock),.reset(clear),.msel(msel),.sh(sh),.sarld(sarld),.adld(adld),.sar(sar),.ADR(adreg),.done(done));
ADctrl adc2(.Clk(clock),.Clear(clear),.gt(gt),.adstart(adstart),
.done(done),.msel(msel),.sarld(sarld),.sh(sh),
.adld(adld), .adflg(adflg));
endmodule
DatapathControl Unit
done
clr clk reset clk
sarld
adreg[3:0]
sar[3:0]
adld
sh
adstart
gt
msel
