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14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual

Analog-to-Digital Converter

AD9648

Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or otherrights of third parties that may result from its use. Specifications subject to change without notice. Nolicense is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A

Tel: 781.329.4700 www.analog.comFax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved

FEATURES

1.8 V analog supply operation

1.8 V CMOS or LVDS outputs

SNR = 74.5 dBFS @ 70 MHz

SFDR = 91 dBc @ 70 MHz

Low power: 78 mW/channel ADC core @ 125 MSPS

Differential analog input with 650 MHz bandwidth

IF sampling frequencies to 200 MHz

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = 0.35 LSB

Serial port control options

Offset binary, gray code, or twos complement data format

Optional clock duty cycle stabilizerInteger 1-to-8 input clock divider

Data output multiplex option

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data

alignment

APPLICATIONSCommunications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMAI/Q demodulation systems

Smart antenna systems

Broadband data applications

Battery-powered instruments

Hand held scope meters

Portable medical imaging

Ultrasound

Radar/LIDAR

1This product is protected by a U.S patent.

FUNCTIONAL BLOCK DIAGRAM

VIN+A

VINA

VREF

SENSE

VCM

RBIAS

VINB

VIN+B

ORA

D0A

D13A

DCOA

DRVDD

ORB

D13B

D0B

DCOB

SDIOAGNDAVDD SCLK

SPI

PROGRAMMING DATA

MUXOPTION

PDWN DFSCLK+ CLK

MODECONTROLS

DCS

DUTY CYCLESTABILIZER

SYNC

DIVIDE1 TO 8

OEB

CSB

REFSELECT

ADC

CMOS/LVDS

OUTPUT

BUFFER

ADC

CMOS/LVDS

OUTPUTBUFFER

AD9648

0 9 9 7 5 0 0 1NOTES

1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;SEE FIGURE 7 FORLVDS PIN NAMES.

Figure 1.

PRODUCT HIGHLIGHTS

1. TheAD96481operates from a single 1.8 V analogpower supply and features a separate digital output

driver supply to accommodate 1.8 V CMOS or LVDS

logic families.

2. The patented sample-and-hold circuit maintainsexcellent performance for input frequencies up to

200 MHz and is designed for low cost, low power, and

ease of use.

3. A standard serial port interface supports variousproduct features and functions, such as data output

formatting, internal clock divider, power-down,

DCO/data timing and offset adjustments.

4. TheAD9648is packaged in a 64-lead RoHS compliantLFCSP that is pin compatible with theAD9650/

AD9269/AD926816-bit ADC, theAD9258 14-bit

ADC, theAD9628/AD9231 12-bit ADCs, and the

AD9608/AD9204 10-bit ADCs, enabling a simple

migration path between 10-bit and 16-bit converters

sampling from 20 MSPS to 125 MSPS.
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Rev. 0 | Page 2 of 44

TABLE OF CONTENTSFeatures .............................................................................................. 1Applications ....................................................................................... 1Functional Block Diagram .............................................................. 1Product Highlights ........................................................................... 1Revision History ............................................................................... 2General Description ......................................................................... 3Specifications ..................................................................................... 4

DC Specifications ........................................................................... 4AC Specifications ........................................................................... 5Digital Specifications ................................................................... 6Switching Specifications ................................................................ 8Timing Specifications .................................................................. 9

Absolute Maximum Ratings .......................................................... 12Thermal Characteristics ............................................................ 12ESD Caution ................................................................................ 12

Pin Configurations and Function Descriptions ......................... 13Typical Performance Characteristics ........................................... 19

AD9648-125 ................................................................................ 20AD9648-105 ................................................................................ 22

Equivalent Circuits ......................................................................... 24Theory of Operation ...................................................................... 25

ADC Architecture ...................................................................... 25Analog Input Considerations .................................................... 25

Voltage Reference ....................................................................... 27Clock Input Considerations ...................................................... 28Channel/Chip Synchronization ................................................ 30Power Dissipation and Standby Mode .................................... 30Digital Outputs ........................................................................... 31Timing ......................................................................................... 31

Built-In Self-Test (BIST) and Output Test .................................. 32Built-In Self-Test (BIST) ............................................................ 32Output Test Modes ..................................................................... 32

Serial Port Interface (SPI) .............................................................. 33Configuration Using the SPI ..................................................... 33Hardware Interface ..................................................................... 34Configuration Without the SPI ................................................ 34SPI Accessible Features .............................................................. 34

Memory Map .................................................................................. 35Reading the Memory Map Register Table ............................... 35Memory Map Register Table ..................................................... 36Memory Map Register Descriptions ........................................ 39

Applications Information .............................................................. 41Design Guidelines ...................................................................... 41

Outline Dimensions ....................................................................... 42Ordering Guide .......................................................................... 42

REVISION HISTORY

7/11Revision 0: Initial Version

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AD9648


GENERAL DESCRIPTIONTheAD9648is a monolithic, dual-channel, 1.8 V supply, 14-bit,

105 MSPS/125 MSPS analog-to-digital converter (ADC). It

features a high performance sample-and-hold circuit and on-

chip voltage reference.

The product uses multistage differential pipeline architecture

with output error correction logic to provide 14-bit accuracy at

125 MSPS data rates and to guarantee no missing codes over the

full operating temperature range.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom

user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles.

An optional duty cycle stabilizer (DCS) compensates for wide

variations in the clock duty cycle while maintaining excellent

overall ADC performance.

The digital output data is presented in offset binary, Gray code, or

twos complement format. A data output clock (DCO) is provided

for each ADC channel to ensure proper latch timing with receiving

logic. Output logic levels of 1.8 V CMOS or LVDS are supported.

Output data can also be multiplexed onto a single output bus.

TheAD9648is available in a 64-lead RoHS compliant LFCSP and

is specified over the industrial temperature range (40C to

+85C). This product is protected by a U.S. patent.
http://www.analog.com/AD9648http://www.analog.com/AD9648http://www.analog.com/AD9648http://www.analog.com/AD9648http://www.analog.com/AD9648http://www.analog.com/AD9648http://www.analog.com/AD9648http://www.analog.com/AD9648

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SPECIFICATIONSDC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless

otherwise noted.

Table 1.

AD9648-105 AD9648-125

Parameter Temp Min Typ Max Min Typ Max Unit

RESOLUTION Full 14 14 Bits

ACCURACY

No Missing Codes Full Guaranteed Guaranteed

Offset Error Full 0.8 0.3 +0.2 0.8 0.3 +0.2 % FSR

Gain Error Full 4.20 1.3 +4.2 5.1 1.3 +5.1 % FSR

Differential Nonlinearity (DNL)1 Full 0.5 +1.2 0.5 +1.2 LSB

25C 0.5 0.5 LSB

Integral Nonlinearity (INL)1 Full 2.3 +2.3 2.3 +2.3 LSB

25C 1.0 1.0 LSB

MATCHING CHARACTERISTICOffset Error Full 0.01 0.58 0.01 0.58 % FSR

Gain Error Full 0.5 4.0 0.5 4.0 % FSR

TEMPERATURE DRIFT

Offset Error Full 2 2 ppm/C

Gain Error Full 50 50 ppm/C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) Full 0.98 1.00 1.02 0.98 1.00 1.02 V

Load Regulation Error at 1.0 mA Full 2 2 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25C 0.98 0.98 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 V p-pInput Capacitance2 Full 5 5 pF

Input Resistance (Differential) Full 7.5 7.5 k

Input Common-Mode Voltage Full 0.9 0.9 V

Input Common-Mode Range Full 0.5 1.3 0.5 1.3 V

POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V

DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

IAVDD1 Full 81 86 95 100 mA

IDRVDD (1.8 V CMOS)1 Full 19.2 22.5 mA

IDRVDD(1.8 V LVDS)1 Full 63.5 65.0 mA

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AD9648-105 AD9648-125


POWER CONSUMPTION

DC Input Full 135.4 155.5 mW

Sine Wave Input (DRVDD = 1.8 V CMOSOutput Mode)

Full 172.3 181.3 202.5 211.5 mW

Sine Wave Input (DRVDD = 1.8 V LVDSOutput Mode)

Full 180.4 189.4 211.5 220.5 mW

Standby Power3 Full 108 120 mW

Power-Down Power Full 2.0 2.0 mW

1 Measure with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.2 Input capacitance refers to the effective capacitance between one differential input pin and AGND.3 Standby power is measured with a dc input and with the CLK pins active (1.8 V CMOS mode).

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless

otherwise noted.

Table 2.AD9648-105 AD9648-125

Parameter1 Temp Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 9.7 MHz 25C 75.4 75.0 dBFS

fIN = 30.5 MHz 25C 75.2 74.7 dBFS

fIN = 70 MHz 25C 74.8 74.5 dBFS

Full 73.8 73.0 dBFS

fIN = 100 MHz 25C 73.8 73.9 dBFS

fIN = 200 MHz 25C 71.0 71.5 dBFS

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 9.7 MHz 25C 74.3 73.9 dBFS

fIN

= 30.5 MHz 25C 74.0 73.4 dBFS

fIN = 70 MHz 25C 73.4 73.3 dBFS

Full 73.0 72.8 dBFS

fIN = 100 MHz 25C 72.8 72.8 dBFS

fIN = 200 MHz 25C 69.6 70.3 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25C 12.0 11.9 Bits

fIN = 30.5 MHz 25C 12.0 11.9 Bits

fIN = 70 MHz 25C 11.8 11.8 Bits

fIN = 100 MHz 25C 11.8 11.8 Bits

fIN = 200 MHz 25C 11.3 11.4 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 9.7 MHz 25C 98 96 dBc

fIN = 30.5 MHz 25C 90 90 dBcfIN = 70 MHz 25C 93 91 dBc

Full 86 82 dBc

fIN = 100 MHz 25C 92 90 dBc

fIN = 200 MHz 25C 81 84 dBc

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AD9648-105 AD9648-125

Parameter1 Temp Min Typ Max Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25C 98 96 dBc

fIN = 30.5 MHz 25C 90 90 dBc

fIN = 70 MHz 25C 93 91 dBc

Full 86 82 dBc

fIN = 100 MHz 25C 92 90 dBc

fIN = 200 MHz 25C 81 84 dBc

WORST OTHER (HARMONIC OR SPUR)

fIN = 9.7 MHz 25C 98 97 dBc

fIN = 30.5 MHz 25C 96 97 dBc

fIN = 70 MHz 25C 96 97 dBc

Full 91 90 dBc

fIN = 100 MHz 25C 92 92 dBc

fIN = 200 MHz 25C 90 90 dBc

TWO-TONE SFDR

fIN = 29 MHz (7 dBFS ), 32 MHz (7 dBFS ) 25C 84 84 dBc

CROSSTALK2 Full 95 95 dBANALOG INPUT BANDWIDTH 25C 650 650 MHz

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.2 Crosstalk is measured at 100 MHz with 1.0 dBFS on one channel and no input on the alternate channel.

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS diferential input, 1.0 V internal reerence, and DCS enabled, unless

otherwise noted.

Table 3.

AD9628-105/125

Parameter Temp Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK)Logic Compliance CMOS/LVDS/LVPECL

Internal Common-Mode Bias Full 0.9 V

Differential Input Voltage Full 0.3 3.6 V p-p

Input Voltage Range Full AGND - 0.3 AVDD + 0.2 V

Input Common-Mode Range Full 0.9 1.4 V

High Level Input Current Full 10 +10 A

Low Level Input Current Full 10 +10 A

Input Capacitance Full 4 pF

Input Resistance Full 8 10 12 k

LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 DRVDD + 0.2 V

Low Level Input Voltage Full 0 0.6 VHigh Level Input Current Full 10 +10 A

Low Level Input Current Full 40 132 A

Input Resistance Full 26 k


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Parameter Temp Min Typ Max Unit

LOGIC INPUT (SCLK/DFS/SYNC)2


Low Level Input Voltage Full 0 0.6 V

High Level Input Current (VIN = 1.8 V) Full 92 135 A




LOGIC INPUT/OUTPUT (SDIO/DCS)1


Low Level Input Voltage Full 0 0.6 V

High Level Input Current Full 10 +10 A

Low Level Input Current Full 38 128 A



LOGIC INPUTS (OEB, PDWN)2


Low Level Input Voltage Full 0 0.6 VHigh Level Input Current (VIN = 1.8 V) Full 90 134 A




DIGITAL OUTPUTS

CMOS ModeDRVDD = 1.8 V

High Level Output Voltage

IOH = 50 A Full 1.79 V

IOH = 0.5 mA Full 1.75 V

Low Level Output Voltage

IOL = 1.6 mA Full 0.2 V

IOL = 50 A Full 0.05 V

LVDS ModeDRVDD = 1.8 V

Differential Output Voltage (VOD), ANSI Mode Full 290 345 400 mV

Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V

Differential Output Voltage (VOD), Reduced Swing Mode Full 160 200 230 mV

Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V

1 Pull up.2 Pull down.

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SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless

otherwise noted.

Table 4.

AD9648-105 AD9648-125


CLOCK INPUT PARAMETERS

Input Clock Rate Full 1000 1000 MHz

Conversion Rate1

DCS Enabled Full 20 105 20 125 MSPS

DCS Disabled Full 10 105 10 125 MSPS

CLK PeriodDivide-by-1 Mode (tCLK) Full 9.52 8 ns

CLK Pulse Width High (tCH) Full 4.76 4 ns

Aperture Delay (tA) Full 1.0 1.0 ns

Aperture Uncertainty (Jitter, tJ) Full 0.07 0.07 ps rms

DATA OUTPUT PARAMETERS

CMOS Mode (DRVDD = 1.8 V)

Data Propagation Delay (tPD) Full 1.8 2.9 4.4 1.8 2.9 4.4 nsDCO Propagation Delay (tDCO)

2 Full 2.0 3.1 4.4 2.0 3.1 4.4 ns

DCO to Data Skew (tSKEW) Full 1.2 0.1 +1.0 1.2 0.1 +1.0 ns

LVDS Mode (DRVDD = 1.8 V)

Data Propagation Delay (tPD) Full 2.4 2.4 ns

DCO Propagation Delay (tDCO)2 Full 2.4 2.4 ns

DCO to Data Skew (tSKEW) Full 0.20 +0.03 +0.25 0.20 +0.03 +0.25 ns

CMOS Mode Pipeline Delay (Latency) Full 16 16 Cycles

LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 16/16.5 16/16.5 Cycles

Wake-Up Time (Power Down)3 Full 350 350 s

Wake-Up Time (Standby) Full 250 250 ns

Out-of-Range Recovery Time Full 2 2 Cycles

1

Conversion rate is the clock rate after the divider.2 Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Table 18).3 Wake-up time is defined as the time required to return to normal operation from power-down mode.

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TIMING SPECIFICATIONS

Table 5.

Parameter Description Limit Unit

SYNC TIMINGREQUIREMENTS

tSSYNC SYNC to rising edge of CLK+ setup time 0.24 ns typ

tHSYNC SYNC to rising edge of CLK+ hold time 0.40 ns typ

SPI TIMINGREQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns min

tDH Hold time between the data and the rising edge of SCLK 2 ns min

tCLK Period of the SCLK 40 ns min

tS Setup time between CSB and SCLK 2 ns min

tH Hold time between CSB and SCLK 2 ns min

tHIGH SCLK pulse width high 10 ns min

tLOW SCLK pulse width low 10 ns min

tEN_SDIO Time required for the SDIO pin to switch from an input to an output relativeto the SCLK falling edge

10 ns min

tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relativeto the SCLK rising edge

10 ns min

Timing Diagrams

tPD

tSKEW

tCH

tDCO

tCLK

N 16N 17

N 1

N + 1 N + 2

N + 3

N + 5

N + 4

N

N 15 N 14 N 13 N 12

VIN

CLK+

CLK

CH A/CH B DATA

DCOA/DCOB

tA

09975-002

Figure 2. CMOS Default Output Mode Data Output Timing

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tPD

tSKEW

tCH

tDCO

tCLK

CH AN 16

CH BN 15

CH AN 14

CH BN 13

CH AN 12

CH BN 11

CH AN 10

CH BN 9

CH AN 8

N 1

N + 1 N + 2

N + 3

N + 5

N + 4

N

VIN

CLK+

CLK

CH A DATA

DCOA/DCOB

tA

CH B DATACH BN 16

CH AN 15

CH BN 14

CH AN 13

CH BN 12

CH AN 11

CH BN 10

CH AN 9

CH BN 8

09975-003

Figure 3. CMOS Interleaved Output Mode Data Output Timing

tPD

tSKEW

tCH

tDCO

tCLK

CH AN 12

CH BN 12

CH AN 11

CH BN 11

CH AN 10

CH BN 10

CH AN 9

CH BN 9

CH AN 8

N 1

N + 1 N + 2

N + 3

N + 5

N + 4

N

VIN

CLK+

CLK

DCO+

DCO

D0+ (LSB)

PARALLELINTERLEAVED

MODE

D0 (LSB)

D13+ (MSB)

D13 (MSB)

tA

CH AN 12

CH BN 12

CH AN 11

CH BN 11

CH AN 10

CH BN 10

CH AN 9

CH BN 9

CH AN 8

CHA0N 12

CHA1N 12

CHA0N 11

CHA1N 11

CHA0N 10

CHA1N 10

CHA0N 9

CHA1N 9

CHA0N 8

D1+/0+ (LSB)CHANNEL

MULTIPLEXEDMODE

CHANNEL A

D1/D0 (LSB)

D13+/D12+ (MSB)

D13/D12 (MSB)

CHA12N 12

CHA13N 12

CHA12N 11

CHA13N 11

CHA12N 10

CHA13N 10

CHA12N 9

CHA13N 9

CHA12N 8

CH B0N 12

CH B1N 12

CH B0N 11

CH B1N 11

CH B0N 10

CH B1N 10

CH B0N 9

CH B1N 9

CH B0N 8

D1+/D0+ (LSB)CHANNEL

MULTIPLEXEDMODE

CHANNEL B

D1/D0 (LSB)

D13+/D12+ (MSB)

D13/D12 (MSB)

CH B12N 12

CH B13N 12

CH B12N 11

CH B13N 11

CH B12N 10

CH B13N 10

CHA12N 9

CHA13N 9

CHA12N 8

09975-004

Figure 4. LVDS Modes for Data Output Timing

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SYNC

CLK+

tHSYNCtSSYNC

09975-

005

Figure 5. SYNC Input Timing Requirements

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ABSOLUTE MAXIMUM RATINGSTable 6.

Parameter Rating

Electrical1

AVDD to AGND 0.3 V to +2.0 V

DRVDD to AGND 0.3 V to +2.0 V

VIN+A/VIN+B, VINA/VINB to AGND 0.3 V to AVDD + 0.2 V

CLK+, CLK to AGND 0.3 V to AVDD + 0.2 V

SYNC to AGND 0.3 V to AVDD + 0.2 V

VCM to AGND 0.3 V to AVDD + 0.2 V

RBIAS to AGND 0.3 V to AVDD + 0.2 V

CSB to AGND 0.3 V to DRVDD + 0.2 V

SCLK/DFS to AGND 0.3 V to DRVDD + 0.2 V

SDIO/DCS to AGND 0.3 V to DRVDD + 0.2 V

OEB 0.3 V to DRVDD + 0.2 V

PDWN 0.3 V to DRVDD + 0.2 V

D0A/D0B through D13A/D13B to

AGND0.3 V to DRVDD + 0.2 V

DCOA/DCOB to AGND 0.3 V to DRVDD + 0.2 VEnvironmental

Operating Temperature Range(Ambient)

40C to +85C

Maximum Junction TemperatureUnder Bias

150C

Storage Temperature Range(Ambient)

65C to +150C

1 The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) +0.2 V but should not exceed 2.1 V.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for

the LFCSP package. Soldering the exposed paddle to the PCB

increases the reliability of the solder joints and maximizes the

thermal capability of the package.

Table 7. Thermal Resistance

Package Type

AirflowVelocity(m/sec) JA

1, 2 JC1, 3 JB

1, 4 JT1,2 Unit64-Lead LFCSP9 mm 9 mm(CP-64-4)

0 22.3 1.4 N/A 0.1 C/W

1.0 19.5 N/A 11.8 0.2 C/W

2.5 17.5 N/A N/A 0.2 C/W

1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).3 Per MIL-Std 883, Method 1012.1.4 Per JEDEC JESD51-8 (still air).

Typical JA is specified for a 4-layer PCB with a solid ground

plane. As shown Table 7, airflow improves heat dissipation,

which reduces JA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes reduces JA.

ESD CAUTION

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PIN 1

INDICATOR

17181920212223242526272829303132

D4

D4+

DRVDD

D5

D5+

D6

D6+

DCO

DCO+

D7

D7+

DRVDD

D8

D8+

D9

D9+

64636261605958575655545352515049

AVDD

AVDD

VIN+B

VINB

AVDD

AVDD

RBIAS

VCM

SENSE

VREF

AVDD

AVDD

VINA

VIN+A

AVDD

AVDD

1

234

567

89

1011

121314

1516

CLK+

CLKSYNC

NC

NCNCNC

D0 (LSB)D0+ (LSB)

DRVDDD1

D1+D2D2+

D3D3+

PDWN

OEBCSBSCLK/DFS

SDIO/DCSOR+OR

D13+ (MSB)D13 (MSB)D12+D12

DRVDDD11+D11

D10+D10

48

474645

444342

41403938

373635

3433

AD9648INTERLEAVED PARALLEL LVDS

TOP VIEW(Not to Scale)

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDESTHE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BECONNECTED TO GROUND FOR PROPER OPERATION.

09975-007

Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View)

Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies

10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).

49, 50, 53, 54,59, 60, 63, 64

AVDD Supply Analog Power Supply (1.8 V Nominal).

4, 5, 6, 7 NC No Connect. Do not connect to these pins.

0 AGND,Exposed Pad

Ground The exposed thermal pad on the bottom of the package provides the analog ground forthe part. This exposed pad must be connected to ground for proper operation.

ADC Analog

51 VIN+A Input Differential Analog Input Pin (+) for Channel A.

52 VINA Input Differential Analog Input Pin () for Channel A.

62 VIN+B Input Differential Analog Input Pin (+) for Channel B.

61 VINB Input Differential Analog Input Pin () for Channel B.

55 VREF Input/Output Voltage Reference Input/Output.

56 SENSE Input Reference Mode Selection.

58 RBIAS Input/Output External Reference Bias Resistor.

57 VCM Output Common-Mode Level Bias Output for Analog Inputs.

1 CLK+ Input ADC Clock InputTrue.

2 CLK Input ADC Clock InputComplement.

Digital Input

3 SYNC Input Digital Synchronization Pin. Slave mode only.

Digital Outputs

9 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0True.

8 D0 (LSB) Output Channel A/Channel B LVDS Output Data 0Complement.

12 D1+ Output Channel A/Channel B LVDS Output Data 1True.

11 D1 Output Channel A/Channel B LVDS Output Data 1Complement.

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PIN 1

INDICATOR

17181920212223242526272829303132

BD9/D8

BD9+/D8+

DRVDD

BD11/D10

BD11+/D10+

BD13/D12(MSB)

BD13+/D12+(MSB)

DCO

DCO+

AD1/D0(LSB)

AD1+/D0+(LSB)

DRVDD

AD3/D2

AD3+/D2+

AD5/D4

AD5+/D4+

64636261605958575655545352515049

AVDD

AVDD

VIN+B

VINB

AVDD

AVDD

RBIAS

VCM

SENSE

VREF

AVDD

AVDD

VINA

VIN+A

AVDD

AVDD

1

23

4567

89

10

11121314

1516

CLK+

CLKSYNC

NCNCNCNC

B D1/D0 (LSB)B D1+/D0+ (LSB)

DRVDD

B D3/D2B D3+/D2+B D5/D4B D5+/D4+

B D7/D6B D7+/D6+

PDWN

OEBCSB

SCLK/DFSSDIO/DCSOR+OR

A D13+/D12+ (MSB)A D13/D12 (MSB)A D11+/D10+

A D11/D10DRVDDA D9+/D8+A D9/D8

A D7+/D6+A D7/D6

48

4746

45444342

414039

38373635

3433

AD9648CHANNEL MULTIPLEXED LVDS

TOP VIEW(Not to Scale)

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDESTHE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BECONNECTED TO GROUND FOR PROPER OPERATION. 0

9975-008

Figure 8. Channel Multiplexed LVDS Pin Configuration (Top View)

Table 10 Pin Function Descriptions (Channel Multiplexed Parallel LVDS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies

10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).

49, 50, 53, 54,59, 60, 63, 64

AVDD Supply Analog Power Supply (1.8 V Nominal).

4, 5, 6, 7 NC Do Not Connect.

0 AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the analogground for the part. This exposed pad must be connected to ground forproper operation.

ADC Analog

51 VIN+A Input Differential Analog Input Pin (+) for Channel A.

52 VINA Input Differential Analog Input Pin () for Channel A.

62 VIN+B Input Differential Analog Input Pin (+) for Channel B.

61 VINB Input Differential Analog Input Pin () for Channel B.55 VREF Input/Output Voltage Reference Input/Output.

56 SENSE Input Reference Mode Selection.

58 RBIAS Input/Output External Reference Bias Resistor.

57 VCM Output Common-Mode Level Bias Output for Analog Inputs.

1 CLK+ Input ADC Clock InputTrue.

2 CLK Input ADC Clock InputComplement.

Digital Input

3 SYNC Input Digital Synchronization Pin. Slave mode only.

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TYPICAL PERFORMANCE CHARACTERISTICSAD9648-125


otherwise noted.

120

100

80

60

40

20

0

0 10 20 30 40 6050

AMPLITUDE(dBFS)

FREQUENCY (MHz)

125MSPS9.7MHz AT 1dBFSSNR = 74.4dB (75.4dBFS)SFDR = 95.4dBc

09975-014

Figure 9. Single-Tone FFT with fIN= 9.7 MHz

120

100

80

60

40

20

0

0 10 20 30 40 50 60

AMPLITUDE(dBFS)

FREQUENCY (MHz)


09975-022


120

100

80

60

40

20

0

0 10 20 30 40 50 60

AMPLITUDE(d

BFS)

FREQUENCY (MHz)


09975-023


120

100

80

60

40

20

0

0 10 20 30 40 50 60

AMPLITUDE(dBFS)

FREQUENCY (MHz)


09975-02

4


120

100

80

60

40

20

0

0 10 20 30 40 50 60

AMPLITUDE(dBFS)

FREQUENCY (MHz)


09975-025


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AD9648-125


otherwise noted.

6M

0

15

30

45

60

75

90

105

120

135

12M 18M 24M 30M 36M 42M 48M 54M 60M6M

0

15

30

45

60

75

90

105

120

135

12M 18M 24M 30M 36M 42M 48M 54M 60M

2F1 F2 2F2 F1

2F1+ F2

FREQUENCY (MHz)

AMPLITUDE(Hz)

09975-067

Figure 14. Two-Tone FFT with fIN1 = 29 MHz and fIN2 = 32 MHz

50

55

60

65

70

75

80

85

90

95

100

0 50 100 150 200 250

ANALOG INPUT FREQUENCY (MHz)

SNR/SFDR(dBFS/dBc)

SFDR (dBc)

SNR (dBFS)

09975-069

Figure 15. SNR/SFDR vs. Input Frequency (AIN) with 2 V p- p Full Scale

0

20

40

60

80

100

120

90 80 70 60 50 40 30 20 10 0

SNR/SFDR

(dBFS)

INPUT AMPLITUDE (dBFS)0

9975-068

SFDRFS

SNR

SFDR

SNRFS

Figure 16. SNR/SFDR vs. Input Amplitude (AIN) with fIN= 9.7 MHz

110

90

70

50

30

10

90 80 70 60 50 40 30 20 10

SFDR/IMD3(dBc/dBFS)

INPUT AMPLITUDE (dBFS)

SFDR (dBc)

IMD3(dBc)

SFDR(dB FS)

IMD3 (dBFS)

09975-065

Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29 MHzand fIN2 = 32 MHz

0

20

40

60

80

100

120

5 15 25 35 45 55 65 75 85 95 105 115 125

SNR/SFDR(dBFS/dBc)

SAMPLE RATE (MSPS)

SNR (dBFS)

SFDR (dBc)

09975-020

Figure 18. SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz

0

20

40

60

80

100

120

SNR/SFDR(dBFS/dBc)

5 15 25 35 45 55 65 75 85 95 105 115 125

SAMPLE RATE (MSPS)

SNR (dBFS)

SFDR (dBc)

09975-021


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0 2000 4000 6000 8000 10000 12000 14000 16000

OUTPUT CODE

2.0

1.5

1.0

0.5

0

0.5

1

1.5

2

DNLERROR(LSB)

09975-019

Figure 20. DNL Error with fIN= 9.7 MHz

0

50,000

100,000

150,000

200,000

250,000

300,000

350,000

400,000

450,000

N6

N5

N4

N3

N2

N1 N

N+1

N+2

N+3

N+4

N+5

N+6

NUMBEROFHITS

OUTPUT CODE0

997

5-074

Figure 21. Shorted Input Histogram

2.0

1.5

1.0

-0.5

0

0.5

1.0

1.5

2.0

0 2000 4000 6000 8000 10000 12000 14000 16000

INLERROR(LSB)

OUTPUT CODE0

9975 -018

Figure 22. INL Error with fIN= 9.7 MHz

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AD9648


50

55

60

65

70

75

80

85

90

95

100

0 50 100 150 200 250

SNR/SFDR(dBF

S/dBc)

ANALOG INPUT FREQUENCY (MHz)

SFDR (dBc)

SNR (dBFS)

09975-075

Figure 28. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale

0

20

40

60

80

100

120

5 15 25 35 45 55 65 75 85 95 105

SNR/SFDR(dBFS/dBc)

SAMPLE RATE (MSPS)

SFDR (dBc)

SNR (dBFS)

09975-012


2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

0 2000 4000 6000 8000 10000 12000 14000 16000

DNL

ERROR(LSB)

OUTPUT CODE0

9975-010

Figure 30. DNL Error with fIN= 9.7 MHz

0

20

40

60

80

100

120

90 80 70 60 50 40 30 20 10 0

SNR/SFDR(dBF

S/dBc)

INPUT AMPLITUDE (dBFS)

SFDRFS

SNRFS

SFDR

SNR

09975 -077

Figure 31. SNR/SFDR vs. Input Amplitude (AIN) with fIN= 9.7 MHz

0

20

40

60

80

100

120

5 15 25 35 45 55 65 75 85 95 105

SNR/SFDR(dBFS/dBc)

SAMPLE RATE (MSPS)

SFDR (dBc)

SNR (dBFS)

0 9 9 7 5 - 0 1 1

Figure 32. SNR/SFDR vs. Sample Rate with AIN = 70.1 MH z

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

0 2000 4000 6000 8000 10000 12000 14000 16000

INL

ERROR(LSB)

OUTPUT CODE0

9975 -009

Figure 33. INL Error with fIN= 9.7 MHz

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THEORY OF OPERATIONTheAD9648dual ADC design can be used for diversity

reception of signals, where the ADCs are operating identically

on the same carrier but from two separate antennae. The ADCs

can also be operated with independent analog inputs. The user

can sample any fS/2 frequency segment from dc to 200 MHz,

using appropriate low-pass or band-pass filtering at the ADC

inputs with little loss in ADC performance. Operation to

300 MHz analog input is permitted but occurs at the expense

of increased ADC noise and distortion.

In nondiversity applications, theAD9648can be used as a base-

band or direct downconversion receiver, where one ADC is

used for I input data and the other is used for Q input data.

Synchronization capability is provided to allow synchronized

timing between multiple channels or multiple devices.

Programming and control of theAD9648is accomplished using

a 3-bit SPI-compatible serial interface.ADC ARCHITECTURE

TheAD9648architecture consists of a multistage, pipelined ADC.

Each stage provides sufficient overlap to correct for flash errors in

the preceding stage. The quantized outputs from each stage are

combined into a final 14-bit result in the digital correction logic.

The pipelined architecture permits the first stage to operate with a

new input sample while the remaining stages operate with

preceding samples. Sampling occurs on the rising edge of

the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and an interstage residue amplifier (for example, a multiplyingdigital-to-analog converter (MDAC)). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, corrects errors, and

passes the data to the CMOS/LVDS output buffers. The output

buffers are powered from a separate (DRVDD) supply, allowing

digital output noise to be separated from the analog core. During

power-down, the output buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to theAD9648is a differential switched-

capacitor circuit designed for processing differential input

signals. This circuit can support a wide common-mode range

while maintaining excellent performance. By using an input

common-mode voltage of midsupply, users can minimize

signal-dependent errors and achieve optimum performance.

S S

CPAR

CSAMPLE

CSAMPLE

CPAR

VINx

H

S S

H

H

VIN+x

H

09975-049

Figure 42. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample-and-hold mode (see Figure 42). When the input circuit

is switched to sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current injected from the output

stage of the driving source. In addition, low Q inductors or ferrite

beads can be placed on each leg of the input to reduce highdifferential capacitance at the analog inputs and, therefore,

achieve the maximum bandwidth of the ADC. Such use of low

Q inductors or ferrite beads is required when driving the converter

front end at high IF frequencies. Either a shunt capacitor or two

single-ended capacitors can be placed on the inputs to provide a

matching passive network. This ultimately creates a low-pass

filter at the input to limit unwanted broadband noise. See the

AN-742Application Note, theAN-827Application Note, and the

Analog Dialogue article Transformer-Coupled Front-End for

Wideband A/D Converters (Volume 39, April 2005) for more

information. In general, the precise values depend on the

application.
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Input Common Mode

The analog inputs of theAD9648are not internally dc-biased.

Therefore, in ac-coupled applications, the user must provide a

dc bias externally. Setting the device so that VCM = AVDD/2 is

recommended for optimum performance, but the device can

function over a wider range with reasonable performance, asshown in Figure 43.

An on-board, common-mode voltage reference is included in

the design and is available from the VCM pin. The VCM pin

must be decoupled to ground by a 0.1 F capacitor, as described

in the Applications Information section.

0

10

20

30

40

50

60

70

80

90

100

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

SNR/SFDR(d

BFS/dBc)

INPUT COMMON-MODE VOLTAGE (V)

SFDR (dBc)

SNR (dBFS)

09975-072

Figure 43. SNR/SFDR vs. Input Common-Mode Voltage,fIN= 70 MHz, fS = 125 MSPS

Differential Input Configurations

Optimum performance is achieved while driving the AD9648 in adifferential input configuration. For baseband applications, the

AD8138,ADA4937-2, andADA4938-2differential drivers provide

excellent performance and a flexible interface to the ADC.

The output common-mode voltage of the ADA4938-2 is easily

set with the VCM pin of theAD9648(see Figure 44), and the

driver can be configured in a Sallen-Key filter topology to

provide band limiting of the input signal.

AVDDVIN 76.8

1200.1F

33

33

10pF

200

200

90

ADA4938 ADC

VINx

VIN+x VCM

09975-050

Figure 44. Differential Input Configuration Using the ADA4938-2

For baseband applications below ~10 MHz where SNR is a key

parameter, differential transformer-coupling is the recommended

input configuration. An example is shown in Figure 45. To bias

the analog input, the VCM voltage can be connected to the

center tap of the secondary winding of the transformer.

2Vp-p 49.9

0.1F

R

R

C ADC

VCM

VIN+x

VINx

09975-051

Figure 45. Differential Transformer-Coupled Configuration

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few megahertz (MHz). Excessive signal power can also

cause core saturation, which leads to distortion.

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of theAD9648. For applications above

~10 MHz where SNR is a key parameter, differential double balun

coupling is the recommended input configuration (see Figure 46).

An alternative to using a transformer-coupled input at frequencies

in the second Nyquist zone is to use theAD8352differential driver.

An example is shown in Figure 47. See the AD8352 data sheet

for more information.

ADC

R0.1F0.1F

2Vp-p

VCM

C

R0.1F

S0.1F25

25

SPA P

VIN+x

VINx

09975-053

Figure 46. Differential Double Balun Input Configuration

AD8352

0

0

CD RD RG

0.1F

0.1F

0.1F

0.1F

16

1

2

3

4

5

11

0.1F

0.1F

10

14

0.1F8,13

VCC

200

200

ANALOG INPUT

ANALOG INPUT

R

R

C ADC

VCM

VIN+x

VINx

09975-054

Figure 47. Differential Input Configuration Using the AD8352
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In any configuration, the value of Shunt Capacitor C is dependent

on the input frequency and source impedance and may need to

be reduced or removed. Table 11 displays the suggested values to

set the RC network. However, these values are dependent on the

input signal and should be used only as a starting guide.

Table 11. Example RC Network

Frequency Range (MHz)R Series( Each) C Differential (pF)

0 to 70 33 22

70 to 200 125 Open

Single-Ended Input Configuration

A single-ended input can provide adequate performance in

cost-sensitive applications. In this configuration, SFDR and

distortion performance degrade due to the large input common-

mode swing. If the source impedances on each input are matched,

there should be little effect on SNR performance. Figure 48

shows a typical single-ended input configuration.

1Vp-p

R

R

C

49.9 0.1F

10F

10F 0.1F

AVDD

1k

1k

1k

1k

ADC

AVDD

VIN+x

VINx

09975-052

Figure 48. Single-Ended Input Configuration

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the

AD9648. The VREF can be configured using either the internal

1.0 V reference or an externally applied 1.0 V reference voltage.

The various reference modes are summarized in the sections that

follow. The Reference Decoupling section describes the best

practices PCB layout of the reference.

Internal Reference Connection

A comparator within theAD9648detects the potential at the

SENSE pin and configures the reference into two possible

modes, which are summarized in Table 12. If SENSE is grounded,

the reference amplifier switch is connected to the internal resistor

divider (see Figure 49), setting VREF to 1.0 V.

VREF

SENSE

0.5V

ADC

SELECTLOGIC

0.1F1.0F

VINA/VINB

VIN+A/VIN+B

ADCCORE

09975-055

Figure 49. Internal Reference Configuration

If the internal reference of theAD9648is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 50 shows

how the internal reference voltage is affected by loading.

0

3.00 2.0

LOAD CURRENT (mA)

REFERENCEVOLT

AGEERROR(%)

0.5

1.0

1.5

2.0

2.5

0.2 0.4 0.6 0.8 1.0 1.4 1.6 1.81.2

INTERNAL VREF = 1.00V

0 9 9 7 5 - 0 7 8

Figure 50. VREFAccuracy vs. Load Current

Table 12. Reference Configuration Summary

Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p)

Fixed Internal Reference AGND to 0.2 1.0 internal 2.0

Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0
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External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 51 shows the typical drift characteristics of the

internal reference in 1.0 V mode.

4

3

2

1

0

1

2

3

4

5

640 20 0 20 40 60 80

TEMPERATURE (C)

VREFERROR(mV)

VREF ERROR (mV)

09975-079

Figure 51. Typical VREFDrift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7.5 k load (see Figure 41). The internal buffer generates the

positive and negative full-scale references for the ADC core.

Therefore, the external reference must be limited to a maximum

of 1.0 V.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock theAD9648sample clock

inputs, CLK+ and CLK, with a differential signal. The signal

is typically ac-coupled into the CLK+ and CLK pins via a

transformer or capacitors. These pins are biased internally

(see Figure 52) and require no external bias.

0.9V

AVDD

2pF 2pF

CLKCLK+

09975-058

Figure 52. Equivalent Clock Input Circuit

Clock Input Options

TheAD9648has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter is

of the most concern, as described in the Jitter Considerations

section.Figure 53 and Figure 54 show two preferred methods for clock-

ing theAD9648(at clock rates up to 1 GHz prior to internal CLK

divider). A low jitter clock source is converted from a single-

ended signal to a differential signal using either an RF

transformer or an RF balun.

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 1 GHz, and the RF transformer is recom-

mended for clock frequencies from 10 MHz to 200 MHz. The

back-to-back Schottky diodes across the transformer/balun

secondary limit clock excursions into theAD9648to

approximately 0.8 V p-p differential.

This limit helps prevent the large voltage swings of the clockfrom feeding through to other portions of theAD9648while

preserving the fast rise and fall times of the signal that are critical

to a low jitter performance.

0.1F

0.1F

0.1F0.1F

SCHOTTKYDIODES:

HSMS2822

CLOCKINPUT

50 100

CLK

CLK+

ADC

Mini-Circuits

ADT1-1WT, 1:1 Z

XFMR

09975-059

Figure 53. Transformer-Coupled Differential Clock (Up to 200 MHz)

0.1F

0.1F1nFCLOCK

INPUT

1nF

50

CLK

CLK+

SCHOTTKYDIODES:

HSMS2822

ADC

09975-060

Figure 54. Balun-Coupled Differential Clock (Up to 1 GHz)
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Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR from the low fre-

quency SNR (SNRLF) at a given input frequency (fINPUT) due to

jitter (tJRMS) can be calculated by

SNRHF= 10 log[(2 fINPUT tJRMS)2 + 10 )10/( LFSNR ]

In the previous equation, the rms aperture jitter represents the

clock input jitter specification. IF undersampling applications

are particularly sensitive to jitter, as illustrated in Figure 59.

80

75

70

65

60

55

50

451 10 100 1k

FREQUENCY (MHz)

SN

R(dBFS)

0.5ps

0.2ps

0.05ps

1.0ps

1.5ps

2.0ps

2.5ps3.0ps

09975-080

Figure 59. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of theAD9648.

To avoid modulating the clock signal with digital noise, keep

power supplies for clock drivers separate from the ADC outputdriver supplies. Low jitter, crystal-controlled oscillators make the

best clock sources. If the clock is generated from another type of

source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

See theAN-501Application Note and theAN-756Application

Note, available on www.analog.comfor more information.

CHANNEL/CHIP SYNCHRONIZATION

TheAD9648has a SYNC input that offers the user flexible

synchronization options for synchronizing sample clocks

across multiple ADCs. The input clock divider can be enabled

to synchronize on a single occurrence of the SYNC signal or on

every occurrence. The SYNC input is internally synchronized

to the sample clock; however, to ensure there is no timing

uncertainty between multiple parts, the SYNC input signal should

be externally synchronized to the input clock signal, meeting the

setup and hold times shown in Table 5. Drive the SYNC input

using a single-ended CMOS-type signal.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 60, the analog core power dissipated by

theAD9648is proportional to its sample rate. The digital

power dissipation of the CMOS outputs are determined

primarily by the strength of the digital drivers and the load

on each output bit.

The maximum DRVDD current (IDRVDD) can be calculated as

IDRVDD = VDRVDD CLOAD fCLK N

where Nis the number of output bits (30, in the case of the

AD9648).

This maximum current occurs when every output bit switches

on every clock cycle, that is, a full-scale square wave at the Nyquist

frequency of fCLK/2. In practice, the DRVDD current is estab-

lished by the average number of output bits switching, which

is determined by the sample rate and the characteristics of the

analog input signal.

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data in Figure 60 was

taken in CMOS mode using the same operating conditions as those

used for the Power Supplies and Power Consumption specifications

in Table 1, with a 5 pF load on each output driver.

40

60

80

100

120

140

160

180

200

220

0

10

20

30

40

50

60

70

80

90

100

5 25 45 65 85 105 125

POWER(mW)

SUPPLYCURRENT(A)

ENCODE RATE (MSPS)

IAVDD

TOTAL POWER

IDRVDD

09975-070

Figure 60. AD9648-125 Power and Current vs. Clock Rate (1.8 V CMOSOutput Mode)

40

60

80

100

120

140

160

180

200

0

10

20

30

40

50

60

70

80

90

5 25 45 65 85 105

POWER(mW)

SUPP

LYCURRENT(A)

ENCODE RATE (Msps)

IAVDD

IDRVDD

TOTAL POWER

09975-066

Figure 61. AD9648-105 Power and Current vs. Clock Rate (1.8 V CMOSOutput Mode)
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BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

TheAD9648includes a built-in test feature designed to enable

verification of the integrity of each channel, as well as to

facilitate board level debugging. A built-in self-test (BIST) feature

that verifies the integrity of the digital datapath of theAD9648is included. Various output test options are also provided to place

predictable values on the outputs of theAD9648.

BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected

AD9648signal path. Perform the BIST test after a reset to ensure

the part is in a known state. During BIST, data from an internal

pseudorandom noise (PN) source is driven through the digital

datapath of both channels, starting at the ADC block output. At

the datapath output, CRC logic calculates a signature from the

data. The BIST sequence runs for 512 cycles and then stops.

Once completed, the BIST compares the signature results with a

predetermined value. If the signatures match, the BIST sets Bit 0of Register 0x24, signifying the test passed. If the BIST test fails,

Bit 0 of Register 0x24 is cleared. The outputs are connected

during this test, so the PN sequence can be observed as it runs.

Writing the value 0x05 to Register 0x0E runs the BIST. This enables

Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence

generator, Bit 2 (initialize BIST sequence) of Register 0x0E. At the

completion of the BIST, Bit 0 of Register 0x24 is automatically

cleared. The PN sequence can be continued from its last value

by writing a 0 in Bit 2 of Register 0x0E. However, if the PN

sequence is not reset, the signature calculation does not equal

the predetermined value at the end of the test. At that point, the

user needs to rely on verifying the output data.

OUTPUT TEST MODES

The output test options are described in Table 18 at Address 0x0D.

When an output test mode is enabled, the analog section of the

ADC is disconnected from the digital back-end blocks and the

test pattern is run through the output formatting block. Some of

the test patterns are subject to output formatting, and some are

not. The PN generators from the PN sequence tests can be reset

by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be

performed with or without an analog signal (if present, the

analog signal is ignored), but they do require an encode clock.

For more information, see theAN-877Application Note,

Interfacing to High Speed ADCs via SPI.
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SERIAL PORT INTERFACE (SPI)TheAD9648serial port interface (SPI) allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. The SPI

gives the user added flexibility and customization, depending on

the application. Addresses are accessed via the serial port andcan be written to or read from via the port. Memory is organized

into bytes that can be further divided into fields, which are docu-

mented in the Memory Map section. For detailed operational

information, see theAN-877Application Note, Interfacing to

High Speed ADCs via SPI.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK/DFS pin, the

SDIO/DCS pin, and the CSB pin (see Table 15). The SCLK/DFS

(a serial clock) is used to synchronize the read and write data

presented from and to the ADC. The SDIO/DCS (serial data

input/output) is a dual-purpose pin that allows data to be sent

to and read from the internal ADC memory map registers. TheCSB (chip select bar) is an active low control that enables or

disables the read and write cycles.

Table 15. Serial Port Interface Pins

Pin Function

SCLK Serial clock. The serial shift clock input, which is used tosynchronize serial interface reads and writes.

SDIO Serial data input/output. A dual-purpose pin thattypically serves as an input or an output, depending onthe instruction being sent and the relative position in thetiming frame.

CSB Chip select bar. An active low control that gates the readand write cycles.

The falling edge of the CSB, in conjunction with the rising edge

of the SCLK, determines the start of the framing. An example of

the serial timing and its definitions can be found in Figure 62

and Table 5.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high, SPI

functions are placed in high impedance mode. This mode turns

on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and W1 bits.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to readthe contents of the on-chip memory. The first bit of the first byte in

a multibyte serial data transfer frame indicates whether a read

command or a write command is issued. If the instruction is a

readback operation, performing a readback causes the serial

data input/output (SDIO) pin to change direction from an input to

an output at the appropriate point in the serial frame.

All data is composed of 8-bit words. Data can be sent in MSB-

first mode or in LSB-first mode. MSB first is the default on

power-up and can be changed via the SPI port configuration

register. For more information about this and other features,

see the AN-877 Application Note, Interfacing to High Speed

ADCs via SPI.

DONT CARE

DONT CAREDONT CARE

DONT CARE

SDIO

SCLK

CSB

tS tDH

tCLKtDS tH

R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0

tLOW

tHIGH

0 9 9 7 5 - 0 4 6

Figure 62. Serial Port Interface Timing Diagram
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MEMORY MAPREADING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the chip

configuration registers (Address 0x00 to Address 0x02); thechannel index and transfer registers (Address 0x05 and

Address 0xFF) and the ADC functions registers, including setup,

control, and test (Address 0x08 to Address 0x102).

The memory map register table (see Table 18) lists the default

hexadecimal value for each hexadecimal address shown. The

column with the heading Bit 7 (MSB) is the start of the default

hexadecimal value given. For example, Address 0x05, the device

index register, has a hexadecimal default value of 0x03. This

means that in Address 0x05 Bits[7:2] = 0, and Bits[1:0] = 1. This

setting is a default channel index setting. The default value

results in both ADC channels receiving the next write

command. For more information on this function and others, see

theAN-877Application Note, Interfacing to High Speed ADCs via

SPI. This application note details the functions controlled by

Register 0x00 to Register 0xFF. The remaining registers, are

documented in the Memory Map Register Description section.

Open Locations

All address and bit locations that are not included in Table 18

are not currently supported for this device. Unused bits of a

valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x05). If the entire address location

is open (for example, Address 0x13), this address location should

not be written to.

Default Values

After theAD9648is reset, critical registers are loaded withdefault values. The default values for the registers are given in

the memory map register table, Table 18.

Logic Levels

An explanation of logic level terminology follows:

Bit is set is synonymous with bit is set to Logic 1 orwriting Logic 1 for the bit.

Clear a bit is synonymous with bit is set to Logic 0 orwriting Logic 0 for the bit.

Channel-Specific Registers

Some channel setup functions, such as the signal monitor

thresholds, can be programmed differently for each channel. Inthese cases, channel address locations are internally duplicated for

each channel. These registers and bits are designated in Table 18

as local. These local registers and bits can be accessed by setting

the appropriate Channel A or Channel B bits in Register 0x05.

If both bits are set, the subsequent write affects the registers of

both channels. In a read cycle, only Channel A or Channel B

should be set to read one of the two registers. If both bits are set

during an SPI read cycle, the part returns the value for Channel A.

Registers and bits designated as global in Table 18 affect the entire

part or the channel features for which independent settings are not

allowed between channels.
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MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 18 are not currently supported for this device.

Table 18. Memory Map Registers

Addr

(Hex)

Register

Name

Bit 7

(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

(LSB)

DefaultValue

(Hex) CommentsChip Configuration Registers

0x00 SPI portconfig(global)

Open LSB first Soft reset 1 1 Soft reset LSB first Open 0x18 The nibblesaremirrored soLSB-firstmode orMSB-firstmoderegisterscorrectly,regardlessof shiftmode

0x01 Chip ID(global)

8-bit chip ID[7:0]AD9648 = 0x88

Readonly

Unique chipID used todifferentiate

devices;read only

0x02 Chipgrade(global)

Open Speed grade ID

100 = 105 MSPS101 = 125 MSPS

Open Readonly

Uniquespeedgrade IDused todifferentiatedevices;read only

Channel Index and Transfer Registers

0x05 Deviceindex(global)

Open Open Open Open Open Open DataChannel B

DataChannel A

0x03 Bits are settodeterminewhichdevice onthe chipreceives the

next writecommand;applies tolocalregistersonly

0xFF Transfer(global)

Open Open Open Open Open Open Open Transfer 0x00 Synchron-ouslytransfersdata fromthe mastershiftregister tothe slave

ADC Functions

0x08 Powermodes

(local)

Open Open Externalpower-

down pinfunction0 = PDWN1 = standby

Open Open Open Internal power-downmode

00 = normal operation01 = full power-down10 = standby11 = digital reset

0x00 Determinesvarious

genericmodes ofchipoperation

0x09 Globalclock(global)

Open Open Open Open Open Open Open Duty cyclestabilizer0 =Disabled1 =enabled

0x01

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Addr(Hex)

RegisterName

Bit 7(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0(LSB)

DefaultValue(Hex) Commen

0x0B Clockdivide(global)

Open Open Open Open Open Clock divide ratio000 = divide by 1001 = divide by 2010 = divide by 3

011 = divide by 4100 = divide by 5101 = divide by 6110 = divide by 7111 = divide by 8

0x00 The dividratio isvalue plu

0x0C Enhance-mentcontrol(global)

Open Open Open Open Open Chop0 =disabled1 =enabled

Open Open 0x00 Chop moenabled iBit 2 isenabled

0x0D Test mode(local)

User test mode control00 = single pattern mode01 = alternatecontinuous/repeatpattern mode

10 = single once patternmode11 = alternate oncepattern mode

Reset PNlong gen

Reset PNshort gen

Output test mode0000 = off (default)0001 = midscale short0010 = positive FS0011 = negative FS

0100 = alternating checkerboard0101 = PN long sequence0110 = PN short sequence0111 = one/zero word toggle1000 = user test mode1111 = ramp output

0x00 When thisregister isset, the tedata isplaced onthe outpu

pins inplace ofnormal da

0x0E BISTenable(global)

Open Open Open Open Open InitializeBISTsequence

Open BIST enable 0x00

0x10 Customeroffsetadjust(local)

Offset adjust in LSBs from +127 to 128(twos complement format)

0x00

0x14 Outputmode

Output port logic type(global)

00 = CMOS, 1.8 V

10 = LVDS, ANSI11 = LVDS, reducedrange

OutputInterleaveenable

(global)

Output portdisable (local)

Open(global)

Outputinvert(local)

Output format00 = offset binary01 = twos complement

10 = Gray code

0x00 Configuretheoutputsand theformat ofthe data

0x15 Outputadjust

Open Open CMOS 1.8 V DCO drivestrength00 = 101 = 210 = 311 = 4

Open Open CMOS 1.8 V datadrive strength

00 = 101 = 210 = 311 = 4

0x00 DeterminCMOSoutputdrivestrengthpropertie

0x16 Clockphasecontrol(global)

InvertDCOclock0 = notinverted1 =inverted

Open Open Open Open Input clock divider phase adjustrelative to the encode clock000 = no delay001 = one input clock cycle010 = two input clock cycles011 = three input clock cycles100 = four input clock cycles

101 = five input clock cycles

110 = six input clock cycles111 = seven input clock cycles

0x00 Allowsselection clockdelays intthe inputclockdivider

0x17 Outputdelay(global)

DCOclockdelay0 =disabled1 =enabled

Open Data delay0 =disabled1 =enabled

Open Open Delay selection000 = 0.56 ns001 = 1.12 ns010 = 1.68 ns011 = 2.24 ns100 = 2.80 ns101 = 3.36 ns110 = 3.92 ns111 = 4.48 ns

0x00 This setsthe fineoutputdelay ofthe outpuclock butdoes notchangeinternaltiming

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Addr(Hex)

RegisterName

Bit 7(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0(LSB)

DefaultValue(Hex) Comments

0x18 VREFselect(global)

Open Open Open Open Open Internal VREF digital adjustment000 = 1.0 V p-p

001 = 1.14 V p-p010 = 1.33 V p-p

011 = 1.6 V p-p100 = 2.0 V p-p

0x04 Select and/or adjustVREF

0x19 UserPattern 1LSB(global)

B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-definedPattern 1LSB

0x1A UserPattern 1MSB(global)

B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-definedPattern, 1MSB

0x1B UserPattern 2LSB(global)

B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-definedPattern 2LSB

0x1C UserPattern 2MSB

B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-definedPattern, 2

MSB0x24 MISR LSB MISR LSB[7:0] 0xFF Read only

0x25 MISR MSB MISR MSB[15:8] 0xFF Read only

0x2A Overrangecontrol(global)

Open Open Open Open Open Open Open Overrangeoutput0 =disabled1 =enabled

0x01 Overrangecontrolsettings

0x2E Outputassign(local)

Open Open Open Open Open Open Open 0 = ADC A1 = ADC B(local)

ADC A =0x00ADC B =0x01

Assign anADC to anoutputchannel

0x3A Synccontrol(global)

Open Open Open Open Open Syncnext only

Syncenable

Open 0x00 Sets theglobal syncoptions

0x100 Samplerateoverride

Open Sample rateoverrideenable

Resolution010 = 14 bits100 = 12 bits110 = 10 bits

Sample rate011 = 80 MSPS

100 = 105 MSPS101 = 125 MSPS

0x00

0x101 User I/OControlRegister 2

Outputenablebar (OEB)pinenable

Open Open Open Open Open Open DisableSDIO pull-down

0x00 OEB andSDIO pincontrols

0x102 User I/OControlRegister 3

Open Open Open Open VCM power-down

Open 0x00
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MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Register 0x00 to Register 0xFF, see theAN-877Application Note,

Interfacing to High Speed ADCs via SPI.

Power Modes (Register 0x08)

Bits[7:6]Open

Bit 5External Power-Down Pin Function

If set, the external PDWN pin initiates power-down mode.

If clear, the external PDWN pin initiates standby mode.

Bits[4:2]Open

Bits[1:0]Internal Power-Down Mode

In normal operation (Bits[1:0] = 00), both ADC channels are

active.

In power-down mode (Bits[1:0] = 01), the digital data path clocks

are disabled while the digital data path is reset. Outputs are

disabled.In standby mode (Bits[1:0] = 10), the digital data path clocks

and the outputs are disabled.

During a digital reset (Bits[1:0] = 11), the digital data path clocks

are disabled while the digital data path is held in reset. The outputs

are enabled in this state. For optimum performance, it is recom-

mended that both ADC channels be reset simultaneously. This

is accomplished by ensuring that both channels are selected via

Register 0x05 prior to issuing the digital reset instruction.

Enhancement Control (Register 0x0C)

Bits[7:3]Open

Bit 2Chop ModeFor applications that are sensitive to offset voltages and other

low frequency noise, such as homodyne or direct-conversion

receivers, chopping in the first stage of the AD9628 is a feature

that can be enabled by setting Bit 2. In the frequency domain,

chopping translates offsets and other low frequency noise to

fCLK/2 where it can be filtered.

Bits[1:0]Open

Output Mode (Register 0x14)

Bits[7:6]Output Port Logic Type

00 = CMOS, 1.8 V

10 = LVDS, ANSI11 = LVDS, reduced range

Bit 5Output Interleave Enable

For LVDS outputs, setting Bit 5 enables interleaving. Channel A

is sent coincident with a high DCO clock, and Channel B is

coincident with a low DCO clock. Clearing Bit 5 disables the

interleaving feature. Channel A is sent on least significant bits

(LSBs), and Channel B is sent on most significant bits (MSBs).

The even bits are sent coincident with a high DCO clock, and

the odd bits are sent coincident with a low DCO clock.

For CMOS outputs, setting Bit 5 enables interleaving in CMOS

DDR mode. On ADC Output Port A, Channel A is sent coincidentwith a low DCO clock, and Channel B is coincident with a high

DCO clock. On ADC Output Port B, Channel B is sent coincident

with a low DCO clock, and Channel A is coincident with a high

DCO clock. Clearing Bit 5 disables the interleaving feature, and

data is output in CMOS SDR mode. Channel A is sent to Port A,

and Channel B is sent to Port B.

Bit 4Output Port Disable

Setting Bit 4 high disables the output port for the channels

selected in Bits[1:0] of the device index register (Register 0x05).

Bit 3Open

Bit 2Output Invert

Setting Bit 2 high inverts the output port data for the channels

selected in Bits[1:0] of the device index register (Register 0x05).

Bits[1:0]Output Format

00 = offset binary

01 = twos complement

10 = Gray code

Sync Control (Register 0x3A)

Bits[7:3]Open

Bit 2Clock Divider Next Sync Only

If the clock divider sync enable bit (Address 0x3A, Bit 1) is high,

Bit 2 allows the clock divider to sync to the first sync pulse itreceives and to ignore the rest. The clock divider sync enable bit

resets after it syncs.

Bit 1Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 is high. This is continuous sync mode.

Bit 0Open

Transfer (Register 0xFF)

All registers except Register 0x100 are updated the moment they

are written. Setting Bit 0 of this transfer register high initializes

the settings in the ADC sample rate override register (Address

0x100).

Sample Rate Override (Register 0x100)

This register is designed to allow the user to downgrade the device.

Any attempt to upgrade the default speed grade results in a chip

power-down. Settings in this register are not initialized until Bit 0

of the transfer register (Register 0xFF) is written high.
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User I/O Control 2 (Register 0x101)

Bit 7OEB Pin Enable

If the OEB pin enable bit (Bit 7) is set, the OEB pin is enabled.

If Bit 7 is clear, the OEB pin is disabled (default).

Bits[6:1]Open

Bit 0SDIO Pull-Down

Bit 0 can be set to disable the internal 30 k pull-down on the

SDIO pin, which can be used to limit the loading when many

devices are connected to the SPI bus.

User I/O Control 3 (Register 0x102)

Bits[7:4]Open

Bit 3VCM Power-Down

Bit 3 can be set high to power down the internal VCM

generator. This feature is used when applying an external

reference.

Bits[2:0]Open

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APPLICATIONS INFORMATIONDESIGN GUIDELINES

Before starting design and layout of theAD9648as a system,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections andlayout requirements that are needed for certain pins.

Power and Ground Recommendations

When connecting power to theAD9648, it is recommended that

two separate 1.8 V supplies be used. Use one supply for analog

(AVDD); use a separate supply for the digital outputs (DRVDD).

For both AVDD and DRVDD several different decoupling capa-

citors should be used to cover both high and low frequencies.

Place these capacitors close to the point of entry at the PCB level

and close to the pins of the part, with minimal trace length.

A single PCB ground plane should be sufficient when using the

AD9648. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performanceis easily achieved.

LVDS Operation

TheAD9648defaults to CMOS output mode on power-up.

If LVDS operation is desired, this mode must be programmed,

using the SPI configuration registers after power-up. When the

AD9648 powers up in CMOS mode with LVDS termination

resistors (100 ) on the outputs, the DRVDD current can be

higher than the typical value until the part is placed in LVDS

mode. This additional DRVDD current does not cause damage

to the AD9648, but it should be taken into account when consid-

ering the maximum DRVDD current for the part.

To avoid this additional DRVDD current, theAD9648outputs

can be disabled at power-up by taking the PDWN pin high.

After the part is placed into LVDS mode via the SPI port, the

PDWN pin can be taken low to enable the outputs.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. A continuous, exposed

(no solder mask) copper plane on the PCB should mate to the

AD9648exposed paddle, Pin 0.

The copper plane should have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow through

the bottom of the PCB. These vias should be filled or plugged to

prevent solder wicking through the vias, which can compromise

the connection.

To maximize the coverage and adhesion between the ADC and

the PCB, a silkscreen should be overlaid to partition the continuous

plane on the PCB into several uniform sections. This provides

several tie points between the ADC and the PCB during the reflow

process. Using one continuous plane with no partitions guarantees

only one tie point between the ADC and the PCB. For detailed

information about packaging and PCB layout of chip scale

packages, see theAN-772Application Note,A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP), atwww.analog.com.

VCM

The VCM pin should be decoupled to ground with a 0.1 F

capacitor.

Reference Decoupling

The VREF pin should be externally decoupled to ground with

a low ESR, 1.0 F capacitor in parallel with a low ESR, 0.1 F

ceramic capacitor.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,it may be necessary to provide buffers between this bus and the

AD9648to keep these signals from transitioning at the converter

inputs during critical sampling periods.
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OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 091707-C

6.35

6.20 SQ

6.05

0.25 MIN

TOP VIEW 8.75BSC SQ

9.00BSC SQ

164

1617

4948

3233

0.50