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LOYOLAICAM COLLEGE OF ENGINEERING AND TECHNOLOGY

(LICET)

DEPARTMENT OF ECE

LAB MANUAL

FOR

EC6311ANALOG AND DIGITAL CIRCUITS LABORATORY

CYCLE II

List of experiments:

Design and implementation of code converters using logic gates

(i) BCD to excess-3 code and vice versa

(ii) Binary to gray and vice-versa

Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC

7483

Design and implementation of Multiplexer and De-multiplexer using logic gates

Design and implementation of encoder and decoder using logic gates

Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters

Design and implementation of 3-bit synchronous up/down counter

Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops

Add-on content:

System design using above experiments

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CODE CONVERTERS

BINARY CODE TO GRAY CODE

AIM:

To Design and Implement BINARY TO GRAY & GRAY TO BINARY using logic

gates.

APPARATUS REQUIRED:

PROCEDURE:

1. The connections are made as per the circuit diagram.

2. Give the logical inputs as per the truth table.3. The corresponding output is verified with their truth table.

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BINARY TO GRAY TRUTH TABLE

INPUT OUTPUT

A B C D W X Y Z

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

1 1 0 1 1 0 1 1

1

2

3

4

5

6

9

10

8

B2 B1 B0

G3

G2

G1

G0

B3

IC7486

IC7486

BINARY TO GRAY CODE

CODE CONVERTER

IC7486

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GRAY TO BINARY TRUTH TABLE

INPUT OUTPUT

W X Y Z A B C D

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

RESULT:

Thus the Code Converters were designed and implemented.

1

2 3

4

5 6

9

10 8

12

13 11

1

2 3

4

5 6

GRAY TO BINARY CODE

B2

B1

B0

G0G1G2G3

B3

IC7486

IC7486IC7486

IC7486

IC7486

IC7486

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BCD TO EXCESS 3 CODE AND VICE VERSA

AIM:

To Design and Implement BCD TO EXCESS 3 & EXCESS TO BCD converter using

logic gates.

APPARATUS REQUIRED:

1. IC trainer kit.

2. IC 7486

3. Connecting wires

PROCEDURE:

1. The connections are made as per the circuit diagram.

2. Give the logical inputs as per the truth table.

3. The corresponding output is verified with their truth table.

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TRUTH TABLE:

BCD TO EXCESS 3 CODES:

INPUT OUTPUT

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 00 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

3

4

5

6

9

8

1

2 3 1 2

1

122

13

1

2 3

4

5 6 1

2

3

4

5

6 1

2 3

IC7411IC7432

IC7404

IC7404

IC7404

IC7404

IC7432IC7408

IC7432IC7408

IC7486

B1B2B3

B0

BCD TO EXCESS-3 CODE

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EXCESS 3 TO BCD CODE:

INPUT OUTPUT

E3 E2 E1 E0 B3 B2 B1 B00 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

RESULT:

Thus the Code Converters were designed and implemented.

3

4

5

6

9

8

1

2

3

1

2

3

1

122

13

3

64

5

1

2

3

4

5

6

1

2

3

1

122

13

1

2

3

B0

E0E1E2E3

EXCESS-3 TO BCD CODE

B3

B2

B1

IC7404

IC7404

IC7404

IC7408

IC7486

IC7432

IC7432

IC7432

IC7411

IC7411

IC7411

IC7408

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4 BIT BINARY ADDER / SUBTRACTOR

AIM:

To design and implement 4 bit parallel binary adder and Subtractor.

APPARATUS REQUIRED:

PROCEDURE:

1. The connections are made as per the circuit diagram.2. Apply the binary inputs for A and B.

3. Observe the output for the corresponding input .

PIN Diagram

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RESULT:

Thus the 4 bit binary adder and Subtractor circuit was designed and implemented.

A4

1

A3

3

A2

8

A1

10

B4

16

B3

4

B2

7

B1

11

C0

13

C4

14

SUM4

15

SUM3

2

SUM2

6

SUM1

9

1

2

3

4

5

6

9

10

8

12

13

11

A3

GND/VCC

B2

B1

B0

A0A3

A1

A2

B3

S0 CoutS3S2S1

Cin

IC7486

IC7486

IC7486

IC7486

4 BIT BINARY ADDER/SUBTRACTOR

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BCD ADDER

AIM:

To design and implement BCD adder.

APPARATUS REQUIRED:

PROCEDURE:

1. The connections are made as per the circuit diagram.

2. Apply the binary inputs for X and Y.

3. Observe the output for the corresponding input .

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RESULT:Thus the BCD adder circuit was designed and implemented

A4

1

A3

3

A2

8

A1

10

B4

16

B3

4

B2

7

B1

11

C0

13

C4

14

SUM4

15

SUM3

2

SUM2

6

SUM1

9

A4

1

A3

3

A2

8

A1

10

B4

16

B3

4

B2

7

B1

11

C0

13

C4

14

SUM4

15

SUM3

2

SUM2

6

SUM1

9

0

00

1

23

1

2 3

45

6

Y1

Y0

X0

X1

X2

X3

Y3

Y2

Cout

S2S1S0 S3

IC 7432

IC 7432

IC 7408

BCD ADDER

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MULTIPLEXER AND DEMULTIPLEXER

AIM:

To Design and Implement Multiplexer, DeMultiplexer using logic gates and MSI devices.

APPARATUS REQUIRED:

PROCEDURE:

1. The connections are made as per the circuit diagram.

2. Give the logical inputs as per the truth table.3. The corresponding output is verified with their truth table.

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TRUTH TABLE:

MULTIPLEXER

INPUT OUTPUTS0 S1 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

1

2

3

4

1

122

13

3

64

5

9

810

11

1

122

13

1

2

3

4

5

6

9

10

8

S0S1

IC7411

IC7404

IC7404

Y

D3

D2

D1

D0

IC7432

IC7432

IC7432

IC7411

IC7411

IC7411

MULTIPLEXER

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TRUTH TABLE:

DEMULTIPLEXER

INPUT OUTPUT

D A B D0 D1 D2 D3

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

RESULT:

Thus the Multiplexer circuit is designed and implemented.

1

2

3

4

9

810

11

3

64

5

9

810

11

1

122

13

IC7411

S1 S0

IC7404

IC7404

D2

D3

D0

D1

IC7411

IC7411

IC7411

DEMULTIPLEXER

Y3

Y2

Y1

Y0

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ENCODER AND DECODER

AIM:

To Design and Implement encoder and decoder using logic gates .

APPARATUS REQUIRED:

S.No Components Specification Quantity

IC trainer kit. 1OR Gate IC 7432 2

3 Input AND IC 7411 2

Not Gate IC 7404 1

Patch chords 35

PROCEDURE:

1. The connections are made as per the circuit diagram.

2. Give the logical inputs as per the truth table.3. The corresponding output is verified with their truth table.

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TRUTH TABLE:

ENCODER

INPUT OUTPUT

A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D

1 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 1

0 0 0 1 0 0 0 0 0 1

0 0 0 0 1 0 0 0 1 0

0 0 0 0 0 1 0 0 1 0

0 0 0 0 0 0 1 0 1 1

0 0 0 0 0 0 0 1 1 1

1

2 3

4

5 6

9

10 8

12

13 11

1

2 3

4

5 6

9

10 8

12

13 11

1

2 3

A3A2A1A0 A7A6A5A4

IC7432

IC7432

IC7432

IC7432

D2

D1

D0

ENCODER (OCTAL TO BINARY)

IC7432

IC7432

IC7432

IC7432

IC7432

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TRUTH TABLE:

DECODER

INPUT OUTPUT

I0 I1 I2 A0 A1 A2 A3 A4 A5 A6 A7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

RESULT:

Thus the encoder and decoder circuit is designed and implemented.

1

2

3

4

5

6

I2I1I0

1

122

13

3

64

5

9810

11

1

122

13

3

64

5

9

810

11

1

122

13

3

64

5

A6

A5

A4

A3

A2

A1

A0

IC7404

IC7404

IC7404

A7

IC7411

IC7411

IC7411

IC7411

DECODER (BINARY TO OCTAL)

IC7411

IC7411

IC7411

IC7411

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ASYNCHRONOUS COUNTER

AIM:

To Design and Implement 4-bit ripple counter.

APPARATUS REQUIRED:

PROCEDURE:

1. The connections are made as per the circuit diagram.2. Give the logical inputs as per the truth table.3. The corresponding output is verified with their truth table.

PIN DIAGRAM FOR IC 7476

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LOGIC DIAGRAM:

TRUTH TABLE:

CLK QA QB QC QD

0 0 0 0 01 1 1 1 1

2 1 1 1 0

3 1 1 0 1

4 1 1 0 0

5 1 0 1 1

6 1 0 1 0

7 1 0 0 1

8 1 0 0 0

9 0 1 1 1

10 0 1 1 0

11 0 1 0 1

12 0 1 0 0

13 0 0 1 1

14 0 0 1 0

15 0 0 0 1

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RESULT:

Thus the Asynchronous Counter circuits are designed and verified with their truth table.

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SYNCHRONOUS COUNTER

AIM:

To Design and Implement 3-bit Synchronous counter.

APPARATUS REQUIRED:

PROCEDURE:

1. The connections are made as per the circuit diagram.

2. Give the logical inputs as per the truth table.3. The corresponding output is verified with their truth table.

STATE DIAGRAM:

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STATE TABLE:

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K-MAP:

LOGIC DIAGRAM:

RESULT:

Thus the Synchronous Counter circuits are designed and verified with their truth table.

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SHIFT REGISTERS

AIM:

To Design a 4bit Shift Register using flip-flops.

(1). Serial In Serial Out(2). Serial In Parallel Out

(3). Parallel In Parallel Out.

APPARATUS REQUIRED:

PROCEDURE:

1. The connections are made as per the circuit diagram.

2. Give the logical inputs as per the truth table.3. The corresponding output is verified with their truth table.

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SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK DATA QD

0 1 0

1 1 0

2 0 0

3 0 0

4 0 1

SERIAL IN PARALLEL OUT:

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TRUTH TABLE:

CLK DATA QA QB QC QD

0 1 0 0 0 0

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 0

4 0 0 0 0 1

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

CLOCK D1 D2 D3 D4 QA QB QC QD

0 1 1 0 0 0 0 0 0

1 1 1 0 0 1 1 0 0

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PARALLEL IN SERIAL OUT:

RESULT:

Thus the Shift Registers circuits are designed and verified with their truth table.