adder tree to adder chain - fhi · adder tree to adder chain l bringing you the next level in...

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BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _

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out

in

out

in

in

out

0

in

out

Adder Tree to Adder Chain Adder Tree to Adder Chain l


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Filter Specification: Sampling Frequency = 600 Mhz, Coefficients = 92

Input time delay series is created inside the DSP Slice for maximum performance irrespective of the number of coefficients

Max Sample Rate = Clock RateDedicated cascade connections (PCOUT and PCIN)

are exploited to achieve maximum performance

Systolic FIR Filter Systolic FIR Filter

K0 K1 K90 K91

0

DSP48 SliceDSP48 Slice

x(n)

y(n)48

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DSP48 Slice DSP48 Slice

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When the coefficients are symmetrical,Ø pre-adders either reduce the number of multiplications by 50% Ø or double the sample rateFactorizing the taps replaces one multiplication by a pre-addition/-subtraction

k13 k17

Non symmetrical filter (k13?k17) :(tap13×k13) + (tap17×k17)

Symmetrical filter (k13=k17) :(tap13+tap17) × k13

2 mults and one post-add

1 pre-add

Symmetrical Filter Example

1 multDirect benefit : saves 50% of the DSP slices

PrePre--adder Benefits with adder Benefits with Symmetrical FiltersSymmetrical Filters

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Symmetric Systolic Symmetric Systolic BandpassBandpass FIR FilterFIR Filter

8Samplein

Max Sample Rate = Clock Rate

K1 K44 K45K0

0

DSP48A Slice 2DSP48A Slice 1

27Sampleout

DSP48A Slice 45 DSP48A Slice 46

Z -92srl32

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SpartanSpartan--3A DSP48A Slice3A DSP48A Slice

OpMode[3:2]

0 X

0

PCIN

PCOUT

CE

M REG

D QCE

P REG

D Q

A

BCIN

01

C

Z

CE

C REG

D Q

BCOUT

01

CE

A1 REG

D Q

CE

B1 REG

D Q

CARRYOUT

Opmode[5]

CARRYIN

OpMode[1:0]

Opmode[7]

+/-

CE

B0 REG

D Q

CE

D REG

D Q

CE

A0 REG

D Q

D

B

C

Opmode[4]

Opmode[6]

+/-


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BandpassBandpass FIR Filter using System GeneratorFIR Filter using System Generator

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BandpassBandpass FIR Filter using System GeneratorFIR Filter using System Generatorl


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BandpassBandpass FIR Filter using System GeneratorFIR Filter using System GeneratorHardware Resources Hardware Resources BandpassBandpass FIR FilterFIR Filterl


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BandpassBandpass FIR Filter using System GeneratorFIR Filter using System GeneratorHardware Resources Hardware Resources BandpassBandpass FIR FilterFIR Filterl

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Hardware CoHardware Co--SimSim Simulation FIR FilterSimulation FIR Filterl


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Hardware CoHardware Co--SimSim Simulation FIR FilterSimulation FIR Filterl

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Compare Hardware CoCompare Hardware Co--SimSim SimulationSimulationl


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Easily integrate purchased or custom RTL for any block in a design

RTL IntegrationRTL Integrationl

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WrapWrap--UpUp

Ø Any low cost FPGA Development board can be used for Hardware Verification and Co-Simulation

Ø Use appropriate tooling and use it with careØ Try different implementationsØ Knowledge is powerØ Use common sence


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Core|Core|VisionVision

Our competences

Core|Vision has more than 75 man years of design experience in hard- and software development. Our competence areas are:

Ø System DesignØ FPGA DesignØ ConsultancyØ Digital Signal ProcessingØ Embedded Real-time SoftwareØ Data Acquisition, digital and analogØ Modeling & SimulationØ ASIC Conversion & PrototypingØ PCB design & Layout

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?Cereslaan 10b

5384 VT Heesch) +31 (0)412 660088

www.www.corecore--visionvision..nlnl

Email : Email : info@[email protected]

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Training ProgramTraining ProgramØ Introduction to VHDL 3 daysØ Advanced VHDL 2 daysØ Essentials of FPGA Design 1 dayØ Designing for Performance 2 daysØ Advanced FPGA Implementation 2 daysØ Design Techniques for Lower Cost 1 dayØ Designing with Virtex 4 Family 2 daysØ Designing with Virtex 5 Family 1 dayØ Designing with Spartan 6 and Virtex 6 Family 3 days

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Training ProgramTraining ProgramØ Embedded Systems Development 2 daysØ Embedded Systems Software Development 2 daysØ Open-Source Linux Development 2 daysØ Advanced Features and Techniques of EDK 2 daysØ Designing with PlanAhead 2 daysØ Designing with Multi Gigabit Serial IO 3 daysØ AccelDSP Synthesis Tool Training 2 daysØ DSP Design Using System Generator 2 daysØ DSP Implementation Techniques for Xilinx FPGAs 3 days


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Training ProgramTraining ProgramØ Designing a LogiCORE PCI System 2 daysØ Designing a LogiCORE PCI-X System 2 daysØ Designing a LogiCORE PCI-e System 2 daysØ Designing with EMAC Controllers 2 daysØ Fundamentals of CPLD Design 1 dayØ Designing for Performance for CPLD 2 daysØ Introduction to Verilog 3 daysØ Minimizing Your Design Time with ChipScope Pro 1 day

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Training ProgramTraining Program

Ø VHDL Design for FPGA 3 daysØ Advanced VDHL 2 daysØ Comprehensive VHDL 5 days

adder tree to adder chain - fhi · adder tree to adder chain l bringing you the next level in...

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