What are a Half Adder and a Full Adder

Written byHarpreet

HomeTechnology and GadgetsHalf Adder is a digital combinational circuit that is used for the addition of two bits and provides an output in the form of a sum bit and a carry bit. The logical functional equations that relate the outputs S and C of a half adder circuit to the input bits are given below:-Sum(S) = A ex-OR B

Carry(C) = A.B Thus a half adder circuit can easily be synthesized by using 1 ex-OR gate and 1 AND gate. Since a half adder circuit can only be used to add two bits, it becomes obsolete in case of multi-bit addition in practical applications.

A full adder circuit is the one that is used for addition of three bits. It is more complex than a half adder circuit. Let A,B and C be the input bits of a full adder and S and C be the output bits, then the logical equations that relates the outputs to the inputs are:-S= A (ex-OR) B (ex-OR) CC= AB + C (A+B)

Thus two ex-OR gates, two AND gates and two OR gates can be used for the hardware synthesis of the circuit. These full adder circuits are the ones that can be used for multi bit addition of numbers.

In addition of multiple bits, the carry output from a full adder being used for the addition of bits at ones place isfedas an input bit to the full adder being used for the addition of the bits at the next significant place and so on. The sum bits from all the full adders along with the carry bit from the full adder dealing with the most significant bits is available to the user as an output. The carry input to the full adder dealing with the least significant place should be made 0 by the user.

In market, only 4 bit full adders and 8 bit full adders are available in IC form and they need to be combined for addition of higher number of bits such as 16 and 32. The biggest disadvantage of a multi-bit full adder is the large propagation delay that is encountered in the transmission of carry bits from one adder block to the other. That is the reason why these have been replaced by more sophisticated designs such a look ahead carry adder in practical computational systems.

Half Adder and Full Adder

Half Adder and Full Adder Circuit

Half Adder and Full Adder circuits is explained with their truth tables in this article. Design of Full Adder using Half Adder circuit is also shown.Single-bit Full Adder circuit and Multi-bit addition using Full Adder is also shown.Before going into this subject, it is very important to know about Boolean Logic and Logic Gates.

Half AdderWith the help of half adder, we can design circuits that are capable of performing simple addition with the help of logic gates.

Let us first take a look at the addition of single bits.

0+0 = 0

0+1 = 1

1+0 = 1

1+1 = 10

These are the least possible single-bit combinations. But the result for 1+1 is 10. Though this problem can be solved with the help of an EXOR Gate, if you do care about the output, the sum result must be re-written as a 2-bit output.

Thus the above equations can be written as

0+0 = 00

0+1 = 01

1+0 = 01

1+1 = 10

Here the output 1of 10 becomes the carry-out. The result is shown in a truth-table below. SUM is the normal output and CARRY is the carry-out.

INPUTS OUTPUTSA B SUM CARRY0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

From the equation it is clear that this 1-bit adder can be easily implemented with the help of EXOR Gate for the output SUM and an AND Gate for the carry. Take a look at the implementation below.

Half Adder Circuit

For complex addition, there may be cases when you have to add two 8-bit bytes together. This can be done only with the help of full-adder logic.

Full AdderThis type of adder is a little more difficult to implement than a half-adder. The main difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs. The first two inputs are A and B and the third input is an input carry designated as CIN. When a full adder logic is designed we will be able to string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.

The output carry is designated as COUT and the normal output is designated as S. Take a look at the truth-table.

INPUTS OUTPUTSA B CIN COUT S0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

From the above truth-table, the full adder logic can be implemented. We can see that the output S is an EXOR between the input A and the half-adder SUM output with B and CIN inputs. We must also note that the COUT will only be true if any of the two inputs out of the three are HIGH.

Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will half adder will be used to add A and B to produce a partial Sum. The second half adder logic can be used to add CIN to the Sum produced by the first half adder to get the final S output. If any of the half adder logic produces a carry, there will be an output carry. Thus, COUT will be an OR function of the half-adder Carry outputs. Take a look at the implementation of the full adder circuit shown below.

Full Adder Circuit

Though the implementation of larger logic diagrams is possible with the above full adder logic a simpler symbol is mostly used to represent the operation. Given below is a simpler schematic representation of a one-bit full adder.

Single-bit Full Adder

With this type of symbol, we can add two bits together taking a carry from the next lower order of magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a multi-bit operation, each bit must be represented by a full adder and must be added simultaneously. Thus, to add two 8-bit numbers, you will need 8 full adders which can be formed by cascading two of the 4-bit blocks. The addition of two 4-bit numbers is shown below.

Multi-Bit Addition using Full Adder

Flip Flops

JOHNAPRIL - 19 - 2010

6 COMMENTS23ShareBasic Flip Flops

This article deals with the basic flip flop circuits like S-R Flip Flop, J-K Flip Flop, D Flip Flop, and T Flip Flop along with truth tables and their corresponding circuit symbols.Before going to the topic it is important that you get knowledge of its basics. Click on the links below for more information.

TAKE A LOOK :BOOLEAN LOGICTAKE A LOOK :LOGIC GATESTAKE A LOOK :HALF ADDER AND FULL ADDERFlip flops are actually an application of logic gates. With the help of Boolean logic you can create memory with them. Flip flops can also be considered as the most basic idea of a Random Access Memory [RAM]. When a certain input value is given to them, they will be remembered and executed, if the logic gates are designed correctly. A higher application of flip flops is helpful in designing better electronic circuits.

The most commonly used application of flip flops is in the implementation of a feedback circuit. As a memory relies on the feedback concept, flip flops can be used to design it.

There are mainly four types of flip flops that are used in electronic circuits. They are

1. The basic Flip Flop or S-R Flip Flop2. Delay Flip Flop [D Flip Flop]3. J-K Flip Flop4. T Flip Flop1. S-R Flip FlopThe SET-RESET flip flop is designed with the help of two NOR gates and also two NAND gates. These flip flops are also called S-R Latch.

S-R Flip Flop using NOR GateThe design of such a flip flop includes two inputs, called the SET [S] and RESET [R]. There are also two outputs, Q and Q. The diagram and truth table is shown below.

S-R Flip Flop using NOR Gate

From the diagram it is evident that the flip flop has mainly four states. They are

S=1, R=0Q=1, Q=0This state is also called the SET state.

S=0, R=1Q=0, Q=1This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the value of Q follows the value of S.

S=0, R=0Q & Q = RememberIf both the values of S and R are switched to 0, then the circuit remembers the value of S and R in their previous state.

S=1, R=1Q=0, Q=0 [Invalid]This is an invalid state because the values of both Q and Q are 0. They are supposed to be compliments of each other. Normally, this state must be avoided.

S-R Flip Flop using NAND GateThe circuit of the S-R flip flop using NAND Gate and its truth table is shown below.

S-R Flip Flop using NAND Gate

Like the NOR Gate S-R flip flop, this one also has four states. They are

S=1, R=0Q=0, Q=1This state is also called the SET state.

S=0, R=1Q=1, Q=0This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the value of Q follows the compliment value of S.

S=0, R=0Q=1, & Q =1 [Invalid]If both the values of S and R are switched to 0 it is an invalid state because the values of both Q and Q are 1. They are supposed to be compliments of each other. Normally, this state must be avoided.

S=1, R=1Q & Q= RememberIf both the values of S and R are switched to 1, then the circuit remembers the value of S and R in their previous state.

Clocked S-R Flip FlopIt is also called a Gated S-R flip flop.

The problems with S-R flip flops using NOR and NAND gate is the invalid state. This problem can be overcome by using a bistable SR flip-flop that can change outputs when certain invalid states are met, regardless of the condition of either the Set or the Reset inputs. For this, a clocked S-R flip flop is designed by adding two AND gates to a basic NOR Gate flip flop. The circuit diagram and truth table is shown below.

Clocked S-R Flip Flop

A clock pulse [CP] is given to the inputs of the AND Gate. When the value of the clock pulse is 0, the outputs of both the AND Gates remain 0. As soon as a pulse is given the value of CP turns 1. This makes the values at S and R to pass through the NOR Gate flip flop. But when the values of both S and R values turn 1, the HIGH value of CP causes both of them to turn to 0 for a short moment. As soon as the pulse is removed, the flip flop state becomes intermediate. Thus either of the two states may be caused, and it depends on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse. Thus the invalid states can be eliminated.

2. D Flip FlopThe circuit diagram and truth table is given below.

D Flip Flop

D flip flop is actually a slight modification of the above explained clocked SR flip-flop. From the figure you can see that the D input is connected to the S input and the complement of the D input is connected to the R input. The D input is passed on to the flip flop when the value of CP is 1. When CP is HIGH, the flip flop moves to the SET state. If it is 0, the flip flop switches to the CLEAR state.

To know more about the triggering of flip flop click on the link below.

TAKE A LOOK :TRIGGERING OF FLIP FLOPSTAKE A LOOK :MASTER-SLAVE FLIP FLOP CIRCUIT3. J-K Flip FlopThe circuit diagram and truth-table of a J-K flip flop is shown below.

J-K Flip Flop

A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is that the intermediate state is more refined and precise than that of a S-R flip flop.

The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J stands for SET and the letter K stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.

The circuit includes two 3-input AND gates. The output Q of the flip flop is returned back as a feedback to the input of the AND along with other inputs like K and clock pulse [CP]. So, if the value of CP is 1, the flip flop gets a CLEAR signal and with the condition that the value of Q was earlier 1. Similarly output Q of the flip flop is given as a feedback to the input of the AND along with other inputs like J and clock pulse [CP]. So the output becomes SET when the value of CP is 1 only if the value of Q was earlier 1.

The output may be repeated in transitions once they have been complimented for J=K=1 because of the feedback connection in the JK flip-flop. This can be avoided by setting a time duration lesser than the propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction.

4. T Flip FlopThis is a much simpler version of the J-K flip flop. Both the J and K inputs are connected together and thus are also called a single input J-K flip flop. When clock pulse is given to the flip flop, the output begins to toggle. Here also the restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction. Take a look at the circuit and truth table below.

T Flip Flop

Logic Gates

JOHNAPRIL - 16 - 2010

2 COMMENTS4ShareDigital Logic Gates

This article explains the basic logic gates like NOT Gate, AND Gate, OR Gate, NAND Gate, NOR Gate, EXOR Gate and EXNOR gate with their corresponding truth tables and circuit symbols.Logic Gates are considered to be the basics of Boolean Logic. To know more about Boolean Logic click on the link below.

TAKE A LOOK :BOOLEAN LOGICTo know about the application of logic gates, click on the links below

TAKE A LOOK :HALF ADDER AND FULL ADDERTAKE A LOOK :FLIP FLOPSThere are mainly 7 types of logic gates that are used in expressions. By combining them in different ways, you will be able to implement all types of digital components. Take a look at each basic logic gate and their operation.

A Logic Gate is assigned as an elementary building block of digital circuits. Logic gate is considered as a device which has the ability to produce one output level with the combinations of input levels. There are seven basic types of logic gates:

AND GATE OR GATE NOT GATE NAND GATE NOR GATE EXCLUSIVE-OR GATE (X-OR) GATE EXCLUSIVE-NOR (X-NOR) GATEThe reason for which the computers are capable of performing complex operation is due to the interconnection of these logic gates. Logic gates are implemented by using transistors, diodes,relays, optics and molecules or even by several mechanical elements. Due to this reason logic gates can also be considered as electronic circuits. The logic gates can be build up in a wide variety forms such as large-scale integrated circuits (LSI), very large-scale integrated circuits (VLSI) and also in small-scale integrated circuits (SSI). Here the inputs and output of all the gates of integrated devices can be accessible and also the external connections are made available to them just like discrete logic gates.

Inputs and outputs of logic gates are in two levels termed as HIGH and LOW, or TRUE and FALSE, or ON and OFF, or simply 1 and 0. A table which list out the combination of input variables and the corresponding output variables is termed as TRUTH TABLE. It explains how the logic circuit output responds to various combinations of logic levels at the inputs. Here we are following level logic, in which the voltage levels are represented as logic 1 and logic 0. Level logic is of two types such as positive logic or negative logic. In the positive logic system, higher of the two voltage levels are represented as 1 and lower of the two voltage levels are represented as 0. But in the negative logic system, higher of the two voltage levels are represented as 0 and lower of the two voltage levels are represented as 1. While considering the transistor-transistor logic (TTL), the lower state is assumed to be zero volts (0V) and the higher state is considered as five volts positive (+5V).

AND GATEAn AND gate requires two or more inputs and produce only one output. The AND gate produces an output of logic 1 state when each of the inputs are at logic 1 state and also produces an output of logic 0 state even if any of its inputs are at logic 0 state. The symbol for AND operation is ., or we use no symbol for representing. If the inputs are of X and Y, then the output can be expressed as Z=XY. TheAND gate is so named because, if 0 is called false and 1 is called true, the gate performs in the same way as the logical and operator. The AND gate is also named as all or nothing gate. The logic symbols and truth tables of two-input and three-input AND gates are given below.

2 Input AND Gate Truth Table

3 Input AND Gate Truth Table

Discrete AND gates may be realized by using diodes or transistors. The inputs represented as X and Y may be either 0V or +5V correspondingly. The output is represented by Z . In the diode of AND gate, when both the inputs are of same value, X=+5V and Y= +5V, then the diodes are in OFF condition. As a result, no current flows through the resistor and there will not be any voltage drop across the resistor. Here the output will be Z=+5V. Similarly, when both the inputs such as X and Y are equal to 0V, then the corresponding diodes such as either D1 or D2 or both the diodes are at ON state and act as short circuits. Here the output will be Z corresponds to 0V. In practical cases the output z corresponds to 0.6V or 0.7V, which is treated as logic 0 state.

2 Input Diode AND Gate

2 Input Transistor AND Gate

In the case of transistor AND gate, When the inputs X, Y = 0V or when X=0V and Y= +5V or when X=+5V and Y=0V, both the transistors Q1 and Q2 are at OFF state. At the same time, Transistor Q3 gets enough base drive from the supply through Resistor R3 and so transistor Q3 will be ON. Thereby the output voltage Z= Vce(sat)corresponds to 0V. When both the inputs are equal to +5V, the transistors Q1 and Q2 will be ON and therefore the voltage at the collector of transistor Q1 will drop. Due to this the transistor Q3 doesnt get enough base drive and turns OFF. As a result no current flows through the collector resistor of Q3 and , thereby no voltage drop across it. So the final output voltage corresponds to +5V. The truth table for this gate circuit is shown below:

Discrete AND Gate Truth Table

OR GATESimilar to AND gate, an OR gate may also have two or more inputs but produce only one output. The OR gate produces an output of logic 1 state even if any of its inputs is in logic 1 state and also produces an output of logic 0 state if any of its inputs is in logic 0 state. The symbol for OR operation is +. If the inputs are of X and Y, then the output can be represented as Z=X+Y. An OR gate may also be defined as a device whose output is 1, even if one of its input is 1. OR gate is also called as any or all gate. It is also called as an inclusive OR gate because it consists of the condition of both the inputs can be present. The logic symbols and truth table for two-input and three-input OR gates are given below.

2 Input OR Gate Truth Table

3 Input OR Gate Truth Table

Discrete OR gates may be realized by using diodes or transistors. The inputs represented as X and Y may be either 0V or +5V correspondingly. The output is represented by Z . In the diode of OR gate, when both the inputs are of same value, X=0V and Y= 0V, then both the diodes are in OFF condition. As a result, no current flows through the resistor and there will not be any voltage drop across the resistor. Here the output will be Z=0V. Similarly, when both the inputs or either the inputs such as X and Y are equal to +5V, then the corresponding diodes either D1 or D2 or both the diodes are at ON state and act as short circuits. Here the output will be Z corresponds to +5V. In practical cases the output Z corresponds to +5V-diode drop = +5V 0.7V = +4.3V, which is regarded as Logic 1 state.

2 Input Diode OR Gate

In the case of transistor OR gate, when the inputs X=0V and Y = 0V both the transistors Q1 and Q2 are at OFF state. At the same time, Transistor Q3 gets enough base drive from the supply +5V through Resistor R3 and so transistor Q3 will be ON. Thereby the output voltage Z= Vce(sat)corresponds to 0V. When either the inputs X and Y or both the inputs are equal to +5V, then the corresponding transistors either Q1 or Q2 will be ON or both the transistors Q1 and Q2 will be ON and therefore the voltage at the collector of transistor Q1 is VCE(sat)corresponds to 0V. Due to this reason the transistor Q3 doesnt forward bias the base-emitter junction and turns OFF. So the final output voltage corresponds to +5V (logic 1 state). The truth table for this gate circuit is shown below:

Discrete OR Gate Truth Table

NOT GATEThe NOT gate is also called as an inverter, simply because it changes the input to its opposite. The NOT gate is having only one input and one corresponding output. It is a device whose output is always the compliment of the given input. That means, the NOT gate produces an output of logic 1 state when the input is of logic 0 state and also produce the output of logic 0 state when the input is of logic 1 state. The NOT operation is denoted by -(bar). When the input variable to the NOT gate is represented by X and the output is represented by Z. In the NOT operation it can be read as Z is equal to X bar. The logic symbol and truth table are given below:

NOT Gate Truth Table

Discrete NOT gate may be realized by using transistors. The inputs represented as X may be either 0V or +5V correspondingly. The output is represented by Z. When the input X = 0V, then the transistor Q1 will be reverse biased and therefore it remains OFF. As a result no current flows through the resistor and thereby there will not be any voltage drop across the resistor. As a result, the output voltage Z corresponds to +5V. When the input X= +5V, transistor Q1 is ON and the output voltage Z=Vce(sat)corresponds to 0V. The truth table for the NOT gate is given below:

Transistor Inverter NOT Gate

Transistor Inverter NOT Gate Truth Table

NAND GATEThe NAND and NOR gates are the universal gates. Each of this gates can realize the logic circuits single handedly. The NAND and NOR are also called as universal building blocks. Both NAND and NOR has the ability to perform three basic logic functions such as AND,OR and NOT. NAND gate is a combination of an AND gate and a NOT gate. The expression for the NAND gate is whole bar. The output of the NAND gate is at logic 0 level only when each of the inputs assumes a logic 1 level. The truth table of two-input NAND gate is given below:

2 Input NAND Gate -Truth Table

A Discrete two-input NAND gate is as shown in the figure. The two inputs are represented by X and Y. The output is represented by Z . When the input X and Y= +5V, then both the diodes D1 and D2 are OFF. The transistor Q1 gets enough base drive from the supply through resistor and therefore transistor Q1 is ON and the output Z=Vce(sat)corresponds to 0V. Similarly when inputs either x=0V or Y=0V or when both inputs are equal to 0V, at that time the transistor Q1 is OFF and therefore, output voltage Z= +5V. The truth table is given below:

Discrete NAND Gate

Discrete NAND Gate -Truth Table

NOR GATENOR means NOT OR. That means, NOR gate is a combination of an OR gate and a NOT gate. The output is logic 1 level, only when each of its inputs assumes a logic 0 level. For any other combination of inputs, the output is a logic 0 level. The truth table of two-input NOR gate is given below:

2 Input NOR Gate Truth Table

3 Input NOR Gate -Truth Table

Discrete two-input NOR gate is as shown in the figure. The inputs represented as X and Y may be 0V correspondingly. As a result the transistors Q1 and Q2 are OFF, as a result no current flows through the resistor and thereby there will not be any voltage drop across the resistor. Here, the output voltage Z corresponds to +5V. When either of the input X= +5V or Y=+5V or both the inputs corresponds to +5V, the corresponding transistor Q1or Q2 or both Q1 and Q2 are ON . Therefore the output voltage Z=Vce(sat)corresponds to ground and equal to 0V. The truth table for the NOR gate is given below:

Discrete NOR Gate

Discrete NOR Gate Truth Table

EXCLUSIVE-OR GATE (X-OR) GATEAn X-OR gate is a two input, one output logic circuit. X-OR gate assumes logic 1 state when any of its two inputs assumes a logic 1 state. When both the inputs assume the logic 0 state or when both the inputs assume the logic 1 state, the output assumes a logic 0 state. The output of the X-OR gate will be the sum of the modulo sum of its inputs. X-OR gate is also termed as anti-coincidence gate or inequality detector. An X-OR gate can also be used as inverter by connecting one of the two input terminals to logic1 and also by inputting the sequence to be inverted to the other terminal.

X-OR Gate Truth Table

EXCLUSIVE-NOR (X-NOR) GATEAn X-NOR gate is a combination of an X-OR gate and a NOT gate. The X-NOR gate is also a two input, one output concept. The output of the X-NOR gate will be logic 1 state when both the inputs assume a 0 state or when both the inputs assume a 1 state. The output of the X-NOR gate will be logic 0 state when one of the inputs assume a 0 state and the other a 1 state. It is also named as coincidence gate, because its output will be 1 only when the inputs coincide. X-NOR gate can also be used as inverter by connecting one of the two input terminals to logic 0 and also by inputting the sequence to be inverted to the other terminal.

X-NOR Gate Truth-Table

Master-Slave Flip Flop Circuit

JOHNAPRIL - 20 - 2010

3 COMMENTS9ShareBefore knowing more about the master-slave flip flop you have to know more on the basics of a J-K flip flop and S-R flip flop. To know more about the flip flops, click on the link below.

TAKE A LOOK :FLIP FLOPSTAKE A LOOK :TRIGGERING OF FLIP FLOPSMaster-slave flip flop is designed using two separate flip flops. Out of these, one acts as the master and the other as a slave. The figure of a master-slave J-K flip flop is shown below.

Master Slave Flip Flop

From the above figure you can see that both the J-K flip flops are presented in a series connection. The output of the master J-K flip flop is fed to the input of the slave J-K flip flop. The output of the slave J-K flip flop is given as a feedback to the input of the master J-K flip flop. The clock pulse [Clk] is given to the master J-K flip flop and it is sent through a NOT Gate and thus inverted before passing it to the slave J-K flip flop.

Working

When Clk=1, the master J-K flip flop gets disabled. The Clk input of the master input will be the opposite of the slave input. So the master flip flop output will be recognized by the slave flip flop only when the Clk value becomes 0. Thus, when the clock pulse males a transition from 1 to 0, the locked outputs of the master flip flop are fed through to the inputs of the slave flip-flop making this flip flop edge or pulse-triggered. To understand better take a look at the timing diagram illustrated below.

Master Slave J-K Flip Flop Timing Diagram

Thus, the circuit accepts the value in the input when the clock is HIGH, and passes the data to the output on the falling-edge of the clock signal. This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with the timing of the clock signal.

Boolean Logic

In this article, the basics of Boolean Logic is explained

Boolean Logic

In this article, the basics of Boolean Logic is explained

Boolean Logic is considered to be the basic of digital electronics. We know that a computers most basic operation is based on digital electronics. Earlier, there were operations which only humans could do. But now, these operations [and maybe more] can be done by computers. The games that we play in our computers like chess and solitaire, and even the use of Word Pad for typing documents is an application of Boolean Logic. These ideas of Boolean Logic are implemented in semiconductor chips made out of silicon and also with the help of external connecting wires. These chips do exactly whatever instructions are fed into it, and that too without a single mistake.

The Boolean Logic was first introduced by George Boole during the 1800s. He performed his concept with the help of simple logical instructions. The basic boolean operation can be further mapped into operations using bits and bytes. The most basic idea of Boolean Logic can be explained using logic gates. When the logic required becomes complex, these logic gates can be combined into more complex forms to get the required output. To know more about Boolean Logic and their applications, click on the link below.