adpt 6085278 pci express claim chart

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US Patent 6,085,278

Stillman Gates and Jamileh Davoudi

IPVALUE CONFIDENTIAL – PROPERTY OF IPVALUE MANAGEMENT INC. – ALL RIGHTS RESERVED. NOT FOR USE OR PRODUCTION IN ANY SUBSEQUENT PATENT LICENSING DISCUSSION OR LITIGATION, SOLELY TO BE USED FOR EVALUATION. SUBJECT TO DISCLAIMER FOUND ON THE FIRST PAGE OF THIS PRESENTATION.

Patent No. 6,085,278Gates et al ; Claim 1

• Title: Communications Interface

Gates et al.; Claim 1

Adapter for a Computer System Including Posting of System Interrupt Status

• Inventor: Stillman Gates and Jamileh Davoudi

Filing Date J ne 2 1998• Filing Date: June 2, 1998

• Example Impacted Claim: 1

• Illustrative Products: Intel E8500 Northbridge Chipsets Used with Core Duo Motherboards

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Claim 1Claim 1US 6,085,278

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Patent No. 6,085,278G t t l Cl i 1

Claim 1( f )


(1 of 2)1. A bus interface apparatus comprising: a host interface that is

Host System

Bus Interfacehost interface that is connectable to a bus, the bus being connectable to a host system the host system

Bus Interface Apparatus

system, the host system including a host driver; Bus

Source: Intel Web Site

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http://www.intel.com/assets/pdf/datasheet/306745.pdf, page 17



Claim 1( f )

host interface connectable to a bus


(2 of 2)1. A bus interface apparatus comprising: a host interface that ishost interface that is connectable to a bus, the bus being connectable to a host systemsystem,

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Source: Intel Web Site http://www.intel.com/assets/pdf/datasheet/306745.pdf, page 28



Claim 1


the host system including a host driver;

The Intel datasheet referenced device driver is an example host driver


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Claim 1( f )

The Intel datasheet refers to “PCI Express Device Configuration Registers” which we will see in the next slides provide a command


(1 of 2)and a command channel control and monitoring circuit coupled to the

Registers which we will see in the next slides provide a command channel control and monitoring capability for use with certain disk IO subsystems.

circuit coupled to the host interface and including a data buffer,


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http://www.intel.com/assets/pdf/datasheet/306745.pdf, pages 58



Claim 1( f )

The system memory includes the data buffer


(2 of 2)and a command channel control and monitoring circuit coupled to thecircuit coupled to the host interface and including a data buffer,

S I l W b Si

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Source: Intel Web Sitehttp://www.intel.com/assets/pdf/datasheet/306745.pdf, pages 17



Claim 1( f )


(1 of 4)the command channel control and monitoring circuit controlling andcircuit controlling and monitoring communication functionality between the data buffer and thethe data buffer and the bus;

The North Bridge chipset contains registers that are used to monitor and control communications between the bus and corresponding data buffers.

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Source: Intel Web Sitehttp://www.intel.com/assets/pdf/datasheet/306745.pdf, page 51



For example, the Independent Memory Interface status registers contain “RAID and Mirroring recovery state, Initialization state, and Hot Plug S i t t ” Th b i l f it d iti l it

Claim 1( f )


Sequencing status”. These being examples of monitored critical items.(2 of 4)the command channel control and monitoring circuit controlling andcircuit controlling and monitoring communication functionality between the data buffer and thethe data buffer and the bus;


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The E8500 NorthBridge provides controlling functions for the data flows arising from devices attached to the PCI Express bus using the PCI Express Device Control Register

Claim 1( f )


Device Control Register.(3 of 4)the command channel control and monitoring circuit controlling andcircuit controlling and monitoring communication functionality between the data buffer and thethe data buffer and the bus;


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The E8500 NorthBridge provides controlling functions for the data flows arising to and from devices attached to the PCI Express bus via memory-

d t ti h th f d t i tt h d t th XMBClaim 1( f )


mapped transactions where the memory referred to is attached to the XMB.(4 of 4)the command channel control and monitoring circuit controlling andcircuit controlling and monitoring communication functionality between the data buffer and thethe data buffer and the bus;


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Claim 1


The IMI_HPINT interrupt signals the host driver to check the IMI Status registers.

the command channel control and monitoring circuit including ancircuit including an interrupt posting status register that is readable by the host driver,


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Claim 1The Independent Memory Interface status registers contain “RAID and Mirroring recovery state, Initialization state, and Hot Plug Sequencing status”. These being examples of status information received from different


the interrupt posting status register consolidating a

functional blocks in a RAID controller which is coupled to the Host bus via the NB and PCI Express bus.

consolidating a summary of interrupt status information of interrupts arising from a plurality of functionala plurality of functional blocks coupled to the bus,


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Claim 1

The recited “summary of interrupt status information” is provided within the IMIST register where bits 0 to 5 in the register reflect the status of the PWRINT, PRSINT, FAILINT, ATNINT, MRLINT, and XMBINT interrupt events arising from the aforementioned functional blocks


the interrupt posting status register consolidating a

events arising from the aforementioned functional blocks.

consolidating a summary of interrupt status information of interrupts arising from a plurality of functionala plurality of functional blocks coupled to the bus,


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Claim 1 The Independent Memory Interface status (IMIST) registers are “readable by the host driver to investigate a cause of the interrupt status ” We read that


the interrupt posting status register being readable by the host

the host driver to investigate a cause of the interrupt status. We read that this is performed “by software” when it gets an IMI_HPINT, and the software determines the cause of an IMI_HPINT interrupt be examining the status of the PWRINT, PRSINT, FAILINT, ATNINT, MRLINT, and XMBINT data bits in the register.readable by the host

driver to investigate a cause of the interrupt statue;.

This is a transcription mistake in the patent when the PTO printed the final issued patent, evidenced by the


yprosecution history in which this error did not occur in the application and revisions.

Please read “status”

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SupplementarySupplementary

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adpt 6085278 pci express claim chart

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