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advanced performance architecture description

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DDR2 Memory Controller IP Core Local Bus 8-128 Bytes Wide 400 MHz Memory Performance DDR2 SDRAM (256-bit) H-V Scaler Frame Rate Converter HDMI Transmitter (1080p) PCIe Interface HDMI Receiver (720p) HyperDrive Multi-port DDR2 Memory Controller LVDS Output 6-Port Example: Medical Equipment HDTV Display Key Features • 400 MHz DDR2 memory performance • Up to 10 local bus RD or WR ports • Full or half-rate local bus • Configurable FIFO depth: 16 to 2048 bytes • Memory data width: up to 128 bits 8/16/32/64/128-bit • Local bus width from 16 to 256-bits • Intelligent SDRAM burst caching minimizes wait-states • Layout independent DDR Round-Trip capture scheme • Multiple time domain clocking • Configuration GUI streamlines design process • Supports Cyclone I, II, III*, Stratix I, II, III* and GX * Pending verification Advanced Performance Architecture • 267/400 MHz Cyclone II/Stratix II memory performance • Source synchronous clocking simplifies timing closure • Configurable FIFO optimizes streaming video applications • Configurable memory and local bus data width • SDRAM DQ/DQS groups not restricted to dedicated DQ pins • Local bus operates at full/Half-rate of DDR2 bus • Round-robin bus arbitration Description The Microtronix HyperDrive Multi-port DDR2 Memory Controller IP Core levitates FPGA based hardware designs to a whole new level of performance. It is built around a new DDR2 state machine controller, and an interleaved FIFO architecture which allows the local bus data path operates either at full-rate, (twice the DDR2 databus width) or at half-rate with a bus width of 4X four times the DDR2 databus interface. In a Cyclone device, the local bus operates at half-rate only. A proprietary Microtronix data capture technique enables 400 MHz DDR2 performance in a Stratix II device. The memory controller supports burst memory RD/WR access cycles and handles all memory tasks, including initialization and refresh cycles. The core integrates: a burst DDR2 memory controller core, a port arbitrator and an intelligent look-ahead FIFO controller into one easy-to-use core. The core supports up to ten independently clocked streaming-data sources operating from one shared high bandwidth memory system. With a few clicks of a mouse and within minutes, using the intuitive Microtronix GUI interface, designers can create a multi-port system, a design task which would normally take several man-months of effort! Target Applications The HyperDrive DDR2 core is targeted at applications requiring ultra high-performance memory subsystems including; HDTV consumer electronics, video conversion/enhancement equipment, military vision systems, medical imaging, data networking, Ethernet, PCIe, data recorders.

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Page 1: Advanced Performance Architecture Description

DDR2 Memory Controller IP Core

Local Bus8-128 Bytes

Wide

400 MHz Memory

Performance

DDR2 SDRAM(256-bit)

H-VScaler

Frame RateConverter

HDMITransmitter

(1080p)

PCIeInterface

HDMIReceiver(720p)

HyperDriveMulti-port

DDR2 MemoryController

LVDSOutput

6-Port Example: Medical Equipment HDTV Display

Key Features

• 400MHzDDR2memoryperformance• Upto10localbusRDorWRports• Fullorhalf-ratelocalbus• ConfigurableFIFOdepth:16to2048bytes• Memorydatawidth:upto128bits8/16/32/64/128-bit• Localbuswidthfrom16to256-bits• IntelligentSDRAMburstcachingminimizeswait-states• LayoutindependentDDRRound-Tripcapturescheme• Multipletimedomainclocking• ConfigurationGUIstreamlinesdesignprocess• SupportsCycloneI,II,III*,StratixI,II,III*andGX

* Pending verification

Advanced Performance Architecture

• 267/400MHzCycloneII/StratixIImemoryperformance• Sourcesynchronousclockingsimplifiestimingclosure• ConfigurableFIFOoptimizesstreamingvideoapplications• Configurablememoryandlocalbusdatawidth• SDRAMDQ/DQSgroupsnotrestrictedtodedicatedDQpins• Localbusoperatesatfull/Half-rateofDDR2bus• Round-robinbusarbitration

Description

TheMicrotronixHyperDriveMulti-portDDR2MemoryControllerIPCorelevitatesFPGAbasedhardwaredesignstoawholenewlevelofperformance.ItisbuiltaroundanewDDR2statemachinecontroller,andaninterleavedFIFOarchitecturewhichallowsthelocalbusdatapathoperateseitheratfull-rate,(twicetheDDR2databuswidth)orathalf-ratewithabuswidthof4XfourtimestheDDR2databusinterface.InaCyclonedevice,thelocalbusoperatesathalf-rateonly.AproprietaryMicrotronixdatacapturetechniqueenables400MHzDDR2performanceinaStratixIIdevice.

ThememorycontrollersupportsburstmemoryRD/WRaccesscyclesandhandlesallmemorytasks,includinginitializationandrefreshcycles.Thecoreintegrates:aburstDDR2memorycontrollercore,aportarbitratorandanintelligentlook-aheadFIFOcontrollerintooneeasy-to-usecore.

Thecoresupportsuptotenindependentlyclockedstreaming-datasourcesoperatingfromonesharedhighbandwidthmemorysystem.Withafewclicksofamouseandwithinminutes,usingtheintuitiveMicrotronixGUIinterface,designerscancreateamulti-portsystem,adesigntaskwhichwouldnormallytakeseveralman-monthsofeffort!

Target Applications

TheHyperDriveDDR2coreistargetedatapplicationsrequiringultrahigh-performancememorysubsystemsincluding;HDTVconsumerelectronics,videoconversion/enhancementequipment,militaryvisionsystems,medicalimaging,datanetworking,Ethernet,PCIe,datarecorders.

Page 2: Advanced Performance Architecture Description

Technical Description

TheMicrotronixHyperDdriveDDR2MemoryControllerIPCorebuildsupontheproprietarysource-synchronousdatacapturetechnologydevelopedinourfirstgenerationSDRAMcontrollers.ThecoredecouplestheDDR2statemachinecontrollerfromthehigh-speeddatapath,decreasingtimingconstraintsandimprovestimingclosureboostingperformancebyover30%.ThefmaxperformanceconstraintoftheinternalmemoryblocksisresolvedbyinterleavingthelocalbusFIFOsenablingthemtooperateathalfdatarateofthememoryinterface.TheCycloneIIcoreimplementationoperatesinthishalf-ratemodeonly.

Aproprietarysource-synchronousdesigntechniqueisusedforcapturingthehigh-speedDDR2datafromthememorydevicesindependentoftheround-tripdelay.TheschememakesIPcoretimingsindependentofthePCBlayouttracelengthsignaldelayandanyassociatedimpedancevarianceoftheboardfabricationprocess.Theuseofsource-synchronousdatacaptureclockingalsofreestheIPcoredesigntaskfromthePCBdesignstepandreducestheFPGAdesigncompilationtoasimpletwo-stepprocess!

Source-synchronousdatacapturealsoboostsmemoryperformancebyremovingtheextraresynchronizationclocksrequiredbyPLLbased

designs.Thisexpandsthedatacapturetimingmarginsextendingtemperatureperformanceandenablingfastertimingclosureinthedesignfittingprocess.AnadditionalsidebenefitisthattheSDRAMdatapinsarenolongerrestrictedtotheuseofdedicatedDQpins,increasingdesignflexibilityandavailableIOpinsthusreducingpackageconstraints.

TheportscanbeconfiguredforeitherRDorWRaccess.ByusingFIFO’stobridgethetimedomainofthelocalbusportstotheSDRAMmemoryclockdomain,eachportcanbeindependentlyclockedattheiroptimaldesignfrequency.PortFIFObufferdepthcanalsobeconfigured(from16to2048bytes)tothematchcharacteristicsofthestreamingdatadeviceandprovidedforextendedburstpipelined

memorycycleseliminatingCASlatencyoverheadencounteredusingashortburstaccesscontroller.InternallytheFIFO’sarepartitionedintotwobanksallowingtheinputandoutputofeachtobefilledoremptiedsimultaneously.

NORTHAMERICANHEADOFFICELONDON,CANADA

PHONE:+15196900091TOLL-FREE:+18886900091

Other Features and IP Core Deliverables

• ModelSim/VHDLprecompiledsimulationslibrary• OnDieTermination(ODT)improvessignalintegrity• Includeslicenseand1yearofupdates• AlteraOpenCorePlusevaluation• Customcoresareavailable.

Ordering Info

• SKU:6243-01-01HyperDriveMulti-portDDR-2MemoryControllerIPCore

• www.microtronix.com

MemoryTimingGUI

MemoryConfigurationGUI

PortConfigurationGUI

MEMORY PERFOMANCE (MHZ)

DEVICE SPEEDGRADE DDR2

ArriaGX -6 300

StratixIII -4,-3,-2 300,333,400

StratixII/GX -5,-4,-3 300,333,367


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