DDR2 Memory Controller IP Core
Local Bus8-128 Bytes
Wide
400 MHz Memory
Performance
DDR2 SDRAM(256-bit)
H-VScaler
Frame RateConverter
HDMITransmitter
(1080p)
PCIeInterface
HDMIReceiver(720p)
HyperDriveMulti-port
DDR2 MemoryController
LVDSOutput
6-Port Example: Medical Equipment HDTV Display
Key Features
• 400MHzDDR2memoryperformance• Upto10localbusRDorWRports• Fullorhalf-ratelocalbus• ConfigurableFIFOdepth:16to2048bytes• Memorydatawidth:upto128bits8/16/32/64/128-bit• Localbuswidthfrom16to256-bits• IntelligentSDRAMburstcachingminimizeswait-states• LayoutindependentDDRRound-Tripcapturescheme• Multipletimedomainclocking• ConfigurationGUIstreamlinesdesignprocess• SupportsCycloneI,II,III*,StratixI,II,III*andGX
* Pending verification
Advanced Performance Architecture
• 267/400MHzCycloneII/StratixIImemoryperformance• Sourcesynchronousclockingsimplifiestimingclosure• ConfigurableFIFOoptimizesstreamingvideoapplications• Configurablememoryandlocalbusdatawidth• SDRAMDQ/DQSgroupsnotrestrictedtodedicatedDQpins• Localbusoperatesatfull/Half-rateofDDR2bus• Round-robinbusarbitration
Description
TheMicrotronixHyperDriveMulti-portDDR2MemoryControllerIPCorelevitatesFPGAbasedhardwaredesignstoawholenewlevelofperformance.ItisbuiltaroundanewDDR2statemachinecontroller,andaninterleavedFIFOarchitecturewhichallowsthelocalbusdatapathoperateseitheratfull-rate,(twicetheDDR2databuswidth)orathalf-ratewithabuswidthof4XfourtimestheDDR2databusinterface.InaCyclonedevice,thelocalbusoperatesathalf-rateonly.AproprietaryMicrotronixdatacapturetechniqueenables400MHzDDR2performanceinaStratixIIdevice.
ThememorycontrollersupportsburstmemoryRD/WRaccesscyclesandhandlesallmemorytasks,includinginitializationandrefreshcycles.Thecoreintegrates:aburstDDR2memorycontrollercore,aportarbitratorandanintelligentlook-aheadFIFOcontrollerintooneeasy-to-usecore.
Thecoresupportsuptotenindependentlyclockedstreaming-datasourcesoperatingfromonesharedhighbandwidthmemorysystem.Withafewclicksofamouseandwithinminutes,usingtheintuitiveMicrotronixGUIinterface,designerscancreateamulti-portsystem,adesigntaskwhichwouldnormallytakeseveralman-monthsofeffort!
Target Applications
TheHyperDriveDDR2coreistargetedatapplicationsrequiringultrahigh-performancememorysubsystemsincluding;HDTVconsumerelectronics,videoconversion/enhancementequipment,militaryvisionsystems,medicalimaging,datanetworking,Ethernet,PCIe,datarecorders.
Technical Description
TheMicrotronixHyperDdriveDDR2MemoryControllerIPCorebuildsupontheproprietarysource-synchronousdatacapturetechnologydevelopedinourfirstgenerationSDRAMcontrollers.ThecoredecouplestheDDR2statemachinecontrollerfromthehigh-speeddatapath,decreasingtimingconstraintsandimprovestimingclosureboostingperformancebyover30%.ThefmaxperformanceconstraintoftheinternalmemoryblocksisresolvedbyinterleavingthelocalbusFIFOsenablingthemtooperateathalfdatarateofthememoryinterface.TheCycloneIIcoreimplementationoperatesinthishalf-ratemodeonly.
Aproprietarysource-synchronousdesigntechniqueisusedforcapturingthehigh-speedDDR2datafromthememorydevicesindependentoftheround-tripdelay.TheschememakesIPcoretimingsindependentofthePCBlayouttracelengthsignaldelayandanyassociatedimpedancevarianceoftheboardfabricationprocess.Theuseofsource-synchronousdatacaptureclockingalsofreestheIPcoredesigntaskfromthePCBdesignstepandreducestheFPGAdesigncompilationtoasimpletwo-stepprocess!
Source-synchronousdatacapturealsoboostsmemoryperformancebyremovingtheextraresynchronizationclocksrequiredbyPLLbased
designs.Thisexpandsthedatacapturetimingmarginsextendingtemperatureperformanceandenablingfastertimingclosureinthedesignfittingprocess.AnadditionalsidebenefitisthattheSDRAMdatapinsarenolongerrestrictedtotheuseofdedicatedDQpins,increasingdesignflexibilityandavailableIOpinsthusreducingpackageconstraints.
TheportscanbeconfiguredforeitherRDorWRaccess.ByusingFIFO’stobridgethetimedomainofthelocalbusportstotheSDRAMmemoryclockdomain,eachportcanbeindependentlyclockedattheiroptimaldesignfrequency.PortFIFObufferdepthcanalsobeconfigured(from16to2048bytes)tothematchcharacteristicsofthestreamingdatadeviceandprovidedforextendedburstpipelined
memorycycleseliminatingCASlatencyoverheadencounteredusingashortburstaccesscontroller.InternallytheFIFO’sarepartitionedintotwobanksallowingtheinputandoutputofeachtobefilledoremptiedsimultaneously.
NORTHAMERICANHEADOFFICELONDON,CANADA
PHONE:+15196900091TOLL-FREE:+18886900091
Other Features and IP Core Deliverables
• ModelSim/VHDLprecompiledsimulationslibrary• OnDieTermination(ODT)improvessignalintegrity• Includeslicenseand1yearofupdates• AlteraOpenCorePlusevaluation• Customcoresareavailable.
Ordering Info
• SKU:6243-01-01HyperDriveMulti-portDDR-2MemoryControllerIPCore
• www.microtronix.com
MemoryTimingGUI
MemoryConfigurationGUI
PortConfigurationGUI
MEMORY PERFOMANCE (MHZ)
DEVICE SPEEDGRADE DDR2
ArriaGX -6 300
StratixIII -4,-3,-2 300,333,400
StratixII/GX -5,-4,-3 300,333,367
