advanced vlsi design (ece 695kr) - purdue engineeringvlsi/courses/ee695kr/s2008/... · 1...

1Nano-electronic Research Lab. Kaushik Roy

Advanced VLSI Design(ECE 695KR)

Kaushik RoyProfessor of ECEPurdue University


Acknowledgement

Professor Supriyo DattaSwaroop GhoshProfessor Chris KimProfessor Swarup BhuniaProfessor Saibal MukhopadhyaySRC, Intel, AMD,..


Course OverviewTargeted for graduate students who have already taken basic VLSI design classesReal world challenges and solutions in designing high-performance and low-power circuitsRelations to VLSI Design» Recent developments in digital IC design» Project oriented» Student participation: class presentation


PrerequisiteMOS VLSI Design or equivalent» MOS transistor» Static, dynamic logic» Adders, Multipliers,..» ….

Familiarity with VLSI CAD tools» Magic or Cadence: LVS, DRC» HSPICE

Basic knowledge on solid-state physics


Class MaterialsLecture notes: primary referenceK. Roy, S. Prasad, Low Power CMOS VLSI Circuit Design, John WileyA. Chandrakasan, W. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2001.Y. Taur, T. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 2002.J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, Prentice Hall, 2nd edition, 2003. (prerequisite)


Approximate Course OutlineIntroduction -- Importance of Power, Speed, & Reliability in scaled technologies and technology requirements

» Digital computing and transistor as a switch. Basic switch characteristics required for efficient and low-energy computing

» Ion/Ioff ratio and CV/I as a measure of device “good-ness”» Power dissipation and the minimum energy required for computing –

comparison with today’s power dissipation and computational needs. What can possibly be done to improve power while being speed-efficient.

Transistors and scaling of technology» Bottom-up approach starting from molecules to bulk» Bulk-Si, Double-gate, Tri-gate devices and possible circuit implications» Emerging technologies and possible circuit implications

Device/Circuit co-design for speed/power/reliability» Inverters, Logic» Memory bit-cell


Course Outline (cont’d)Leakage components, estimation and leakage tolerant design techniques

» Subthreshold, Gate, Junction tunneling, GIDL, Diode leakage etc.» Memory and logic design for leakage tolerance» Scalability of leakage tolerant design techniques

Parameter variations – spatial and temporal – due to process, NBTI, Hot-electron, TDDB

» OPC» Sensors to detect process corners/reliability degradation» Failure analysis for memories and logic

Design with unreliable components» Logic and memories

Low-voltage design including digital subthreshold operationsInterconnects and its impact on scaled technologies. Possible solutions at the technology, circuit, architecture levelLow-power and process-tolerant design solutions at the algorithm and architecture level

» Digital signal processing applications» General purpose computing


Grading etc.Semester long project (report due on the last week of class) – 60% of the grade» Project of your choice but discuss with me to get approval» If you have difficulty finding a topic, I can help» Presentation of your work – mid-semester and end-of the

semester» Project should be of publishable quality and the report

should be of normal conference paper format (6 pages, double column etc.)

» Best and second best project (determined by a panel of judges) will be rewarded with a cache prize (~$350-500/per student) and a plaque. Funded by AMD. So do your best.

Homeworks and presentations on topics of current interest – 40% of grade. Problems will be given throughout the semester. Each student will take turns to post the homework solutions.


CAD ToolsCadence» Schematic editor, layout editor, DRC, LVS

HSPICE, awavesTechnology files» TSMC 0.18μm, BPTM 70nm, …

Synopsys design compiler, library compilerTaurus-device, Taurus-Medici

Everyone should have some experience with these tools


Project TopicStudents pick the research topic they want to work onAfter the literature survey, choose a paper that you would like to evaluate yourselfHas to be on digital VLSI circuit/system» Op-amp design alone is not acceptable» Op-amp design for digital applications is acceptable

Show your work’s claim using your own simulationsYour contribution must be clearly shown at the end» Improve previous design» New circuit/system, modeling technique» Show limitation of previous techniques

Talk to the instructor in case you need help


How to Find a Project Topic?Conferences» International Solid-State Circuits Conference (ISSCC,

top conference!): slides posted on IEEExplore» Symposium on VLSI Circuits (VLSIC), DAC, ICCAD» Custom Integrated Circuits Conference (CICC)» ……

Journal» IEEE TVLSI, IEEE TCAD, IEEE TED» IEEE Journal of Solid-State Circuits (JSSC)» Intel Technology Journal» IBM Journal on R & D» …..


How to Find a Project Topic?Funding agencies» Research needs document (www.src.org)

Presentation» University of Michigan VLSI seminar series

(www.eecs.umich.edu/vlsi_seminar/)» Design automation conference (www.dac.com)

Pick a recent issue in VLSI design (< 5 years)I suggest you start doing the literature survey ASAP


Academic MisconductStudents caught engaging in an academically dishonest practice will receive a failing grade for the course. University policy on academic dishonesty will be followed strictly.

14

Trend to Miniaturization of Convergent Systems

1970 1980 1990 2000

100

1000

10000

100000

Vol

ume(

cm3 )

W/S

SMART“Watch” & Bio-sensor

SINGLE FUNCTION

MULTIFUNCTION

MEGAFUNCTION

Notebook

PC

LaptopCellular

Func

tiona

l Den

sity

or

Com

pone

nt D

ensi

ty /

cm3 )

15

Vision of Digital Convergence by 1000X (Source: GeorgiaTech PRC)

Digital + Analog + RF + Optical+Sensors

•Computing/Internet

•Digital Audio

•Digital Imaging/Video

•Cellular/Wireless

•GPS/Satellite

•Sensors

•And, of course, timekeeping!

16

Package & IC Integration to 3D SOP3D Metric: Transistors / cm3 or Components/cm3

ICICPACKAGE

PWB

SOBSOB

PWB }FlashFlash RAMRAM

MicroprocessorMicroprocessor

Embedded Actives & Embedded Actives & PassivesPassivesRF:RF: Antennas, MEMS Antennas, MEMS Switches, Switches, R,L,CsR,L,Cs, Ultra Thin , Ultra Thin Si, Thin CoreSi, Thin CoreDigital:Digital: DecapsDecaps, Nano TIM, , Nano TIM, Nano Interconnections, Nano Interconnections, Nano Heat TransferNano Heat TransferNanoNano && MMO BatteriesMMO BatteriesOptoelectronics:Optoelectronics:detectors, waveguidesdetectors, waveguides

SIPSIP SOPSOP

CMOS DEVICECMOS DEVICE

PASTPAST PRESENTPRESENT FUTUREFUTURE

VOLU

ME

VOLU

ME

}

MEDIUMMEDIUMVOLUMEVOLUME

VERY LOWVERY LOWVOLUMEVOLUME

HIGHHIGHVOLUMEVOLUME

ICIC


A physical system as a computing medium

We need to create a bit first. Information processing always requires physical carrier, which are material particles.

First requirement to physical realization of a bit implies creating distinguishable states within a system of such material particles.

The second requirement is conditional change of state.

The properties of distinguishability and conditional change of state are two fundamental properties of a material subsystem to represent information. These properties can be obtained by creating energy barriers in a material system.


Particle Location is an Indicator of State

1 1 0 0 1 0


Barrier engineering in semiconductors

n n

p

By doping, it is possible to create a built-in field and energy barriers of controllable height and length within semiconductor. It allows one to achieve conditional complex electron transport between different energy states inside semiconductors that is needed in the physical realization of devices for information processing.


Moore’s Law

Intel founder and chairman Gordon Moore predicted in 1965 that the number of transistors on a chip will double every 18-24 months


Transistor Scaling

Constant E-field scaling: voltage and dimensions (both horizontal and vertical) are scaled by the same factor k, (~1.4), such that the electrical field remains unchanged.


Technology Scaling

22 7.0

reduction)delay (30% 7.07.0

7.07.0 )(

,,7.0

β

ββ

ββ

ββ

⎯⎯ →⎯=

=×

⎯⎯ →⎯=

=×⎯⎯ →⎯−=

⎯⎯ →⎯⎯⎯ →⎯⎯⎯→⎯

scalesdd

scalesdd

scalestdd

scalest

scalesdd

scale

CVE

ICV

D

VVTkWI

VVDimensions

ox


IC Frequency & Power Trends

Clock frequency improves 50%Gate delay improves ~30% Power increases 50%Power =CL V2 f

Freq

uenc

y (M

Hz)

1.0 0.8 0.6 .35 .25 .18

Technology Generation (μm)

0.01

0.1

1

10

100

1000

1 2 3 4 5 6 7

Chi

p Po

wer

(W)

0

200

400

600

800

1000

Freq

uenc

y (M

Hz)

Frequency

Power

486DX CPU

Pentium Processor

386

Pentium IIProcessor

R

R

1000

100

10

1

0.1

0.01

Chi

p Po

wer

(W

)

1000

800

600

400

200

0

Active switched capacitance “CL” is increasing.


Vdd vs. Vt scaling

Recently: constant e-field scaling, akavoltage scalingVCC ⌫ 1V

VCC & modest VT

scalingLoss in gate overdrive (VCC-VT) 1.4 1.0 0.8 0.6 .35 .25 .18

Technology Generation (μm)

0

1

2

3

4

5

0 1 2 3 4 5 6 7

VC

C o

r VT (V

)

VT=.45V

VCC=1.8V

VCC

VT

(VCC- VT)Gate over drive

V CC o

r V T

(V)

5

4

3

2

1

0

Voltage scaling is good for controlling IC’s active power, but it requires aggressive VT scaling for high performance


Delay

2WW

1 .τ =

−+

CL Tox

VDDVT

VDDn p

05 05

0 3 0 9 13

2. .

. ( . ) .( ) [1]

[1] C. Hu, “Low Power Design Methodologies,”Kluwer Academic Publishers, p. 25.

D

DDLd I

VC=τ

2)1()2

(DD

TDDox

Ld

VV

VCL

WC

−=

μτ

)1(DD

TSATox

Ld

VVWC

C

−=

υτ

Long Channel MOSFET

Short Channel MOSFET

Performance significantly degrades when VDD approaches 3VT.


VT Scaling: VT and IOFF Trade-off

As VT decreases, sub-threshold leakage increases

Leakage is a barrier to voltage scaling

Performance vs Leakage:

VT ↓ IOFF ↑ ID(SAT) ↑ Low VT

High VT

VGVTL VTH

I DS

IOFFL

IOFFH

VD = VDDfixed Tox

ID(SAT)

)()( 3 TGSSAToxeffD VVCWKSATI −∝ υ

22 )()( TGS

eff

effD VVK

LW

SATI −∝

)(1

TGS VV

eff

effsubthOFF eK

LW

II −∝∝


Constant Field Scaling

11/k1/k1

Electric field (E)Capacitance (C=εA/t)Current (I)Channel resistance (Rch)

Device parameters

1/k1/k2

1/k3

k2

1

Delay (CV/I)Power (VI)Switching energy (CV2)Circuit density (1/A)Power density (P/A)

Circuit parameters

1/kk

1/k

Device dimensions (tox, L, W, Xj)Doping concentration (Na, Nd)Voltage (V)

Scaling assumptions

FactorDevice and circuit parameters


Scaling in the Vertical Dimension

Transistor Vt rolls off as the channel length is reducedShallow junction depth reduces Vt roll-offHowever, sheet resistance increases


Scaling in the Vertical Dimension

Vertical dimension scales less than horizontalAggravates short channel effect (Vt roll-off)


Constant Voltage Scaling

k1/kk

1/k

Electric field (E)Capacitance (C=εA/t)Current (I)Channel resistance (Rch)

Device parameters

1/k2

k1/kk2

k3

Delay (CV/I)Power (VI)Switching energy (CV2)Circuit density (1/A)Power density (P/A)

Circuit parameters

1/kk1

Device dimensions (tox, L, W, Xj)Doping concentration (Na, Nd)Voltage (V)

Scaling assumptions

FactorDevice and circuit parameters


Constant Voltage ScalingMore aggressive scaling than constant fieldLimitations» Reliability problems due to high field» Power density increases too fast

Both constant field and constant voltage scaling have been followed in practiceField and power density has gone up as a byproduct of high performance, but till now designers are able to handle the problems


ITRS Roadmap

International Technology Roadmap for Semiconductors 2002 projection (http://public.itrs.net/)


Transistor Scaling

65nm is in production, 45-30nm in research phaseNew technology generation introduced every 2-3 years


Cost per Transistor

You can buy 10M transistors for a buckThey even throw in the interconnect and package for free


Transistors Shipped Per Year

Today, there are about 100 transistors for every ant - Gordon Moore, ISSCC ‘04


Transistors per Chip

1.7B transistors in Montecito (next generation Itanium)Most of the devices used for on-die cache memory


Chip Frequency

30% higher frequency every new generation


Die Size

~15% larger die every new generationThis means more than 2X increase in transistors per chip


Supply Voltage Scaling

Supply voltage is reduced for active power controlfVCP ddactive

2∝


4 Decades of Transistor Scaling:Itanium 2 Processor


Power Density

Year

Pow

er d

ensi

ty (W

/cm

2 )

High-end microprocessors: Packaging, coolingMobile/handheld applications: Short battery life


Active and Leakage Power

Year

Pow

er (W

)

Transistors are becoming dimmersdd

t

L

VVCdelay

−∝

1)

/exp(

qmkTV

I tleak

−∝


Leakage Power Crawling Up in Itanium 2

Transistor leakage is perhaps the biggest problem


Leakage Power versus Temp.

Leakage power is problematic in active mode for high performance microprocessors

0.18μ, 15mm die, 1.4V

0% 0% 1% 1% 2% 3% 5% 7% 9%

-10203040506070

30 40 50 60 70 80 90 100

110

Temp (C)

Pow

er (W

atts

) LeakageActive

0.1μ, 15mm die, 0.7V

6% 9% 14%19%26%

33%41%

49%

56%

-10203040506070

30 40 50 60 70 80 90 100

110

Temp (C)

Pow

er (W

atts

)

LeakageActive


Thermal Runaway

Destructive positive feedback mechanismLeakage increases exponentially with temperatureMay destroy the test socket thermal sensors required

Increased heating

Higher leakage

Higher power dissipation

Increased static current


Gate Oxide Thickness

Electrical tox > Physical toxDue to gate depletion and carrier quantization in the channel


Gate Tunneling Leakage

MOSFET no longer have infinite input resistanceImpacts both power and functionality of circuits


Process Variation in Processors

Fast chips burn too much powerSlow chips cannot meet the frequency requirement


Process Variation in Transistors

More than 2X variation in Ion, 100X variation IoffWithin-dies, die-to-die, lot-to-lot

0.4

0.6

0.8

1.0

1.2

1.4

0.01 0.1 1 10 100

Normalized IOFF

Nor

mal

ized

I ON

NMOSPMOS

100X

2X

150nm, 110°C


Sources of Process Variation

Intrinsic parameter variation (static)- Channel length, random dopant fluctuation

Environmental variation (dynamic)- Temperature, supply variations


Sub-wavelength Lithography


Line Edge/Width Roughness

Ioff and Idsat impacted by LER and LWR


Random Dopant Fluctuation

Vt variation caused by non-uniform channel dopant distribution


Supply Voltage Integrity

IR noise due to large current consumptionLdi/dt noise due to new power reduction techniques (clock gating, power gating, body biasing) with power down mode


Supply Voltage IntegrityDegrades circuit performanceSupply voltage overshoot causes reliability issuesPower wasted by parasitic resistance causes self-heatingVdd fluctuation should be less than 10%

Courtesy IBM


Design complexity surpasses manpowerEffective CAD tools, memory dominated chips

Productivity Gap


Lithography Tool Cost

What will end Moore’s law, economics or physics?


Interconnect ScalingGlobal interconnects get longer due to larger die sizeWire scaling increases R, L and C

Example: local vs. global interconnect delay


Interconnect Delay Problem

Local interconnect has sped up (shorter wires)Global interconnect has slowed down (RC doesn’t scale)

1997 SIA technology roadmap


Interconnect Metal Layers

Local wires have high density to accommodate the increasing number of devicesGlobal wires have low RC (tall, wide, thick, scarce wires)

M1M2M3M4

M5

M6

Nano-electronic Research Lab. Kaushik Roy

Interconnect distribution scaling trends

• RC/μm scaling trend is only one side of the story...

10 100 1,000 10,000 100,000Length (u)

No

of n

ets

(Log

Sca

le)

Pentium Pro (R)Pentium (R) IIPentium (M MX)Pentium (R)Pentium (R) II

Sour

ce: I

ntel


Power Delivery & Distribution Challenges

• High-end microprocessors approaching > 10 GHz• How to deliver and distribute ~100A at < 1V for < $20!• On-die power density >>> hot-plate power density

• crossover happened back in 0.6μm technology! • di/dt noise only worsening with scaling: drivers are one of the sources.

P6P5

P4P3

1.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+071.E+08

1.5 1

0.8

0.6

0.35

0.25

0.18

0.13

0.09

0.06

di/d

t in

AU

Lead Processors

First compaction

Second compaction

0

10

20

30

40

50

60

70

Wat

ts/c

m2

Nano-electronic Research Lab. Kaushik Roy

Example multi-layer system

0.80 x 1.6μm

0.64μm

1.6μm

0.32 x 0.64μm0.64μm0.25 x 0.48μm0.50μm

M4

M5

M3

M2

M1PolySubstrate

0.32 x 0.64μm

1.00 x 1.80μm2.00μm

M6

1.00 x 1.80μm2.00μm

M7 Al

0.80 x 1.6μm1.6μm

K. Soumyanath et. al. [2]


Cross Talk Noise

As wires are brought closer with scaling, capacitive coupling becomes significantAdjacent wires on same layer have stronger coupling


Cross Talk Noise

Multiple aggressors multiple victims possibleCross talk noise can cause logic faults in dynamic circuits


Cross Talk and DelayCapacitive cross talk can affect delayIf aggressor(s) switch in opposite direction, effective coupling capacitance is doubled On the other hand, if aggressor(s) switch in the same direction, Cc is eliminatedSignificant difference in RC delay depending on adjacent switching activity


Soft Error In Storage Nodes

Soft errors are caused by » Alpha particles from package materials» Cosmic rays from outer space

Logic 1 Logic 0

Vinduced


Soft Error In Storage Nodes

Error correction codeShieldingSOIRadiation-hardened cell


More Roadblocks

Memory stabilityLong term reliabilityMixed signal design issuesMask costTesting multi-GHz processorsSkeptics: Do we need a faster computer?…

Eventually, it all boils down to economics


SummaryDigital IC Business is Unique

Things Get Better Every Few YearsCompanies Have to Stay on Moore’s Law Curve to Survive

Benefits of Transistor ScalingHigher Frequencies of OperationMassive Functional Units, Increasing On-Die MemoryCost/MIPS Going Down

Downside of Transistor ScalingPower (Dynamic and Static)Process VariationDesign/Manufacturing Cost….

advanced vlsi design (ece 695kr) - purdue engineeringvlsi/courses/ee695kr/s2008/... · 1...

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