advantages of sce-mi based - t&vsadvantages of sce-mi based bfm’s presented by: bharath mp
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Advantages of SCE-MI Based
BFM’s
Presented by: Bharath MP
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Introduction to SCE-MI
Drawbacks in existing Emulation platform
SCE-MI as a solution for effective Co-Emulation
Generic Architecture of Co-Emulation Modeling
Approach in building SCE-MI based environment
Use-MODEL as Ethernet
Contents
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To provide communication between the testbench which is in high level language like SystemC or UVM (s/w side) and the IP component placed
in FPGA on an emulation board(H/W side) through SCE-MI infrastructure. Interfacing software models to emulators. s/w side H/w side •
Introduction
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Unable to reuse the testbench used for Simulation based verification in the Emulation platform. Thus requires more effort, cost and time to recreate the same for the emulation platform.
All emulators uses proprietary API's. This makes very difficult for software products to port to the different emulators thus restricting the solutions available to the customers. This in turn leads to low productivity and low return on investment who build their own solutions.
The existing API's are signal/pin level oriented and not transaction level.
Customers are reluctant to invest in building applications on proprietary APIs
Drawbacks in existing Emulation Platform
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Enables the reuse of existing testbench used for simulation based verification to be used for emulation platform. Thereby reducing the effort and time.
Enables the portability of transactor models between emulation vendors and makes possible for IP developers to write only one model
Enables to reuse the transaction level scenarios generated at verification stage in the emulation platform.
Enables to develop user defined API’s and thus helps in more customization.
SCE-MI as a solution for effective Co-Emulation
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Transactor Synthesizable-
BFM
Transaction level Abstraction <-> RTL level Abstraction.
Generation of software models at high abstract level and executing on Hardware at RTL abstract level through SCE-MI API
S/W Testbench SystemC UVM/SV
RTL INTERFACE
SC
E-
MI
API
Generic Architecture of Co-Emulation Modeling
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Approach in building SCE-MI based Environment
Verilog/Vhdl DUT (Design Under Test)
SV
INF
SV TestBench
Virtual Interface (Handle to Interface)
Conventional TestBench
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TestBench for Functional/Emulation Platform
Verilog/Vhdl DUT (Design Under Test)
SV TestBench
SV
laye
r for
func
-tion
call
s
SV
xTO
R
DP
I C
or
C+
+
Synthesizable BFM
SCE-MI API Linked to C/C++ libraries
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Verilog/Vhdl DUT (Design Under Test)
SV
laye
r for
func
-tion
call
s
SV
xTO
R
DP
I C
or
C+
+
Synthesizable BFM
SCE-MI API Linked to C/C++ libraries
UVM
MON
UVM
DRIVER
UVM SB
UVM
TRANS
UVM
SEQR
Same Approach even for UVM TestBench
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Using SystemC TestBench
Verilog/Vhdl DUT (Design Under Test)
Prox
y s/w
ports
SV
xTO
R
DP
I C
or
C+
+
Synthesizable BFM
SCE-MI API Linked to C/C++ libraries
SystemC
TLM TB
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Synchronization between Transactor and TB
The most crucial and significant part in building the environment is synchronization between the Transactor and the TB
The approach involves using o Semaphores o Handshake variables o FIFO’s o Callback functions o Tasks
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USE MODEL – FUNCTION BASED MODEL EHTERNET
Ehernet
Transact
or.svh
With
Function
s,classes
Ethernet
Transacto
r.sv
DP
I C
or
C+
+
RTL
Eth_agent
Eth_driver
Test Layer
Eth_mon
Eth_seqr
Eth_sb
UVM Layer
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DPI Datatype Mapping
DPI Arguments C- MAPPED DATATYPES
bit Unsigned char
byte char
Int unsigned Unsigned int
Int int
1D Array – bit svBitVecVal
1D Array - logic svLogicVecVal
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Write Operation
• DPI-C Import & Export Functions
o import tx_wr_strt() Transactor provides start of packet indication
o export tx_wr_pkt() The generated packet from user is send to C
o import tx_wr_data() Transactor calls this after writing each data where in the written data is stored in FIFO in C.
o import tx_wr_done() Transcator after driving one complete packet
o export tx_wr_data_mon() The data from FIFO in C is given to SV TB through call back functions.
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Read Operation
• DPI-C import and export Functions :
o import rx_rd_data()
The RX data received from DUT is stored in FIFO created in C.
o import rx_rd_data_mon()
When complete packet is received by SV TB through callback
functions, indicate to C
o export rx_rd_callback()
This callback Function is called to get the read packet form FIFO in
C to SV
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QUESTIONS …???