advantages of using cmos

EECS 270C / Winter 2014 Prof. M. Green / U.C. Irvine 1

Advantages of Using CMOS

• Compact (shared diffusion regions)

• Very low static power dissipation

• High noise margin (nearly ideal inverter voltage transfer characteristic)

• Very well modeled and characterized

• Mechanically robust

• Lends itself very well to high integration levels

• “Analog” CMOS process usually includes non-salicided poly layer for linear resistors.

• SiGe BiCMOS is very useful but is a generation behind currently available standard CMOS


fT is the frequency at which becomes 1.

fT gives a fundamental speed measure of a technology.

0.25 µm CMOS: fT ~ 23GHz (VDD = 2.5V)0.18 µmCMOS: fT ~ 57GHz (VDD = 1.8V)

VDD

Cgs

VGS

vgs

igid

Transistor fT Calculation


Static CMOS propagation delay:

Assume: Wp = 3Wn for optimum noise margin.

Lp = Ln = Lmin

Operation is 4X slower than theoretical maximum due to n-channel & p-channel gates connected in parallel.

(Actual values will be higher due to high diffusion capacitances present in sub-micron transistors.)

VinVout


IG

ID

fT = 57GHz

VoutVin

n-channel ac simulation to determine fT:

CMOS inverter transient simulation:

Verifying with simulation:


Single-Ended Signaling in CMOS

Series R & L cause supply/ground bounce.Resulting modulation of transistor Vt’s result in pattern-dependent jitter.

Vin Vout

sub

IDD

ISS

VDD

VSS

Vin

Vout

ISS

IDD


Rs = 0Ls = 0

clock out

Rs = 5Ls = 5nH

clock out

data in clock in clock out data out

data out

Rs = 5 Ls = 5nH

Effect of Supply/Ground Bounce on Jitter


Summary of CMOS Gate Performance

1. Simple & straightforward design.

2. Robust operation.

3. Nearly zero static power dissipation.

Advantages of static CMOS gates:

1. Full speed of transistors not exploited due to n-channel & p-channel gate in parallel at load.

2. Single-ended operation causes current spikes leading to VDD/VSS bounce.

3. Single-ended operation also highly sensitive to VDD/VSS bounce leading to jitter.

Disdvantages of static CMOS gates:


Current-Mode Logic (CML)

•Based on conventional differential pair

•Differential operation

•Inherent common-mode rejection

•Very robust in the presence of common- mode disturbances (e.g., VDD / VSS bounce)

CML inverter:VDD

Vin+ Vin-

Vout-Vout+

ISS

R R

CL CL


To keep current source transistor in saturation:

+

_

+

_

VDD

RR

ISS

VS

VGS

+_ VGS

+_

VBIAS

DC Biasing of CML Inverter


To achieve full current switching:

for correct operation

Logic Swing & Gain of CML Inverter

VDD

VDD VDD-ISSR

ISS

R R

CL CL

VDD-ISSR VDD

ISS 0


Small-signal voltage gain:

Note: rising & falling time constants are the same

Recall

for full switching

(Assuming fanout of 1)

rise/fall time constant:

Small-Signal Behavior of CML Inverter


Speed vs. Gain in Logic Circuits

Largest possibleLargest possible gain-bandwidth product is desirable.is desirable.

fast input transition:step response determined by

slow input transition:step response determined by Av


“large-signal” gain-bandwidth product

Relationship between Av , , and Vswing

Larger logic swing preferred for higher gain-bandwidth product

Larger Vswing Larger Vmin smaller W/L larger current density


Suppose we decrease current density by increasing W/L:

Slower!

Thought Experiment

R R R R

ISS ISS


Note that the load is only one gate capacitance:

CML speed ~ 2.5 times faster than static CMOS

IG

ID

fT = 57GHz

n-channel ac simulation to determine fT:

CML buffer transient simulation:


Typical Vswing:

• Should be large enough to allow sufficient gain-bandwidth product.• Should be small enough to prevent transistors from going into triode. * CML will still work in triode (unlike BJT), but there is no additional speed benefit.

Once Vswing has been chosen, designer can trade off between gain &

bandwidth by parameterizing between R & ISS:

Higher speed: ISS R

Higher gain: ISS R


Other Benefits of CML Gates

1. Constant current bias VDD / VSS bounce greatly reduced

KCL sets this current to be nearly constant.

ISS

ISS


data in clock in

Rs = 0Ls = 0

clock out

clock out

Rs = 5Ls = 5nH

clock out

data out

data out

Rs = 5 Ls = 5nH


2. Non-inverting buffer available without additional delay:

CMOS:

inverter buffer

CML:

inverter buffer

tp 2tp


Fanout & Scaling of CML Gates

1x

=

nx

=All voltages unchanged from unit-sized buffer.Currents & power increase by factor of n.

ISS

Vin+ Vin-

Vout- Vout+

R R

nISS

Vin+ Vin-

Vout- Vout+

R/n R/n


For fanout of n:

increases linearly with fanout.


From interconnect, etc.; assumed not to scale with buffer sizes

Should set degradation due to interconnect capacitance

to minimize

Power (proportional to n) determined primarily by interconnect capacitance!


Sub-micron MOSFETs obey square-law characteristics only in a limited region!

CML buffer design procedure:

1. Determine largest allowable ISS (usually limited by electromigration constraints)

2. Choose “unit-sized” n-channel transistor (typically W/L=20)

3. Run a series of simulations to determine optimum value of R:

R too small: full current switching not achieved

R too large: slower than necessary

4. Choose minimum scaling factor after laying out some test buffers of various sizes and determining approximate value of interconnect capacitance Cp.

VGS

Mobility reduction (linear)

Square-law behavior

Weak inversion (exponential)

+_VGS


1. Determine largest allowable ISS

standard layout shared drain (1/2 diffusion capacitance)

Imax independent of Wdetermined by electromigration limits


R = 1200ISSR = 480mV

tp = 12ps*R optimum*

R = 900ISSR = 360mV

tp = 10psR too small

R = 1500ISSR = 600mV

tp = 14psR too large

CML Design Procedure ExampleChoose:


Parameterizing Between Gain & Bandwidth

ISS = 100 µAR = 4.8 kAv = 9.3 dBBW = 2.6 GHz




GSCALE: Global scaling parameter (depends on Cp)MSCALE: Local scaling parameter (depends on fanout or bit rate)GBW: Gain-bandwidth parameter

Parameterized CML Buffer


CML with p-channel Active Load

p-channel load transistors operates in triode region:Increased capacitance and mismatch result

Can be used if linear resistors are not available.


Capacitance Comparison (1)

Poly resistor:

p-channel MOSFET:

gate

sub

channel


Cpoly-sub Cchannel-sub : 0.13 fF/m2

Cdepletion : 1.20 fF/m2

Cchannel-gate : 7.80 fF/m2

Poly resistor:

p-channel MOSFET: Wchannel = Wdiff = 2.5 µm Lchannel = 0.18 µm

Ldiff = 0.3 µm

Wpoly = 0.6 Lpoly = 2.5

= 0.1 fF

= 0.9 fF + 1.8 fF + .03 fF = 2.8 fF


(Numbers based on TSMC 180nm CMOS process)


R = 1.2 ks = 235

Wr = 0.6 µmLr = 2.5 µmCres = 0.1 fF

Wp = 2.5 µm Ldiff = 0.3 µm

Cd2 = 2.8 fF

M2 M2

M1 M1

M1 M1

Cd1 = 3.7 fFCg1 = 5.8 fF



Pulse Response ComparisonPWin = 100ps

resistor loadR = 1.2 k

td = 16 ps; PWout = 100 ps

p-channel load(W/L)p = 2.5 µm / 0.18 µmtd = 20 ps; PWout = 98 ps


Eye Diagram Comparisonincluding mismatch effects

resistor load

= 1.5% mismatch

160mV gate-referred mismatch

= 4% mismatch

p-channel load

ISI

DCD


MA MA

MBMB

MA MA

Series-Gated CML Topology

XOR gate:

Common-mode voltage of BP/N critical:

• Too low current source transistor biased in triode• Too high Transistors MB biased in triode


VS

I1 I2

-ISS

ISS

Slope = gm

Transistors should be biased in saturation to realize maximum gm .

Especially important when gate voltages exhibitslow slew rates

BP BN

Series-Gated CML (2)


VB(cm) = 1.6

VB(cm) = 1.3VB(cm) = 1.0

t

VB(cm) = 1.6

VB(cm) = 1.3 VB(cm) = 1.0

DC current:

Transient response:

(400mV amplitude sinewave applied to BP/BN)


Level-Shifting CML Buffer

VDD

Rcm

ISS

R R

+

_

Output levels:

Used to drive clock inputs of series-gated CML gates

• DC levels shifted down by ISSRcm

• Vswing unchanged


Be reassigning the inputs, the XOR can be transformed into a Select circuit. Used in a 2:1 multiplexer.

CML Select Circuit

ISS

R R

AP AN BP BN

SELA SELB

OUTPOUTN

SELA

AP/N

BP/N

OUTP/N


CML Latch

By setting BP/N = OUTP/N, we can construct a CML latch:

ISS

DP DN

OUTPOUTN

CKP CKN


CML D Flip-Flop

Output OUTP/N is synchronized withCKP/N falling edge.

DP DN

CKP CKN

XNXP

XP XN

OUTNOUTP

CKPCKN

CKP/N

DP/N

OUTP/N


CML Latch Design Considerations

IGG

VGG

dc operating points

Necessary criterion for bistability:

at middle operating point

(Equivalent to loop gain = gmR > 1)

slope=1/rgg

IGGVGG

R R


“transparent” latch

Avoiding Latch Transparency

XP/N


R=1000

R=800

R=600

GBW parametercan be increased toensure bistability.

XP

XN

XP XN


Buffering Clock Signals (1)

Clock signals (generated from VCO or clock divider) often drive large capacitive loads.

1x

…

Fanout = n

C

C

C

For a large fanout, attenuation of clock amplitude will occur.

1x

1x

n


…1x k x k2 xn x

m stages

Now is increased by k << n less attenuation at each stage

Delay = mktp

ktp

Power = P1(1 + k + k2 + … + n)

As fclock 1/tp then k 1; number of stages and total power become very large.

Power dissipated by first stage



Since clock signal is made up of a single frequency (+ harmonics), resonance can be used to increase gain with greatly reduced power dissipation.

Resonant frequency: at resonance

If lossless inductors were available, we could achieve high gain at any frequencysimply by choosing the correct inductor value.



On-Chip Passive Elements

Resistor:

Capacitor:

dw

substrate

(+ fringing)

Inductor:

t

t

w

l

w

Inductance calculation much more complicated!

l

l

l

l

pH/ml

ll


tw

Special case of Greenhouse result

Note for l >> w, L is a weak function of w

To increase effective inductance per unit length, we make use of mutual inductance via spiral structure:

pH/ml

ll

l


Modeling of Spiral Inductor

Design of inductor requires: • inductor simulation package (e.g., asitic) • trial and error• conversion to lumped

element model

number of turns n = 2

1

2

Accurate lumped model should include:• Series inductance (self + mutual) & resistance • Skin effect (frequency dependent series resistance)• Interwinding capacitance• Capacitance to substrate• Substrate capacitance & loss

Procedure for constructing lumped model:1. 2-port s-parameters over frequency range of interest

(this comes from the inductor simulator)2. Choose lumped circuit topology.3. Run simulations to find the optimal lumped circuit

element values such that the the circuit s-parametersare sufficiently close to the inductor’s s-parameters(can use .net and .optimize in HSPICE)


Parameters most relevant to circuit designers:• Inductance• Series resistance• Self-resonant frequency

http://rfic.eecs.berkeley.edu/~niknejad/asitic.html

Link to “asitic” web pages:

Modeling of Spiral Inductor (cont.)

Inductor magnitude impedance vs. frequency


1

2

Cint

L Rs

Cox2Cox1

Csub1 Csub2Rsub1Rsub2

1 2

L:Rs:

Cint:Cox:

Csub/Rsub:

Self/mutual inductanceSeries resistanceInterwinding capacitanceOxide capacitanceSubstrate capacitance/resistance

Values of L and Rs in lumped model should correlate with physical parameters.Values of other lumped model elements need not necessarily correlate with physical parameters.

Modeling of Spiral Inductor (cont.)


Parasitic capacitances usually combine with load capacitance L should be decreased slightly

Series Rs has more important effect:

L

Rs

C R R’CL'

At resonance, Im [Y(jr)] = 0:

Slight increase in effective inductance Very important effect!


Differential-mode groundSets common-mode output voltage

Gain at resonant frequency = gm R’

CL resonates out with L

CML Tuned Amplifiers (1)


Symmetric inductor structure can be used:

Single structure allows more inductance tobe realized from mutual coupling less series resistance



Gain is much higher at resonance, but depends completely on Rs.Variation in gain correlates with variation in metal (not resistor) sheet resistance.


Higher-gain topology:


R’CL’Vswing

+

_

Iin

IL

Let Vswing = 500mV, L=0.5nH, f =10GHz:

Spiral inductor should be wide enoughto meet ac electromigration specs.

Watch out for ac current amplitude in inductors!



Inductors in Broadband Circuits

R

R

Vin

Vout

+

_

LC lossless transmission line (Z0)

0.5 0.5

slope = -Td


Series Peaking (1)

CdCg

CdCg

Lser

With direct connection of 2 buffers,output & input capacitances are in parallel:

By connecting an inductor between the capacitors, the bandwidth and delay increase:

“Series peaking”

EECS 270C / Winter 2014 Prof. M. Green / U.C. Irvine

59

Series Peaking (2)

Cd = Cg = 16 fFR = 400

Lser

Cd Cg

R

Vin+ Vin-

Vx+

Vx-

Using set

Lser = 0BW = 6.3 GHz

Lser = 3.5 nHBW = 8.3 GHz

Lser = 3.5 nH

Lser = 0

Frequency response:

Vin

Vx (Lser = 0)

Transient response:

Vx (Lser = 3.5 nH)

Vin

Vx (Lser = 0)

Series peaking provides speed at the expense of extra delay.


Shunt-Peaking (1)

By connecting an inductor in series with the load resistor (series connection in shunt with output), more current is used, for a longer time, to charge the load capacitance.


Properties of Shunt-Peaking

Resonant frequency:

No resonance for

CL

X Re s

Im s

L = 0:pole at s = −1/RC

X O

L ≠ 0:zero at s = −R/Ladditional pole at s ≈ −(1/CR + R/L)

Frequency response:


BW = 6.3 GHz

L = 1.8 nHBW = 9.4 GHz

L = 3.7 nHBW = 14.3 GHz

Shunt-Peaking -- AC Response

Use of shunt-peakingincreases small-signal bandwidth


Shunt Peaking − Transient Response

Step Response:

td = 13.4 ps

L = 1.8 nHtd = 8.5 ps

L = 3.7 nHtd = 6.7 ps

Pulse Response (tin = 50 ps):

L = 3.7 nHtout = 50.8 psISI = 16 mUI

L = 1.8 nHtout = 50.0 psISI = 0 mUI

L = 0tout = 48.7 psISI = 26 mUI


Shunt Peaking – ISI vs. Pulse Width

ISI (UI)

Input pulse width


Other Advantages of Shunt-Peaking

• CML load is passive & linear

• Can be shown to be very robust in the presence of parasitic series resistance and shunt capacitance inductors can be placed far away from other CML circuit elements.


long metal lines

Effect of Shunt-Peaking Inductor Parasitics (1)

• Series resistance RP simply adds to R

• Shunt capacitance CP resonates with L …

L L

R R

CL CL

CL CL

L L

R R

RP RP

CPCP


Moderate amount of parasitic capacitancehas similar effect to slightly larger inductor.

Disadvantages of using passive inductors:• Consume huge die area• Difficult to design & model

Effect of Shunt-Peaking Inductor Parasitics (2)

Input pulse width

Input pulse width

ISI (UI)

ISI (UI)


Multi-layer Inductors (1)

metal 6

metal 5d

Distance d between two metal layers is much smaller than lateral distances (e.g., w, l, s)

metal 6

metal 5

d


L1 L21 2

+

_

+

_

i1 i2

2-port representation of coupled inductors:

Passivity constraint:

For metal geometries close to each other, k is close to unity.

series connection of coupled inductors:

L1 L2

i1

i2

M

1

+

_2

+

_

For L1 = L2 = L, we have:

In general, for n layers we have:

Multi-layer inductors are more appropriate for shunt-peaking than resonant structures due to additional contact resistance.



Ci

Cj

For more details, see:

A. Zolfaghari, A. Chan & B. Razavi, “Stacked inductors and transformers in CMOS technology,”IEEE Journal of Solid-State Circuits, vol. 36, April 2001, pp. 620-628.

Effective Capacitance:



metal 6 only100 x 100w = 4; s = 2; n = 4L=2.0 nHR=6.9

metal 6 over metal 446 x 46w = 4; s = 2; n = 2.5L=2.0 nHR=12.5

+


Area comparison:


Active Inductors (1)

Rgyr

+

_

v1

i1+

_

v2

i2

Ideal gyrator: Impedance inversion:

Rgyr

+

_

vin

iin

C

Port 1 exhibits inductance when port 2 is connected to a capacitance.

Matrix representation (Z-parameters):



RG

+

_

v1

i1

+

_v2

i2

i1 applied with port 2 open-circuited:

i2 applied with port 1 open-circuited:

(Assume RG gm > 1)

Complete Z-parameters (lossy/active gyrator):

Consider common-drain configuration:


+

_

vin


Interpretation of non-ideal matrix entries:


At low frequencies (Cgs open) Zsource = 1/gm

At high frequencies (Cgs short) Zsource = RG


Impedance at port 1 with port 2 terminated with transistor Cgs:


Equivalent circuit:

+

_

vin



For shunt peaking:

Low-frequency gain:

CML Buffer with Active Inductor Load


Active Inductor AC Response

RG = 4k

RG = 2k

RG = 0


Active Inductor Transient Response (1)

RG = 0PW = 97ps

RG = 5kPW = 100 ps

RG = 10kPW = 104 ps

Differential signals:


Active Inductor Transient Response (2)

Problem: n-channel load shifts output by Vt.Vsb > 0; body effects exacerbates this effect..

Single-endedinput

Single-endedoutputs

Single-ended signals:


Alternate topology:p-channel load exhibits lower Vt (Vbs = 0)

Active Inductor Alternate Topology

differential

single-ended

advantages of using cmos

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