aiman el-maleh, ali alsuwaiyan king fahd university of petroleum & minerals, dept. of computer...

Aiman El-Maleh, Ali AlsuwaiyanAiman El-Maleh, Ali Alsuwaiyan

King Fahd University of Petroleum & Minerals, King Fahd University of Petroleum & Minerals, Dept. of Computer Eng., Saudi ArabiaDept. of Computer Eng., Saudi Arabia

Aiman El-Maleh, Ali AlsuwaiyanAiman El-Maleh, Ali Alsuwaiyan

King Fahd University of Petroleum & Minerals, King Fahd University of Petroleum & Minerals, Dept. of Computer Eng., Saudi ArabiaDept. of Computer Eng., Saudi Arabia

An Efficient Test Relaxation An Efficient Test Relaxation Technique for Combinational & Technique for Combinational & Full-Scan Sequential CircuitsFull-Scan Sequential Circuits

An Efficient Test Relaxation An Efficient Test Relaxation Technique for Combinational & Technique for Combinational & Full-Scan Sequential CircuitsFull-Scan Sequential Circuits

2

OutlineOutlineOutlineOutline

IntroductionIntroduction Problem definitionProblem definition Illustrative exampleIllustrative example Proposed relaxation algorithmProposed relaxation algorithm Experimental resultsExperimental results Improving the effectiveness of test compaction & Improving the effectiveness of test compaction &

compressioncompression ConclusionConclusion

IntroductionIntroduction Problem definitionProblem definition Illustrative exampleIllustrative example Proposed relaxation algorithmProposed relaxation algorithm Experimental resultsExperimental results Improving the effectiveness of test compaction & Improving the effectiveness of test compaction &

compressioncompression ConclusionConclusion

3

IntroductionIntroductionIntroductionIntroduction

With today’s technology, complete systems with With today’s technology, complete systems with millions of transistors are built on a single chip.millions of transistors are built on a single chip.

Increasing complexity of systems-on-a-chip and its Increasing complexity of systems-on-a-chip and its test data size increased cost of testing.test data size increased cost of testing.

Test data must be stored in tester memory and Test data must be stored in tester memory and transferred from tester to chip.transferred from tester to chip.

Cost of automatic test equipment increases with Cost of automatic test equipment increases with increase in speed, channel capacity, and memory.increase in speed, channel capacity, and memory.

Need for test data reduction is imperative.Need for test data reduction is imperative.• Test compaction.Test compaction.

• Test compression.Test compression.

With today’s technology, complete systems with With today’s technology, complete systems with millions of transistors are built on a single chip.millions of transistors are built on a single chip.

Increasing complexity of systems-on-a-chip and its Increasing complexity of systems-on-a-chip and its test data size increased cost of testing.test data size increased cost of testing.

Test data must be stored in tester memory and Test data must be stored in tester memory and transferred from tester to chip.transferred from tester to chip.

Cost of automatic test equipment increases with Cost of automatic test equipment increases with increase in speed, channel capacity, and memory.increase in speed, channel capacity, and memory.

Need for test data reduction is imperative.Need for test data reduction is imperative.• Test compaction.Test compaction.

• Test compression.Test compression.

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IntroductionIntroductionIntroductionIntroduction

Effectiveness of test compaction and compression Effectiveness of test compaction and compression techniques can improve significantly if a partially techniques can improve significantly if a partially specified (specified (relaxedrelaxed) test set is provided.) test set is provided.

Most compression techniques assume a relaxed test.Most compression techniques assume a relaxed test. Compaction achieved by test vector merging of Compaction achieved by test vector merging of

compatible vectors.compatible vectors. Test relaxation can improve effectiveness of dynamic Test relaxation can improve effectiveness of dynamic

test compaction by taking advantage of random test test compaction by taking advantage of random test pattern generation.pattern generation.

Test relaxation can also help in test power reductionTest relaxation can also help in test power reduction• Specify relaxed bits to reduce number of transitions during Specify relaxed bits to reduce number of transitions during

scan.scan.

Effectiveness of test compaction and compression Effectiveness of test compaction and compression techniques can improve significantly if a partially techniques can improve significantly if a partially specified (specified (relaxedrelaxed) test set is provided.) test set is provided.

Most compression techniques assume a relaxed test.Most compression techniques assume a relaxed test. Compaction achieved by test vector merging of Compaction achieved by test vector merging of

compatible vectors.compatible vectors. Test relaxation can improve effectiveness of dynamic Test relaxation can improve effectiveness of dynamic

test compaction by taking advantage of random test test compaction by taking advantage of random test pattern generation.pattern generation.

Test relaxation can also help in test power reductionTest relaxation can also help in test power reduction• Specify relaxed bits to reduce number of transitions during Specify relaxed bits to reduce number of transitions during

scan.scan.

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Problem DefinitionProblem DefinitionProblem DefinitionProblem Definition

Given a test set of a given combinational or full-scan Given a test set of a given combinational or full-scan circuit, generate a partially specified test set that circuit, generate a partially specified test set that maintains the same fault coverage while maximizing maintains the same fault coverage while maximizing the number of unspecified bits i.e., Xs.the number of unspecified bits i.e., Xs.

Test relaxation problem has not been solved Test relaxation problem has not been solved effectively in literature.effectively in literature.

A test set can be relaxed using a brute-force methodA test set can be relaxed using a brute-force method• Every bit is tested for possibility of changing it to x by fault Every bit is tested for possibility of changing it to x by fault

simulation.simulation.

• Impractical for large circuits.Impractical for large circuits.

Dynamic compaction does not relax an already Dynamic compaction does not relax an already existing test set.existing test set.

Given a test set of a given combinational or full-scan Given a test set of a given combinational or full-scan circuit, generate a partially specified test set that circuit, generate a partially specified test set that maintains the same fault coverage while maximizing maintains the same fault coverage while maximizing the number of unspecified bits i.e., Xs.the number of unspecified bits i.e., Xs.

Test relaxation problem has not been solved Test relaxation problem has not been solved effectively in literature.effectively in literature.

A test set can be relaxed using a brute-force methodA test set can be relaxed using a brute-force method• Every bit is tested for possibility of changing it to x by fault Every bit is tested for possibility of changing it to x by fault

simulation.simulation.

• Impractical for large circuits.Impractical for large circuits.

Dynamic compaction does not relax an already Dynamic compaction does not relax an already existing test set.existing test set.

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Thus, to guarantee fault detection, G1=0 implies A=0 Thus, to guarantee fault detection, G1=0 implies A=0 (Because A is unreachable).(Because A is unreachable).

Illustrative ExampleIllustrative ExampleIllustrative ExampleIllustrative Example

G3

G1

G5

G6

G2

G4

0

00

0

0

0 1

1

1

0

0

A

B

C

D

E

0/10/1

1/01/0

0/10/1

0/10/11/01/0

1/01/000

Fault Fault excitationexcitation

Fault Fault propagationpropagation

B=0 satisfiedB=0 satisfied

Apparently, G1=0 satisfied and thus A=X Apparently, G1=0 satisfied and thus A=X (WRONG!!)(WRONG!!)

G3=0 implies C=0, DE=XX OR C=X, DE=00G3=0 implies C=0, DE=XX OR C=X, DE=00

000/00/00/x0/x

xx1/x1/x

To guarantee stem faults propagation, never justify a To guarantee stem faults propagation, never justify a controlling value from a controlling value from a reachable linereachable line..

From this example, we conclude that we need to From this example, we conclude that we need to identify reachable lines before justification.identify reachable lines before justification.

B stuck-at-1B stuck-at-1

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Proposed TechniqueProposed TechniqueProposed TechniqueProposed Technique

For every test vector For every test vector tt do doFault simulate the circuit under the test Fault simulate the circuit under the test ttFor every newly detected fault For every newly detected fault f f dodo

BuildRequirementList(BuildRequirementList( ff )) /**** Returns /**** Returns L ****/L ****/For every line For every line jj in in LL dodo

justify(justify( jj ))End forEnd for

Mark all lines as unreachableMark all lines as unreachableEnd forEnd forOutput relaxed vectorOutput relaxed vectorMark all lines as non-requiredMark all lines as non-required

End forEnd for

For every test vector For every test vector tt do doFault simulate the circuit under the test Fault simulate the circuit under the test ttFor every newly detected fault For every newly detected fault f f dodo

BuildRequirementList(BuildRequirementList( ff )) /**** Returns /**** Returns L ****/L ****/For every line For every line jj in in LL dodo

justify(justify( jj ))End forEnd for

Mark all lines as unreachableMark all lines as unreachableEnd forEnd forOutput relaxed vectorOutput relaxed vectorMark all lines as non-requiredMark all lines as non-required

End forEnd for

8


DefinitionDefinition: A line : A line ll is said to be reachable from a stem is said to be reachable from a stem ss if the fault effect in stem if the fault effect in stem ss reaches line reaches line ll..

BuildRequirementListBuildRequirementList (( ff ))::• Assume the faulty line is Assume the faulty line is jj. .

• Adds Adds jj to to LL (fault activation). (fault activation).

• Trace Trace j j forwardforward until a fanout stem until a fanout stem ss is reached and add is reached and add all side inputs of traced path to all side inputs of traced path to LL..

• Mark reachable lines from Mark reachable lines from ss until an output is reached. until an output is reached.

• Trace backward from the reached output to the stem Trace backward from the reached output to the stem and add all side inputs of reachable lines to and add all side inputs of reachable lines to LL..

DefinitionDefinition: A line : A line ll is said to be reachable from a stem is said to be reachable from a stem ss if the fault effect in stem if the fault effect in stem ss reaches line reaches line ll..

BuildRequirementListBuildRequirementList (( ff ))::• Assume the faulty line is Assume the faulty line is jj. .

• Adds Adds jj to to LL (fault activation). (fault activation).

• Trace Trace j j forwardforward until a fanout stem until a fanout stem ss is reached and add is reached and add all side inputs of traced path to all side inputs of traced path to LL..

• Mark reachable lines from Mark reachable lines from ss until an output is reached. until an output is reached.

• Trace backward from the reached output to the stem Trace backward from the reached output to the stem and add all side inputs of reachable lines to and add all side inputs of reachable lines to LL..

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Justification of a line Justification of a line JJ , , justify(justify( JJ )):: Justification of a line Justification of a line JJ , , justify(justify( JJ ))::

CaseCase ActionAction

JJ is a NOT, XOR, XNOR is a NOT, XOR, XNOR Justify all inputs of Justify all inputs of JJ

JJ has a non-cont. value has a non-cont. value Justify all inputs of Justify all inputs of JJ

There is an There is an unreachableunreachable input input KK with cont. value with cont. value Justify Justify KK

OtherwiseOtherwise Justify all inputs of Justify all inputs of JJ

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Selection CriteriaSelection CriteriaSelection CriteriaSelection Criteria

Justification of a controlling value may involve some Justification of a controlling value may involve some selection.selection.

Cost functions are employed to minimize the number Cost functions are employed to minimize the number of specified inputs. of specified inputs.

Regular cost functions used in ATPG can b e used Regular cost functions used in ATPG can b e used • don’t take advantage of the fact that a stem can justify don’t take advantage of the fact that a stem can justify

several required values.several required values.

Fanout-based cost functions are proposed to take Fanout-based cost functions are proposed to take advantage of this fact. advantage of this fact.

Justification of a controlling value may involve some Justification of a controlling value may involve some selection.selection.

Cost functions are employed to minimize the number Cost functions are employed to minimize the number of specified inputs. of specified inputs.

Regular cost functions used in ATPG can b e used Regular cost functions used in ATPG can b e used • don’t take advantage of the fact that a stem can justify don’t take advantage of the fact that a stem can justify

several required values.several required values.

Fanout-based cost functions are proposed to take Fanout-based cost functions are proposed to take advantage of this fact. advantage of this fact.

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For an AND gate, fanout-based cost functions are For an AND gate, fanout-based cost functions are computed as follows:computed as follows:• Let Let ll be the output of AND gate with be the output of AND gate with ii inputs.inputs.

• Let Let F(l)F(l) denote the the fanout (i.e. the number of fanout denote the the fanout (i.e. the number of fanout branches) of line branches) of line l.l.

• 0-controllability of line l:0-controllability of line l:


For an AND gate, fanout-based cost functions are For an AND gate, fanout-based cost functions are computed as follows:computed as follows:• Let Let ll be the output of AND gate with be the output of AND gate with ii inputs.inputs.

• Let Let F(l)F(l) denote the the fanout (i.e. the number of fanout denote the the fanout (i.e. the number of fanout branches) of line branches) of line l.l.



)(

)(min 0

0 lF

iClC i

)(

)()(

1

1 lF

iClC i

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Selection Criteria - ExampleSelection Criteria - ExampleSelection Criteria - ExampleSelection Criteria - Example

G1

G4

G2

G3

G5

G6A

B

C

D

E

F

0

0

0

0 11

0

0

0

0

0

0

RCRC00(G4)=2(G4)=2

FCFC00(G4)=2(G4)=2

To detect fault To detect fault A s-a-0A s-a-0value G5=0 is value G5=0 is requiredrequired

RCRC00(G3)=2(G3)=2

FCFC00(G3)=1(G3)=1

RCRC00(C)=1(C)=1

FCFC00(C)=1/2(C)=1/2RCRC00(G1)=1(G1)=1

FCFC00(G1)=1/2(G1)=1/2

RCRC00(G2)=1(G2)=1

FCFC00(G2)=1/2(G2)=1/2

Based on regular cost functions, either Based on regular cost functions, either G3 or G4 could be selected, which mayG3 or G4 could be selected, which may result in two required values.result in two required values.

Based on fanout-based cost functions, Based on fanout-based cost functions, G3 will be selected, which results inG3 will be selected, which results inone required value C=0. one required value C=0.

To justify G5=0, either G3=0 or G4=0 To justify G5=0, either G3=0 or G4=0 could be selected. could be selected.

13


In general, fanout-based cost functions provide better In general, fanout-based cost functions provide better selection criteria than regular cost functions.selection criteria than regular cost functions.

There are situations where regular cost functions There are situations where regular cost functions provide better selection criteria.provide better selection criteria.

To take advantage of both, a weighted selection To take advantage of both, a weighted selection criteria is usedcriteria is used

In general, fanout-based cost functions provide better In general, fanout-based cost functions provide better selection criteria than regular cost functions.selection criteria than regular cost functions.

There are situations where regular cost functions There are situations where regular cost functions provide better selection criteria.provide better selection criteria.

To take advantage of both, a weighted selection To take advantage of both, a weighted selection criteria is usedcriteria is used

)( )( )(

)( )( )(

111

000

lFCBlRCAlC

lFCBlRCAlC

14

Experimental ResultsExperimental ResultsExperimental ResultsExperimental Results

ISCAS 85 and full-scan versions of ISCAS 89.ISCAS 85 and full-scan versions of ISCAS 89. SUN Ultra60, 450 MHZ, RAM=512 MB.SUN Ultra60, 450 MHZ, RAM=512 MB. Used test sets are highly compacted and are Used test sets are highly compacted and are

generated by MinTest generated by MinTest [Hamzaoglu et al., ICCAD 98].[Hamzaoglu et al., ICCAD 98].

Compare our results with a brute-force relaxation Compare our results with a brute-force relaxation method.method.

Effect of selection criteria on test relaxation.Effect of selection criteria on test relaxation. Impact of test relaxation on test data compression Impact of test relaxation on test data compression

based on FDR codes based on FDR codes [Chandra et al., VTS 2001].[Chandra et al., VTS 2001].

Impact of test relaxation on test compaction by vector Impact of test relaxation on test compaction by vector merging.merging.

ISCAS 85 and full-scan versions of ISCAS 89.ISCAS 85 and full-scan versions of ISCAS 89. SUN Ultra60, 450 MHZ, RAM=512 MB.SUN Ultra60, 450 MHZ, RAM=512 MB. Used test sets are highly compacted and are Used test sets are highly compacted and are

generated by MinTest generated by MinTest [Hamzaoglu et al., ICCAD 98].[Hamzaoglu et al., ICCAD 98].

Compare our results with a brute-force relaxation Compare our results with a brute-force relaxation method.method.

Effect of selection criteria on test relaxation.Effect of selection criteria on test relaxation. Impact of test relaxation on test data compression Impact of test relaxation on test data compression

based on FDR codes based on FDR codes [Chandra et al., VTS 2001].[Chandra et al., VTS 2001].

Impact of test relaxation on test compaction by vector Impact of test relaxation on test compaction by vector merging.merging.

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Percentage of XsPercentage of XsPercentage of XsPercentage of Xs

Average Xs = Average Xs = 68.3%68.3% ((brute-forcebrute-force).). Average Xs = Average Xs = 65.4%65.4% ((proposedproposed).). An average difference of only An average difference of only 2.9%2.9%..

16

Test Relaxation CPU TimeTest Relaxation CPU TimeTest Relaxation CPU TimeTest Relaxation CPU Time

Average CPU Time = Average CPU Time = 152725152725 Seconds Seconds ((brute-forcebrute-force).). Average CPU Time = Average CPU Time = 66 Seconds Seconds ((proposedproposed).).

17

Cost Function Effect on Extracted Cost Function Effect on Extracted Percentage of XsPercentage of XsCost Function Effect on Extracted Cost Function Effect on Extracted Percentage of XsPercentage of Xs

CircuitCircuit A=0 A=0 B=0B=0

A=1 A=1 B=0B=0

A=0 A=0 B=1B=1

A=1 A=1 B=1B=1

A=1 A=1 B=2B=2

A=1 A=1 B=6B=6

c5315c5315 48.52748.527 50.07650.076 52.06552.065 52.08052.080 52.08052.080 52.08052.080

c7552c7552 48.09148.091 48.32948.329 52.06852.068 52.07552.075 52.07552.075 52.07552.075

c2670c2670 65.89965.899 66.40766.407 68.37768.377 68.74868.748 68.74868.748 68.76768.767

s5378s5378 68.42268.422 69.89169.891 71.05771.057 70.48470.484 70.48470.484 70.75370.753

S9234.1S9234.1 63.62163.621 64.37264.372 65.94965.949 66.04666.046 66.04666.046 66.40866.408

S15850.S15850.11

77.69377.693 77.85577.855 78.97178.971 78.39178.391 78.44878.448 78.83078.830

S13207.S13207.11

92.45792.457 92.48592.485 92.92092.920 92.92092.920 92.92592.925 92.92892.928

S38584.S38584.11

75.32875.328 75.83975.839 78.07278.072 77.79477.794 77.79577.795 77.95177.951

s38417s38417 65.51865.518 65.86565.865 66.46766.467 66.16266.162 66.16466.164 66.17166.171

s35932s35932 22.98622.986 28.12028.120 27.41527.415 28.23828.238 28.23828.238 28.23828.238

AverageAverage 62.85462.854 63.92463.924 65.33665.336 65.29465.294 65.30065.300 65.42065.420

18

Impact of Test Relaxation on FDR Impact of Test Relaxation on FDR CompressionCompressionImpact of Test Relaxation on FDR Impact of Test Relaxation on FDR CompressionCompression

19

Impact of Test Relaxation on Impact of Test Relaxation on Compaction by Vector MergingCompaction by Vector MergingImpact of Test Relaxation on Impact of Test Relaxation on Compaction by Vector MergingCompaction by Vector Merging

20

ConclusionConclusionConclusionConclusion

A novel and efficient test relaxation technique has A novel and efficient test relaxation technique has been presented.been presented.

New selection cost functions proposed to maximize New selection cost functions proposed to maximize number of Xs.number of Xs.

While achieving slightly less test relaxation quality While achieving slightly less test relaxation quality than brute-force test relaxation, the technique is than brute-force test relaxation, the technique is faster by faster by several orders of magnitudeseveral orders of magnitude..

Demonstrated the impact of test relaxation in Demonstrated the impact of test relaxation in improving the effectiveness of test compaction and improving the effectiveness of test compaction and compression techniques.compression techniques.

A novel and efficient test relaxation technique has A novel and efficient test relaxation technique has been presented.been presented.

New selection cost functions proposed to maximize New selection cost functions proposed to maximize number of Xs.number of Xs.

While achieving slightly less test relaxation quality While achieving slightly less test relaxation quality than brute-force test relaxation, the technique is than brute-force test relaxation, the technique is faster by faster by several orders of magnitudeseveral orders of magnitude..

Demonstrated the impact of test relaxation in Demonstrated the impact of test relaxation in improving the effectiveness of test compaction and improving the effectiveness of test compaction and compression techniques.compression techniques.

aiman el-maleh, ali alsuwaiyan king fahd university of petroleum & minerals, dept. of computer...

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