Aligned Wafer LevelAligned Wafer LevelBondingBonding

Brian Brian DrewryDrewryENEE416ENEE416Fall 2009Fall 2009

What is What is Aligned Wafer Level Bonding?Aligned Wafer Level Bonding?

Aligned Wafer Level Bonding can be described as process thatAligned Wafer Level Bonding can be described as process thatallows stacking two or more processed wafers together involving,allows stacking two or more processed wafers together involving,““the application of intermediary layer, wafer alignment and bondingthe application of intermediary layer, wafer alignment and bonding””(Lindner, 1439).(Lindner, 1439).

Benefits of Aligned Wafer BondingBenefits of Aligned Wafer Bonding

The benefits of device stacking are:The benefits of device stacking are:““size reductionsize reductionincrease in increase in ““silicon efficiencysilicon efficiencyreduction in signal delayreduction in signal delayreduced parasiticreduced parasiticdecrease in power consumptiondecrease in power consumptionincrease in speedincrease in speedincrease in number of neighboring devicesincrease in number of neighboring devicesextension of bandwidthextension of bandwidth””

(Linder, 1439). (Linder, 1439).

Intermediate Layers for WaferIntermediate Layers for WaferBondingBonding

An intermediate layer is necessary when bonding two wafers or substratesin wafer level alignment.There are seven different types of intermediate layers, “available for 3-Dinterconnection technology and wafer level packaging:

Solder alloys: requires low temperature and low forceGold to gold wafer bonding: requiring high temperature and high forceCopper to copper wafer bonding: requiring high temperature and high forceAluminum to aluminum wafer bonding: requiring reduced atmosphere

(forming gas), high temperature and high forceAnodic bonding: requiring high temperature, high vacuum, high voltageSilicon direct bonding (SDB): requires ultra clean bonding environmentPolymer bonding: requiring low temperature, low force, high vacuum”

(Linder,1440).The various mechanical properties of the surface is vital to the viability ofthe process viscosity, thermal mismatch and fragility of the bondingelements should be considered.

Infrared Alignment:Infrared Alignment:One of the first methods used inOne of the first methods used inwafer alignment was Infraredwafer alignment was InfraredAlignment.Alignment.This method utilizes the infraredThis method utilizes the infraredlight for the alignment process.light for the alignment process.Silicon is, Silicon is, ““transparent in thetransparent in theinfrared spectrum, one can viewinfrared spectrum, one can viewand align both wafers to eachand align both wafers to eachotherother”” ( (MirzaMirza, 677), 677)The limitations of using infraredThe limitations of using infraredimaging is diffraction, imaging is diffraction, ““alignmentalignmenterrors of +/- 5umerrors of +/- 5um””Transparency of the wafers mayTransparency of the wafers maynot be entirely clear due tonot be entirely clear due tocomposition of the wafer,composition of the wafer,particularly metal components thatparticularly metal components thatdo not allow infrared light passdo not allow infrared light passthrough (through (MirzaMirza, 677)., 677).

Through Wafer Via HolesThrough Wafer Via HolesEtches an hole entirelyEtches an hole entirelythrough the first wafer tothrough the first wafer toview the second wafer forview the second wafer forthe alignment processthe alignment processshown in figure 3.shown in figure 3.This process This process ““requiresrequiresprecision registration ofprecision registration ofthe backside via holethe backside via holemask to the front side ofmask to the front side ofthe the waferwafer””(Mirza(Mirza, 677)., 677).This method is useful inThis method is useful inMEMS applicationsMEMS applicationswhere the thickness iswhere the thickness isseveral microns.several microns.

Wafer Backside AlignmentWafer Backside AlignmentUtilizes alignment keys on theUtilizes alignment keys on thebackside of the first wafer whichbackside of the first wafer whichare then aligned to the front sideare then aligned to the front sidealignment marks of the secondalignment marks of the secondwafer, shown in figure 4.wafer, shown in figure 4.This method is, This method is, ““a standard fora standard forMEMS wafer bonding.MEMS wafer bonding.Requires precision registrationRequires precision registrationprecision registration of theprecision registration of thebackside alignment keys to thebackside alignment keys to thefront side marks and exactfront side marks and exactalignment of the wafers.alignment of the wafers.The registration of alignment keysThe registration of alignment keysand the aligning of both wafers,and the aligning of both wafers,““each introduce errors of the ordereach introduce errors of the orderof 1 umof 1 um”” ( (MirzaMirza, 678)., 678).Is acceptable for MEMSIs acceptable for MEMSapplications in the order of two orapplications in the order of two ormore microns.more microns.

Figure 4: Wafer to wafer alignment using WaferBackside Alignment Keys.

Face to Face Alignment: UsingFace to Face Alignment: UsingSmartViewSmartView

Utilizes two microscopes forUtilizes two microscopes foralignment, one above and onealignment, one above and onebelow the wafer stack.below the wafer stack.The two microscopes, The two microscopes, ““systemsystemfocuses on a common axisfocuses on a common axiscalibrated for each alignment.calibrated for each alignment.Each microscope objectiveEach microscope objectiveobserves one alignment key onobserves one alignment key onthe surface of the waferthe surface of the wafer””Each microscope digitally storesEach microscope digitally storesthe alignment key of the farthestthe alignment key of the farthestwafer then aligns the waferswafer then aligns the wafersaccording to the digital alignmentaccording to the digital alignmentkeys (keys (DragoiDragoi, 426)., 426).Both wafer alignment stages,Both wafer alignment stages,““uses encoded stage motors thatuses encoded stage motors thatallow X,Y movements of 0.1allow X,Y movements of 0.1micronmicron”” ( (MirzaMirza, 679)., 679).

Face to Face Alignment: UsingFace to Face Alignment: UsingSmartViewSmartView

Both wafer alignment stages, Both wafer alignment stages, ““uses encoded stageuses encoded stagemotors that allow X,Y movements of 0.1 micronmotors that allow X,Y movements of 0.1 micron”” ( (MirzaMirza,,679).679).The face to face alignment method is able to, The face to face alignment method is able to, ““achieve 1achieve 1micron alignment precisionmicron alignment precision”” ( (DragoiDragoi, 425)., 425).This process also has an This process also has an ““repeatability of therepeatability of themeasurement system is less than 0.35 measurement system is less than 0.35 micronsmicrons””(Dragoi(Dragoi,,426).426).Smart View, can be a completely automated system or aSmart View, can be a completely automated system or asemi automated system.semi automated system.Face to face alignment is the most accurate alignmentFace to face alignment is the most accurate alignmentavailable and is completely viable in a commercialavailable and is completely viable in a commercialprocess.process.

Wafer BondingWafer BondingIntermediate bonding layers areIntermediate bonding layers areeither spun or sprayed on foreither spun or sprayed on foruniformity of the layers.uniformity of the layers.Sprayed bonding agents such asSprayed bonding agents such aspolymers, polymers, ““average uniformityaverage uniformityachieved was 7.5%achieved was 7.5%””(Lindner,(Lindner,1440).1440).The process of forming theThe process of forming theinterconnects and bonding theinterconnects and bonding thewafers is shown below in figure 6.wafers is shown below in figure 6.The usual thinning processThe usual thinning processprocedures are: procedures are: ““mechanicalmechanicalgrinding, lapping, reactive iongrinding, lapping, reactive ionetching (RIE), wet etching, ADP-etching (RIE), wet etching, ADP-DCE (Atmospheric Down StreamDCE (Atmospheric Down StreamPlasma Dry Chemical Etching)Plasma Dry Chemical Etching)””(Lindner,1441). After thinning both(Lindner,1441). After thinning boththe top and back side of thethe top and back side of theresulting wafer stacks.resulting wafer stacks.

ApplicationsApplications

Capping wafer with planar surfaceand multiple feed-trough and pictureof a MEMS device sample - Courtesyof VTI

ReferencesReferencesV. V. DragoiDragoi*, P. Lindner, M. *, P. Lindner, M. TischlerTischler, C. Schaefer , C. Schaefer ““New challenges for 300mm New challenges for 300mm SiSi technology:3D technology:3Dinterconnects at wafer scale by aligned wafer bondinginterconnects at wafer scale by aligned wafer bonding”” Materials Science in Semiconductor Materials Science in SemiconductorProcessing Volume 5, Issues 4-5, August-October 2002: 425-428 Processing Volume 5, Issues 4-5, August-October 2002: 425-428 ScienceDirectScienceDirect University ofUniversity ofMaryland College Park, Research Port. 24 Oct 2009Maryland College Park, Research Port. 24 Oct 2009http://www.sciencedirect.com.proxy-http://www.sciencedirect.com.proxy-um.researchport.umd.edu/science?_ob=um.researchport.umd.edu/science?_ob=MImg&_imagekeyMImg&_imagekey=B6VPK-47RJWJD-2-=B6VPK-47RJWJD-2-D&_cdi=6209&_user=961305&_orig=D&_cdi=6209&_user=961305&_orig=search&_coverDatesearch&_coverDate=10%2F31%2F2002&_sk=999949995&=10%2F31%2F2002&_sk=999949995&view=view=c&wchpc&wchp=dGLbVlz-=dGLbVlz-zSkWz&md5=947b4f4a80c238214a1a3390c01d2559&ie=/zSkWz&md5=947b4f4a80c238214a1a3390c01d2559&ie=/sdarticle.pdfttp://www.sciencedirect.cosdarticle.pdfttp://www.sciencedirect.com.proxyum.researchport.umd.edu/science?_obm.proxyum.researchport.umd.edu/science?_ob==MImg&_imagekeMImg&_imagekeLindner, Paul, Lindner, Paul, ““3D interconnect through aligned wafer level bonding3D interconnect through aligned wafer level bonding”” Electronic Components and Electronic Components andTechnology Conference, 2002. Technology Conference, 2002. ProceddingsProceddings 52nd 28-31 May 2002: 1439-1443 52nd 28-31 May 2002: 1439-1443 IEEE ExploreIEEE ExploreUniversity of Maryland College Park, Research Port. 24 Oct 2009 University of Maryland College Park, Research Port. 24 Oct 2009 http://ieeexplore.ieee.org.proxy-http://ieeexplore.ieee.org.proxy-um.researchport.umd.edu/stamp/stamp.jsp?tpum.researchport.umd.edu/stamp/stamp.jsp?tp=&=&arnumberarnumber=1008295&isnumber=21740=1008295&isnumber=21740 A.R A.R MirzaMirza, , ““One Micron Precision, Wafer-Level Aligned Bonding for Interconnect, MEMS andOne Micron Precision, Wafer-Level Aligned Bonding for Interconnect, MEMS andPackaging ApplicationsPackaging Applications”” Electronic Components and Technology Conference, 2002: 676-680 Electronic Components and Technology Conference, 2002: 676-680IEEE ExploreIEEE Explore University of Maryland College Park, Research Port. 24 Oct 2009 University of Maryland College Park, Research Port. 24 Oct 2009httphttp://ieeexplore.ieee.org.proxy-://ieeexplore.ieee.org.proxy-um.researchport.umd.edu/stamp/stamp.jsp?tpum.researchport.umd.edu/stamp/stamp.jsp?tp=&arnumber=853231&isnumber=18541=&arnumber=853231&isnumber=18541I-I-MirconewsMirconews –– ADVANCED PACKAGING:3D IC, WLP &TSV: 3DWLP OF ADVANCED PACKAGING:3D IC, WLP &TSV: 3DWLP OF MEMS:MarketMEMS:Market Drivers Drivers& technical Challenges & technical Challenges ““3D WLP of MEMS: Market Drivers & Technical Challenges3D WLP of MEMS: Market Drivers & Technical Challenges”” Donald DonaldRobert, Ken Robert, Ken GilleoGilleo, , HeikkiHeikki KuismaKuisma. 5 Feb 2009. . 5 Feb 2009. YoleYole Development. 26 Oct 2009 Development. 26 Oct 2009 http://www.i-http://www.i-micronews.com/analysis/3D-WLP-MEMS-Market-Drivers-Technical-Challenges,2710.htmlmicronews.com/analysis/3D-WLP-MEMS-Market-Drivers-Technical-Challenges,2710.html应应用于用于3D3D互互连连的的对对准晶准晶圆键圆键合技合技术术, James Lu, , James Lu, T.MatthiasT.Matthias, P Lindner EV Group, , P Lindner EV Group, SchSch. 1 Jan. 2006.. 1 Jan. 2006.Ronald Ronald GutmannGutmann Center for Integrated Electronics 24 Oct 2009 Center for Integrated Electronics 24 Oct 2009http://www.laogu.com/wz_26152.htmhttp://www.laogu.com/wz_26152.htm