(453906510) ecen 442 spring 2015 hw3(1)

HW3: Piccolo Interrupts

E C E N 4 4 2 , S p r i n g 2 0 1 5 , H o m e w ork 3 D u e : 0 2 / 1 8 / 2 0 1 5

Read Chapter 6 of System Control and Interrupts document of Piccolo and complete the following portions of a code to set interrupts from three sources: Timer, ADC, and QEP

(The sections that need to be completed are the ones preceded by highlighted comments; you need to replace ??? with one or more phrases/values to complete the code. You do not need to complete the parts followed by . The homework does not include the procedure of setting the interrupts within theperipherals, it only reviews the settings required at the PIE level and the CPU level.)

// Prototype statements for functions found within this file.interrupt void cpu_timer0_isr(void);interrupt void QEPISRCounterCompare(void) interrupt void ADCINT5isr(void);//More prototype statements?

???____

void main(){

// Clear all interrupts and initialize PIE vector table:// Disable CPU interrupts (globally)DINT;// Initialize the PIE control registers to their default state.// The default state is all PIE interrupts disabled and flags// are cleared.// This function is found in the DSP2803x_PieCtrl.c file.InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags: IER = 0x0000;IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt// Service Routines (ISR).InitPieVectTable();// Timer0, ADCINT5, EQEP1_INT Interrupts that are used in this example are// re-mapped to ISR functions found within this file:// notice the PieVecTable structure includes the names of the interrupts EALLOW;// This is needed to write to EALLOW protected register PieVectTable.TINT0 = &cpu_timer0_isr;PieVectTable.EQEP1_INT = &QEPISRCounterCompare(void);PieVectTable.ADCINT5 = &adc_isr;EDIS; // This is needed to disable write to EALLOW protected registers// Enable required interrupts:// Enable the PIE blockPieCtrlRegs.PIECTRL.bit.ENPIE = 1;// Enable the interrupts in the PIE level:// notice the PieCtrlRegs structure includes the order of the interrupts// within a group: INTx1 INTx2 INTx8PieCtrlRegs.PIEIER1.bit.INTx7 = 1; PieCtrlRegs.PIEIER10.bit.INTx5 =1;PieCtrlRegs.PIEIER5.bit.INTx1 = 1;//Enable the associated groups:IER |= M_INT1;IER |= M_INT10;IER |= M_INT5;

// Enable Global interrupt INTM EINT;// Enable Global realtime interrupt DBGMERTM;while(1) {}}//###########################################################################// Interrupt Service Routines//###########################################################################//The First ISR:interrupt void cpu_timer0_isr(void){// Acknowledge interrupt to PIE:PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;} //The Second ISR: interrupt void ADCINT5_ISR(void);{// Acknowledge interrupt to PIE:PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;}//The Third ISR:interrupt void QEP_ISRCounterCompare(void);{// Acknowledge interrupt to PIE:PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;}