7/13/2015 1 ee4271 vlsi design vlsi routing. 2 7/13/2015 routing problem routing to reduce the area
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04/19/23 1
EE4271 VLSI Design
VLSI Routing
204/19/23
Routing Problem
Routing to reduce the area
304/19/23
Metal layer 1
Via
Routing Anatomy
Topview
3Dview
Metal layer 2
Metal layer 3
Sym
bolic
Layou
t
©Bazargan
404/19/23
Routing Grid
504/19/23
Channel Routing Terminology
Upper boundaryUpper boundary
Lower boundaryLower boundary
TracksTracks
Terminals (Gate Pins)Terminals (Gate Pins)ViaVia
WidthWidth
604/19/23
Channel Routing Problem - I
• Input: – Two vectors of the same length to represent the pins on two
sides of the channel.– One horizontal layer and one vertical layer
• Output:– Connect pins of the same net together.– Minimize the channel width.– Minimize the number of vias.
704/19/23
Channel Routing Problem - II
00 11 22 22 00 33 00 44
11 22 00 33 33 44 44 00
Example: (01220304) (12033440)where 0 = no terminal
804/19/23
A Channel Routing Example
0 1 4 5 1 6 7 0 4 9 10 10
2 3 5 3 5 2 6 8 9 8 7 9
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The Other Example
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Lower Bound on Channel Width00 11 66 11 22 33 55
66 33 55 44 00 22 44
00 11 66 11 22 33 55
66 33 55 44 00 22 44
11 2233
55 4466
LocalLocaldensitydensity 11 33 44 44 44 44 22
Channel density =Channel density =Maximum local densityMaximum local density
Lower bound = 4Lower bound = 4
Lower bound on channel width = Channel density
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A More Complex Example
# columns =174, # nets=72, density =19
Routing result:number of tracks=20
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Realistic Design
From DAC Knowledge CenterDifferent colors refer to different wire densities.
Red color means congestion.
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