a depth-first-search controlled gridless incremental routing algorithm for vlsi circuits
DESCRIPTION
A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits. Hasan Arslan and Shantanu Dutt Electrical & Computer Eng. University of Illinois at Chicago ICCD 2004. Outline. Introduction Importance of Incremental Routing Previous work Our Goals - PowerPoint PPT PresentationTRANSCRIPT
A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits
Hasan Arslan and Shantanu Dutt
Electrical & Computer Eng.
University of Illinois at Chicago
ICCD 2004
Outline• Introduction
• Importance of Incremental Routing• Previous work• Our Goals
• A DFS-Based Incr. Routing Alg.• Non-Uniform Grids• DSR (Depth first search controlled Segment
bump and Refit) Algorithm
• Experimental Results
• Conclusion
Introduction
• In current VLSI Chip• The size gets smaller• High clock frequency• Interconnections on chip very important
• Technical Problems• Wire-congestion and routability• Crosstalk / noise• Power consumption• Terminal distribution
Incremental Routing
• After a chip layout is completed• Time/noise violation• One or more optimization metrics• Technology constraints
• Make changes to the circuit/system• Engineering Change Order (ECO) process
• Time to meet market requirements• Enormous resources and time already spent.
• Need a time-efficient & effective incremental routing algorithm
• Incremental Routing Problem• Set of existing routed nets R• Set of new nets S (due to timing violation, noise…)
• Quality metrics for an Incr. Routing• Near-optimal incr. solutions in a short amount of time
• Preserve previous routing results as much as possible
• Complete the required incremental routing in the available channel area if such a solution exists
Incremental Routing (Cont.)
Prior work on Incremental Routing
• 1) Emmert and Bhatia, “Incremental Routing in FPGA” , IEEE Int. ASIC Conference, 1998.
• 2) Cong and Sarrafzadeh, “Incremental Physical Design” , ISPD 2000.
• 3) Dutt, Shanmugavel and Trimberger, “Efficient Incremental Rerouting for Fault Reconfiguration in FPGAs”, ICCAD 1999.
• 4) Dutt, Verma and Arslan “A Search-Based Bump and Refit Approach to Incremental Routing for ECO Applications in FPGAs”, TODAES 2002
• 5) Xiang, Chao, Wong “An ECO Algorithm for Eliminating Crossalk Violations”, ISPD 2004
Emmert-Bhatia (ASIC’98)• Nets connected to faulty PLB, deleted and rerouted• A graph is built, from source pin to target pin• Standard single-net routing mode (global then detailed)• Do not perturb or move existing nets
• Single Net Routing : Route new nets without removing any existing nets.
• Rip & Reroute : If some nets cannot be routed, rip-up the existing nets which occupy the resources of new nets. Reroute the ripped up nets.
Cong-Sarrafzadeh (ISPD’00)
Dutt, Shanmugavel and Trimberger (ICCAD’99)
• Used incremental rerouting for dynamic fault reconfiguration in FPGAs
• Does not rip-up and reroute• Shift them (or their subnets) to other track positions ---
Bump-&-Refit (B&R)• No change in topology, length of existing nets• Optimal: Finds a detailed route if exists
Dutt, Verma and Arslan (TODAES’02)
• Extended basic B&R significantly for:– full incremental routing (global + detailed)– complex switchboxes– much better results than Std and R&R (routing succ
within avail res, HP of failed nets, speed under certain conditions)
Our Goals• Incremental routing for VLSI (ASIC) circuits• Gridless framework for non-uniform width & spacing req.
and memory & time efficiency• Address the quality metrics of incr. routing
– Near-optimal incr. solutions (min. WL and vias) in a short amt. of time
– Preserve previous routing results as much as possible
– Complete the required incremental routing in the available channel area if such a solution exists = min. # of metal layers
= max. routing success in given layers
• Approach: – Allow bumping of existing nets for near-optimal solns to new nets
– However, to obtain an overall good solution control the amount of perturbation of existing nets or their routing failures by retracting their bumpings using an overall DFS control
n1n2
n1
n2
Adjacent-via
DFS-Based Incr. Routing Alg. (Incr. Routing Concepts)
R-BBox
• If there is an edge between two nets in OG, they might bump each other during shifting one of them.
DFS-Based Incr. Routing Alg. (Incr. Routing Concepts)
For net ni in OG•higher degree (more adj. net in OG) might bump more nets, passing through in dense area •Check only adj. nets/blocks in OG to create non-uniform grid for ni
CG of n
n1
n2
n1.h1
n2.h1n
2.v 1
n1.
v 1 ob1
n1.v1 n1.h1
n2.v1 n2.h1
ob1
1
CG of n2
possibleoverlapping
All paths in Cp tested?
DFS-Based Incr. Routing Alg.
Generate grid line in R-BB
Soln?
Route-with-Bumping(ni)
For each bumped net nk Do-DFS-Routing(nk)
Soln?
Retract curr. bumping-causing
routing path
return(succ.)
Cp=Get-Candidate-Paths
return(succ.)
Do-DFS-Routing(ni) Route-with-Bumping(ni)
Route-without-Bumping(ni)
Soln?
return(fail)
NO
NO
NO
YES
YES
YES
return(fail)
Non-Uniform Grid Extraction
.D.
T
C en ter L in eW ire S p acin g
W ire W id th
W = 4W s = 4
K 1
K 2
K 3
D
T
.Zero W id th P athd w = w /2 + w s= 6
.
K 1
_
K 2
_
K 3
_
•Variable width/spacing rule
To route new net•Create obstruction zone around existing nets •Find zero width path for new net
Width / space req. of new net
s
t t
Non-Uniform Grid Extr. & Routing
s BGLs(Boundary Grid Lines)
OGLs(Occupied Grid Lines)
VGLs(Vacant Grid Lines)
t
• Use VGLs to get solution without bumping .• Use VGLs and OGLs to do B&R type routing (OGLs has higher cost than VGLs).
DFS-Based Incr. Routing Alg.
Generate grid line in R-BB
Soln?
Route-with-Bumping(ni)
For each bumped net nk Do-DFS-Routing(nk)
Soln?
Retract curr.bumping-causing
Routing path
return(succ.)
Cp=Get-Candidate-Paths
All paths in Cp tested?
return(succ.)
Do-DFS-Routing(ni) Route-with-Bumping(ni)
Route-without-Bumping(ni)
Soln?
return(fail)
NO
NO
NO
YES
YES
YES
return(fail)
YES
NO
Get-Next-Path(CP)
Finding Solution without Bumping – Use the 4-via Algorithm (Carothers,Lee,T-CS,1999)
n1n2
n3
n2
1-via routing
Adj-via
Adj-via n1
n1
2-via routing
Adj-via
Adj-via n1
n1
3-via routing
Adj-via
Adj-via n1
n1cv
cv
4-via routing
Adj-via
Adj-via
nj
Bumped seg.
If 1-via path cannot be found due to obstaclesIf 2-via path cannot be found due to obstaclesIf 3-via path cannot be found due to obstacles
DFS-Based Incr. Routing Alg.
For each bumped net nk Do-DFS-Routing(nk)
Soln?
Retract curr.bumping-causing
Routing path
All paths of Cp tested?
return(succ.)
Do-DFS-Routing(ni) Route-with-Bumping(ni)
NO
YES
return(fail)
YES
NO
Get-Next-Path(Cp)
Generate grid line in R-BB
solution
Route-with-Bumping(ni)
return(succ.)
Route-without-Bumping(ni)
Soln?
return(fail)
NO
NO
YES
YES
Cp=Get-Candidate-Paths
Selecting Paths to Route Bumped Seg.
Adj-via
Adj-via n1
n1
Random m paths
Adj-via
Adj-via n1
n1
Equal distance m paths
Adj-vian1
n1
The first m paths
The randomized initial path set selection gave the best solutions in terms of both quality and runtime.
Unr. Nets.
HP of F. nets
F. Net. Width Time(sec)
Seq. 3.56% 1647.6 3.69 32.65Rnd. 3.43% 1451.57 3.47 34.37Equ. 4.08% 1631.33 3.57 49.45
10% new net
DFS-Based Incr. Routing Alg.
For each bumped net nk Do-DFS-Routing(nk)
solution
Retract previous bumping-causing
routing
Have all path of CPtested
return(succ.)
Do-DFS-Routing(ni) Route-with-Bumping(ni)
NO
YES
return(failed)
YES
NO
Get-Next-Path(CP)
Generate grid line in R-BB
Soln?
Route-with-Bumping(ni)
return(succ.)
Route-without-Bumping(ni)
Soln?
return(failed)
NO
NO
YES
YES
Cp=Get-Candidate-Paths
DFS-Controlled Routing with Bump & Refit
n1
njn2
n3
n1..b-seg
n2..h2
n3..h1
n3. .v
1 nj
n1.b-seg
nj
n2..h1
Pi= i-via path is explored
n1..b-seg
n2.pinor
obs
P1
DFS-Controlled Routing with Bump & Refit
n1
njn2
n3
n2..h2
n3..h1
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
n2..h1
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
n1..b-seg
n2..h2
DFS-Controlled Routing with Bump & Refit
n1
njn2
n3
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
n2..h1
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
n1..b-seg
n2..h2
P1
obs P1
ancobs or
anc.n1 oranc.nj
P2-P4
n3..h1
n3. .v
1
n2..h2
DFS-Controlled Routing with Bump & Refit
n1
njn2
n3
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
n2..h1
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
n1..b-seg
P1
obs P1
ancobs or
anc.n1 oranc.nj
P2-P4
n3..h1
n3. .v
1
n3.h1
P2-P3
n2..h2
obs
P1
obs oranc.n1 or
anc.nj
P2-P4
DFS-Controlled Routing with Bump & Refit
n1
njn2
n3
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
n2..h1
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
n1..b-seg
P1
obs P1
ancobs or
anc.n1 oranc.nj
P2-P4
n3.h1
P2-P3
n2..h2
obs
P1
obs oranc.n1 or
anc.nj
P2-P4
n3..h1
n3. .v
1
n2..h2
DFS-Controlled Routing with Bump & Refit
n1
njn2
n3
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
n1..b-seg
P1
obs P1
ancobs or
anc.n1 oranc.nj
P2-P4
n3.h1
P2-P3
obs
P1
obs oranc.n1 or
anc.nj
P2-P4
n3..h1
n3. .v
1
n2..h2
n2.h1
P2
n2..h1
obs
P1
n1..b-seg
DFS-Controlled Routing with Bump & Refit
n1
njn2
n3
n3. .v
1 nj
n1.b-seg
n2.pinor
obs
P1
nj
Pi= i-via path is explored
n2.h2
P2
n3.v1
P1
P1
obs P1
ancobs or
anc.n1 oranc.nj
P2-P4
n3.h1
P2-P3
obs
P1
obs oranc.n1 or
an.nj
P2-P4
n3..h1
n3. .v
1
n2..h2
n2.h1
P2
obs
P1
VGL
P2
Characteristics of Benchmark Circuits
10% 20% 10% 20% 10% 20%Circuit New N. New N. Circuit New N. New N. Circuit New N. New N.net-97 10 19 net-282 28 56 net-797 79 159net-102 10 20 net-391 39 78 net-829 82 164net-103 10 20 net-413 41 82 net-961 96 192net-115 11 23 net-557 55 111 net-968 82 165net-247 24 49 net-700 70 140
46.36 93.21Average number of new nets
– Width of net 2 -15 unit– Space req. btw. nets 1 - 8 unit– Base 2x2 tile of Mcc1 benchmark is replicated with diff. cell sizes and
diff. # of pins– Nets connected to pins randomly generated routed by using max 4-via
routing– Experiment involved routing as many nets as possible under the
constraint of 2 metal layers only routing succ. rate = efficacy of router
Experimental ResultsComparison of Runtimes (sec.)
3.09
34.37
45.51
4.19
12.0815.61
0.05.0
10.015.020.025.030.035.040.045.050.0
10% New Net 20% New Net
Ru
nti
me
(s
ec
.)
Std
R&R
DSR
Comparison of Avr. Unrouted Nets (Base-DSR)
10.8
8.5
4.6
2.4
0.0
2.0
4.0
6.0
8.0
10.0
12.0
10% New Net 20% New NetFai
lure
fac
tor
wit
h r
esp
ect
to D
SR
Std
R&R
Comp. of modified existing nets for each new net
0.00 0.00
2.59
1.511.25
2.04
0.00
0.50
1.00
1.50
2.00
2.50
3.00
10% New Net 20% New NetAvr
. # o
f mod
ified
net
Std R&R DSR
# of Rerouting Exiting Nets Tried for Each New Net (Search Space)
0.00
5.603.24
21.98
14.75
0.000.00
5.00
10.00
15.00
20.00
25.00
10% New Net 20% New Net
# o
f R
ero
ute
d N
ets
Std
R&R
DSR
Experimental Results(Comparison of Failed Nets)
• Unrouted nets are longer and wider when Std. and R&R used• DSR gets more compact layout by routing more and wider nets
Comparison of Total HP of Failed Nets
36.75
6.595.112.15
0.005.00
10.0015.0020.0025.0030.0035.0040.00
10% New Net 20% New NetTo
tal H
P f
acto
r w
ith
res
pec
t to
DS
R
Std R&R
Comparison of Width of Failed Nets
2.06
1.521.601.29
0.00
0.50
1.00
1.50
2.00
2.50
10% New Net 20% New Net
Wid
th f
acto
r w
ith
res
pec
t to
DS
R
Std R&R
Experimental Results(Comparison of Modified Nets)
Comp. of modified existing nets for each new net
0.00 0.00
2.59
1.511.25
2.04
0.00
0.50
1.00
1.50
2.00
2.50
3.00
10% New Net 20% New NetAvr
. # o
f mod
ified
net
Std R&R DSR
Comp. of via incr. of modified nets
0.00% 0.00%
116.68%
88.32%
30.25% 23.17%
0.00%20.00%
40.00%60.00%
80.00%100.00%
120.00%140.00%
10% New Net 20% New NetV
ia in
cre
me
nt
(%)
Std R&R DSR
Comparison of Total HP of Failed Nets
60.62
42.96
9.153.23
0.00
10.00
20.00
30.00
40.00
50.00
60.00
70.00
10% New Net 20% New NetTo
tal H
P f
acto
r w
ith
res
pec
t to
DS
R
Std R&R
Comparison of Width of Failed Nets
3.282.94
2.23
1.75
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
10% New Net 20% New Net
Wid
th f
acto
r w
ith
res
pec
t to
DS
RStd R&R
Experimental Results(Global Nets)
Experimental Results(Global Nets)
Comp. of modified existing nets for each new net
0.00 0.00
2.21
1.281.18 1.14
0.00
0.50
1.00
1.50
2.00
2.50
10% New Net 20% New Net
Av
r. #
of
mo
dif
ied
ne
t
Std R&R DSR
Comp. of via incr. of modified nets
0.00% 0.00%
93.25% 97.42%
35.76%
17.21%
0.00%
20.00%
40.00%
60.00%
80.00%
100.00%
120.00%
10% New Net 20% New Net
Via
inc
rem
en
t (%
)
Std R&R DSR
# of Rerouting Existing Nets Tried for Each New Net Routing (Search Space)
0.00
5.202.98
19.52
11.99
0.000.00
5.00
10.00
15.00
20.00
25.00
10% New Net 20% New Net
# o
f R
ero
ute
d N
ets
Std
R&R
DSR
Conclusions• New Incremental Routing Algorithm DSR
– gridless routing– variable width/space
• Produces significant impr. over Std. R&R– Via incr. of modified nets (3 (5) times less than R&R, 10% and 20%, respectively)– Higher routing success rate (Std.=10.8 (8.5) R&R= 4.6 (2.4) times worse)– Wire length (HPBB) of failed nets: Std. = 36.7 (6.59) R&R = 5.1 (2.15) times worse)– Degree of modification (~20% less modification than R&R)
• Future Work– Tile-based approach to avoid congestion– Timing-driven DSR algorithm
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