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8/10/2019 A Novel Control Scheme of a Parallel
1/8
IEEE
TRANSACTIONS
ON
INDUSTRY
APPLICATIONS,
VOL. 28, NO.
5, SEPTEMBER/ OCTOBER 1992
1023
A Novel Control Scheme of a Parallel
Current-Controlled PWM Inverter
Satoshi Ogasawara, Member,
IEEE,
Jin Takagaki, Hirofumi Magi, Member,
IEEE,
and Akira Nabae, Fellow, IEEE
Abstract-A
novel parallel technique for current-controlled
PWM inverters is described. Two voltage source inverters, the
output terminals
of
which are connected in parallel through
current balancers, are used as a main circuit. In this scheme,
excellent characteristics both in steady states and in transient
states are obtained, keeping the average values of the cross
current and zero sequence current at zero level. This current
control scheme is applicable to large-capacity
GTO
inverters
because good performance is attained even
if
the switching
frequency is only a few hundred Hertz, as shown in the experi-
mental results.
I. INTRODUC~ON
URRENT-CONTROLLED PWM inverters play the
m
st important role in a high-performance ac servo
system and a reactive power compensating system. Con-
ventional current controllers utilizing a voltage source
inverter can be classified as follows:
Direct type-The switching pattern is directly deter-
mined from the current deviation vector. The hystere-
sis-type current controllers [SI, [lo], [121, [131, the
predictive current controllers
[9],
[13], [141, and the
current controller previously proposed by the authors
[l l] are included.
Indirect type [12]-[22]-The average voltage reference
vector during a very small interval of time is deter-
mined to force the actual current to follow its refer-
ence. The switching pattern and sequence are deter-
mined by the voltage reference vector. The ramp
comparison current controllers and the minimal time
control of the current vector [12]-[14] are included.
In the direct-type current controller, there is basically
no
phase lag, but the switching frequency is not constant. On
the other hand, in the indirect-type current controller, the
switching frequency is constant, but some phase lag arises.
Some papers on phase lag compensation based on feed-
back and feedforward control have already been pub-
lished [151-[211.
The characteristics required from the current-con-
trolled PWM inverter are a quick current response in
Paper IPCSD 91-126, approved by the Industrial Drives Committee of
the IEEE Industry Applications Society for presentation at the 1987
Industry Applications Society Annual Meeting, Atlanta,
GA,
October
18-23. Manuscript released for publication September 1, 1991.
The authors are with the Department
of
Electrical Engineering,
Nagaoka University of Technology, Nagaoka, Niigata, Japan.
IEEE Log Number 9108231.
transient states and a low harmonic current content in
steady states. However, these two requirements contradict
each other, that is, the switching mode that yields a high
current derivative must be chosen to pioduce the quick
current response, whereas the switching mode that yields
a low current derivative must be chosen
13
suppress the
current harmonic content.
To
solve the problem, the
authors already proposed a novel current control scheme
of a single-bridge voltage source inverter, in which the
switching mode that yields a low current derivative is
changed to the switching mode that yields a high current
derivative when a large current deviation appears [l l] .
Nowadays, attention is paid to the parallel technique
for current-controlled PWM inverters that may meet the
required properties (i.e., large output power, low har-
monic current content, and/or low switching frequency).
In this paper, a novel current control scheme of parallel
current-controlled PWM inverters is discussed.
This
cur-
rent controller pertains to the direct type above men-
tioned. Two bridge inverters, the output terminals of
which are connected in parallel through the current bal-
ancers, are used as the main circuit. The harmonic cur-
rent content and switching frequency are reduced consid-
erably because a different switching pattern is given to
each inverter. In general, a cross current and a zero
sequence current, however, flow between the two invert-
ers. This proposed scheme makes it possible to keep the
average values of these currents at zero level all the time,
thus giving excellent characteristics both in steady and in
transient states.
11.PRINCIPLE OF CONTROL
STRATEGY
Fig. 1 shows an equivalent load circuit of a voltage
source inverter. The voltage-current vector equation is
expressed as follows:
di
dt
U = L- + Ri + e ,
where the inverter output voltage vector
U,
he current
vector i and the inner induced voltage vector e , are givexi
bY
U
=
[VdVqIT
=
C[VaVbV, IT ,
i = [ id iq lT
=
c[ ia ib iClT,
0093-9994/92 03.00 1992 IEEE
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1024
IEEE TRANSACTIONS ON INDUSTR Y APPLICATIONS,
VOL.
28, NO. 5, SEPTEMBER/ OCTOBER
1992
be chosen to attain quick current response, whereas the
voltage vector that yields a low
d A i / d t
should be chosen
to reduce the switching frequency. In the following sec-
tions, the way to choose the voltage vector and switching
pattern is described.
111.
ANALYSIS
F PARALLEL
NVERTERS
Fig.
2
shows the main circuit of the parallel current-
controlled PWM inverter described in this paper. Two
voltage source inverters are connected in parallel through
the current balancers. The inverter output voltage vector
U and the inverter output current vector i are expressed
Fig. 1. Load of a voltage source inverter.
The current deviation vector
Ai
is defined as
Ai
=
i*
2)
where
i*
is the current reference vector. Substituting 2)
into (1) produces as follows:
1
2
=
- U1
+
u 2 )
( 6 )
(7)
= i , + i ,
A i
dt
L - + R A i = L - + R i * + e ,
Generally,
R A i
can be neglected compared with
where
L d A i / d t .
Expressing the parentheses on the right hand
of
(3)
as
e
gives the following equations
U1 = c [ u a l u b l u c l l r =
E C I S a l S b l S c l I T ,
d Ai
dt
L - = e - U
(4)
di *
dt
e
=
L -
+
Ri*
+
e ,
( 5 )
where
e
means a load counter EMF vector at the inverter
output terminals under the condition that the current
vectar
i
ideally equals the reference
i * ,
that is,
e
is the
voltage vector that lets the load carry the current
i*
without any current deviation. In other words, if the
voltage source inverter can always output the same volt-
age as
e ,
no current deviation vector
Ai
appears. How-
ever, the inverter can output only one voltage vector out
of the discrete set of voltage vectors corresponding to the
switching patterns. The instantaneous value of the current
deviation cannot be made zero all the time.
Therefore, a tolerance of the deviation vector is set up.
If the deviation vector
Ai
is in the permissible region, the
actual current vector
i
is judged to follow the reference
vector
i * ;
therefore, the output voltage vector is not
altered. If
Ai
is outside the permissible region,
i
is judged
not to follow
i * ;
therefore, another voltage vector that
can make the deviation vector
Ai
smaller is chosen. Note
that the
d A i / d t
of the output voltage vector has a
direction component opposite that of
Ai .
By repeating the
above-mentioned process, the current deviation vector
Ai
is kept within the permissible region at all times.
Equation
4)
hows that the derivative of the deviation
vector
d A i / d t
is determined by the choice of an inverter
output voltage vector U out of the discrete set of voltage
vectors. If a voltage vector is chosen
so
that the deviation
derivative is large and egative, the current deviation
vector
Ai
would rapidly become smaller but then would
exceed the permissible region again.
If
a voltage vector is
chosen
so
that the deviation derivative is small and nega-
tive,
Ai
would decrease more slowly, and the time until i
exceeds the permissible region would be longer. There-
fore, the voltage vector that yields a high
d A i / d t
should
u 2 = C [ u aZ u b2u c21T = E C [ S a Z S b 2 S c 2 1 T ~
i , = C [ i a l i b l i C l l T ,
i 2
=
c [ i a Z i b 2 i c 2 l T .
In Fig.
2,
one or zero of switching functions
sal,sbl, scI,
s a 2 , b 2 , c 2
corresponds to the mode in which the upper-
side device or the lower side device is on state, respec-
tively. The parallel voltage source inverter can produce 19
different voltage vectors that have a number
k
from
0
to
18
as shown in Fig. 3. Table I shows the relationships
between the switching pattern and the number of the
output voltage vector
k .
Hereinafter, the inverter output
voltage vector will be expressed as d k ) . Compared with a
single bridge inverter, the number of output voltage vec-
tors increases from
7
to 19. This means that the harmonic
current content and the switching frequency can be re-
duced considerably.
Note that a cross current flows between the two invert-
ers through the current balancers because the different
switching patterns are given to each inverter. The
voltage-current vector equation of the cross current cir-
cuit is expressed as follows:
d
dt
u 1
uz =
l - ( i l 2 )
where 1 is an inductance of a current balancer measured
between the output terminals of the two inverters. Table
I1 shows the relationships between the switching pattern
and the cross current vector
i , , .
In this table, a plus
or
minus sign indicates increasing or decreasing, and the
last letter (a,
6, c ,
x, ,
z )
shows the axis and the direction
in which the cross current vector is increasing or decreas-
ing. Here, the
x,
y ,
and
z
axes are defined as in Fig.
4.
For example, +a means that the cross current vector
*
is increasing to the a-axis direction by
i ;/IIA/sl, and a y means that i , is de-
creasing in the
y-axis
direction by
f i E / l [ A / s l .
If the dc input terminals of the two inverters are
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l b l
ubl
E ,
Fig. 2. Parallel voltage source inverter (dual voltage sources).
Fig. 3. Output voltage vectors
of
the parallel inverter.
TABLE I
RELATIONSHIPSETWEENWITCHINGATTERNND
K
s a 2
sb2
s c 2 )
s,lsbls,I)
000
100 110
010
011 001
101
111
000 0 13
14
15 16
17 18 0
100 13
1
7 14
0
18 12 13
110 14 7
2 8
15
0
13 14
010
15 14
8 3
9 16
0
15
011 16 0 15
9
4
10 17 16
001 17
18
0 16
10
5
11 17
101 18 12
13
0
17
11 6 18
111
0
13 14 15
16
17
18
0
TABLE
I1
RELATIONSHIPSETWEENWITCHINGAT T E RNND CRO SS
CURRENTECTOR
s.2
S b 2 SCZ)
s,Isbls,l) 000 100 110 010 011 001 101 111
000 0
100
+a
110
- c
010
b
011 -a
001
+ c
101 - b
111 0
-a
0
+ b
-2a
+ 6 Y
X
+C
-a
+C
- b
0
-a
i x
+ i z
c
+C
-b
Y
+a
0
+C
- 2 b
- b
+ fTz
+a
+
2a
+
i x
--c
0
- b
+a
Y
-C
+
X
2
c
+ b
0
+a
--c
+ b
--c
2
i
+ 2 b
-a
0
+ b
0
+a
C
f b
-a
+C
- b
0
Y
Fig. 4. Definition
of
axes.
connected in parallel and the two inverters are fed by a
single voltage source as shown in Fig.
5 ,
the zero sequence
current, in addition to the cross current, flows through the
current balancers. The voltage-current equation of the
zero sequence circuit is expressed as follows:
d
U01 U02 = y o 1 o ,
(9)
where
=
u c l / f i
= b l
c l ) / f i ?
b 2 c Z ) / a ,
02 =
.a2 ub2 u c 2 ) / f i
=
io, = id
+ i,,
+
ic1 /G,
io, = i a , + i b 2 + icz>/a
Table I11 shows the relationships between the switching
pattern and the zero sequence current
io, o,.
In this
table, a plus or minus sign indicates increasing or decreas-
ing. For example,
+ 2
means that the zero sequence
current
io, o,
is increasing by
2 E / ( f i I ) [ A / s ] .
The cross current and the zero sequence current should
be controlled to zero. The instantaneous values of these
currents cannot be made zero all the time. Therefore, two
tolerances are set up for the cross current vector and zero
sequence current
so
that these currents are controlled
within the tolerances in the same way that as is the
current deviation vector, that is, the average values of
these currents can be controlled to zero.
This control scheme is suitable for large-capacity vari-
able frequency supplies in which more than two bridges
are required. In a conventional parallel-connected in-
verter in which similar switching patterns is given to each
inverter, neither cross current nor zero sequence current
flows, theoretically. However, the parallel inverter needs
three current balancers because the output current bal-
ance between two inverters is affected by a difference in
switching time and forward voltage drop
[25] .
Two isolated
dc power supplies as shown in Fig.
2
are required. Assum-
ing that diode rectifiers are used as the dc power supplies,
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I
IEEE
TRANSACTIONS ON
INDUSTRY APPLICATIONS,
VOL. 28, NO. 5 ,
SEPTEMBER
/
OCTOBER
1992
Inv.1
Fig. 5. Case
of
single voltage source.
TABLE
111
RELATIONSHIPSETWEENWITCHINGAITERNAND ZERO EQUENCE
CURRENT
s s s )
( S , , S h , S , , )
000
100 110 ol b 2 i? 1 001 101 111
000 0
-1 - 2
-1
- 2 -1 - 2 -3
100
+1 0 -1
0 -1 0 - 1
- 2
1 3 + 2 + 1 0 + 1 0
+1
0 -1
010 +1
0 -1
0
-1 0
-1
- 2
011
+ 2
+1
0
+ 1 0 f l
0 -1
001
+1
0
-1 0 1 0 -1 - 2
101 + 2 + 1
0
+ 1
0 + 1
0 -1
111 + 3 + 2 + l + 2
+ 1 + 2
+ 1
0
the fifth and seventh ac-side harmonic currents are elimi-
nated by using multiphase transformers.
HARMONICURRENT
Iv. SELECTION OF
A
SWITCHING
MODETO
SUPPRESS
A.
Selection of a Voltage Vector v ( k )
To suppress the harmonic current and to reduce the
switching frequency, a voltage vector u k ) is chosen to
give small d A i / d t as expressed in Section 11. Therefore,
the voltage vector is one of three vertices of the triangle
including
e ,
as shown in Fig. 6(a). A relationship between
the voltage vector and the current deviation vector is
expressed as the following equation:
d Ai
dt
-
= e
u k ) . (10)
In Fig. 6(a),
u k , )
can increase
A i
to the y-axis direc-
tion, whereas
u ( k J
and
u ( k , )
can increase A i to the
z
and
x
axis directions, respectively.
To
construct the A i
detection circuit simply, the A i plane is divided into four
regions as shown in Fig. 6(b). If the deviation vector A i is
in the hexagon, i is judged to follow i * ; therefore,
u ( k )
s
not altered. If A i is in region
0
he voltage vector
u(k , ) should be chosen. If A i is in region
@
or
0
u(k,)
or u k, ) should be chosen, respectively.
Similarly, if
e
is in the triangle shown in Fig. 7(a), and
A i is in region
@, 0
r
@
as shown in Fig. 7(b),
u k,), u(k,),
or
u(k,)
should be chosen, respectively. If
A i is in the hexagon shown in Fig. 7(b),
u ( k )
is not
altered.
If e is in the triangle shown in Fig. 6(a) or Fig. 7(a), the
current deviation vector A i is always controlled into the
hexagon by the above-mentioned method. If
e is
outside
of the hexagon, A i cannot be controlled any longer.
Therefore, this control scheme is applicable to the load of
which e is within the largest hexagon shown in Fig.
3.
The
d
i
ii)
Fig. 6.
Selection
of
voltage vector
( k l , , , k 3 ) : (a)
Voltage plane;
(b)
deviation current plane.
d
f
Fig. 7. Selection
of
voltage vector ( k 4 ,
,,
k 6 ) : a) Voltage phase;
(b)
deviation current plane.
line-to-line
rms
value of the maximum sinusoidal inverter
output voltage is
E / fi.
owever, there exists a tradeoff
between the drive s bus utilization capability and the
current controllability in transient states because the cur-
rent controllability is determined by the difference be-
tween e and
u k)
as expressed
by
10).
B.
Selection of a Switching Pattem
The procedure explained in Section
IV-A
can deter-
mine a voltage vector out of the 19 vectors, but a switch-
ing pattern cannot be determined because the switching
pattern that outputs the voltage vector is not unique.
Utilizing the degree of freedom, the cross current vec-
tor i , , and the zero sequence current i o , o , are
controlled. The cross current plane is divided into seven
regions as shown in Fig.
8,
and the zero sequence current
is detected by a window comparator. When the cross
current vector is within the hexagon, the cross current is
judged to not flow. In addition, when the zero sequence
current is within the window, the zero sequence current is
judged not to flow. According to the following conditions,
a switching pattern is chosen:
1)
The voltage vector selected from Section IV-A is
2)
The cross-current vector is reduced.
3)
The zero sequence current is reduced.
4) The number of switching times is minimal.
5 ) The switching frequencies of the two inverters are
Here, the conditions are in order of priority. In the case
output.
balanced.
T
~
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INVERTER
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d
t
Fig. 8. Cross-current plane.
of dual voltage sources, condition 3) is excluded because
the zero sequence current will not exist. If the cross-curent
vector is in the hexagon shown in Fig.
8,
condition 2) is
excluded. If the zero sequence current is in the window,
condition
3)
is excluded. The inverter output current
vector
i ,
the cross current vector
i , , ,
and the zero
sequence current io o are controlled by selection of
the switching pattern.
C.
Detection
of
the Region to which e Belongs
It is possible to keep
Ai
within the hexagon of Fig. 6(b)
and Fig. 7(b) by the procedure shown in Section IV-A.
However, to determine the output voltage vector, it is
necessary to detect to which triangular region
e
belongs.
A relationship between the voltage vector u k) nd the
current deviation vector
Ai
is expressed by 10).
d Ai
d t
L -
= e u k).
10)
Therefore, the triangular region to which e belongs is
detected as follows.
if
the x-axis component of
d A i / d t
is
positive, it indicates that e is in the upper half plane to
the b-axis shown in Fig. 9. If the y-axis component of
d A i / d t
is positive,
e
is in the lower half plane to the
c
axis. If the z-axis component of
d A i / d t
is positive, e is in
the left half plane to the
a
axis. Therefore, a triangular
region is determined by
u(k)
and the
x , y , z
axes compo-
nents of
d A i / d t
as shown in Table IV because the
voltage vector expressed in Section IV-A is always se-
lected.
v. SWITCHOVER TO QUICK
CURRENT
RESPONSE
CONTROL
CHEME
If Ai
becomes larger in transient states, it
is
necessary
to switch over to the quick response current control
system. A voltage vector is chosen in which the d A i / d t
has the largest opposite direction component to A i , as
mentioned in Section 11. Therefore, the voltage vector is
same as that of the hysteresis-type current controller.
Another tolerance of
Ai
whose width is larger than that
of the former tolerance shown in Fig. 6(b) and Fig. 7(b) is
set up. Although the current deviation vector
Ai
exceeds
the tolerance, the voltage vector selected by the quick
current response current control system is output.
Fig. 9. Detection of e.
TABLE IV
DETECTION
F e
VI. SYSTEM
ON~GURATION
Fig. 10 shows the current controller to suppress the
harmonic current. As mentioned in Section IV-A, the
voltage vector u k) is selected according to the current
deviation vector
Ai
and to where triangular region e
belongs. Where triangular region e belongs is determined
from the derivative of the current deviation vector
d A i / d t
and the voltage vector
d k ,
as mentioned in Section
IV-C. The switching pattern of the two inverters is se-
lected from the cross-current vector
i , , ,
the zero
sequence current
io , o, ,
the difference between the
switching frequencies of the two inverters f, ,, and the
present switching pattern, as shown in Section IV-B. In
case of dual voltage sources, it is unnecessary to input the
zero sequence current
iol o,.
The switching pattern
selected by this current controller has a low derivative of
the deviation vector
d A i / d t ,
and the average values of
the cross current and zero sequence current are con-
trolled to zero. In this controller, about
64kB ROMs
and
22 comparators are used.
Fig.
11
shows the system configuration of the proposed
current controller. The upper block is the low harmonic
current controller shown in Fig. 10.As shown in Section
V, a conventional hysteresis-type current controller is
used as the quick current response current control system.
The amplitude of the deviation vector is checked by the
amplitude comparator. If
Ai
becomes large in transient
states, the switching pattern is switched over from that of
the low harmonic current controller to that of the quick
response current controller. Therefore, the same quick
T
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il
2 201 02
f l
2
Detection
(Sec. 4.3)
of e
Ai
region of
e
Fig.
10.
Current controller to suppress harmonic current.
Curren t Controller
I to Suppress
~i
Ti
XIIIO& C u r r en t ,
~
to dr ive
circuit
Fig.10)
Conventional
Fig.
11.
System configuration of proposed curren t controller.
Servo
speed
Fig.
12.
Configuration of experimental system.
current response as the hysteresis-type current controller
is obtained in transient states. In this case, it is not
necessary to control the cross-current vector and the zero
sequence current because the switching patterns of the
two
inverters are same, and these currents do not change,
as shown in Tables I1 and 111. The delay time of the
control circuit is about
2
ps.
Fig. 12 shows the experimental
1.5-kW
permanent mag-
net synchronous motor servo system. 1nv.l and Inv.2 are
both single-bridge voltage source inverters each having
six
switching devices, respectively. The output terminals are
connected through the current balancers
1
The current
controller can be operated as one of four controllers, i.e.,
a hysteresis-type current controller, the previously pro-
posed current controller for a single bridge, and the
parallel current controller proposed here with either dual
voltage sources or a single voltage source. The motor
ratings are given in Table V.
PY f, ,=lkHz
f,,=ZOOHz
(c)
Fig. 13. Experimental waveforms in steady states: (a) Hysteresis-type
current controller; (b) single-bridge current controller; (c) parallel cur-
rent controller.
l ms
Fig.
14.
Waveform of line-to-line output voltage.
TABLE V
RATINGOF
PERMANENT
AGNET YNCHRONOUSOTOR
Rated output 1.5 kW
Rated speed
1200
r/min
Rated current
Armature resistance 0.75 t2
Armature inductance 5.8 mH
Armature linkage fluxdue to
permanent magnet 0.35 Wb
Moment of inertia
12.6 A
(crest value)
Number
of
poles
4
50.1 kg .cmz
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NOVEL CONTROL SCHEME OF
A
PWM INVERTER
1029
VII. EXPERIMENTALESULTS
f s w
=
1.5kH
z
A.
Steady States
Fig. 13 shows the experimental waveforms in steady
states. Here, Fig. 13(a) is a waveform of the hysteresis-type
current controller, (b) is that of a single-bridge current
controller, and (c) is that of the parallel current controller
with dual voltage sources. The average switching frequen-
cies of the switching devices in the three waveforms are
1
kHz, 600 Hz nd 200 Hz espectively. Comparing the
hysteresis-type current controller with the parallel current
controller, the average switching frequency of (c) is one
fifth of (a), whereas the magnitude of current ripple of (c)
is smaller than that of (a). Comparing the single-bridge
current controller with the parallel current controller, the
average switching frequency of (c) is one third of (b),
giving the same width of the current ripples.
Fig. 14 shows a waveform of the line-to-line output
voltage in case of the here-proposed parallel current
controller. It is shown that the parallel current-controlled
PWM inverter outputs half of the dc link voltage. From
this waveform, it is easily understood that the switching
frequency or the harmonic current content is reduced
considerably.
B. Transient States
Fig. 15 shows some transient characteristics of the
hysteresis-type current controller, the single-bridge cur-
rent controller, and the parallel current controller with
both dual and single voltage sources. The average switch-
ing frequencies are 1.9
kHz,
1.5
kHz,
420 Hz, and
840
Hz,
respectively. The same quick current responses are ob-
tained. The average values of the cross current and zero
sequence current are regulated to zero.
VIII. CONCLUSION
The authors have proposed a novel current control
scheme for a parallel current-controlled PWM inverter.
The proposed current control scheme was applied to a
1.5-kW PM motor servo system. It was verified experimen-
tally that the switching frequency of the switching devices
and the harmonic current content were reduced consider-
ably in steady states, and the same quick response as the
hysteresis-type current controller was obtained in tran-
sient states. The average switching frequency using dual
voltage sources was one half of that when using a single
voltage source. Therefore, dual voltage sources should be
used to attain high performance.
The features of the proposed control scheme are sum-
marized as follows: 1 The switching frequency and har-
monic current content are reduced considerably. 2 High-
speed current response is attained in transient states. 3)
The average values of the cross current and zero sequence
current are regulated to zero. 4 The control scheme is
(C) 4
Fig. 15. Transient responses: (a) Hysteresis-type current controller; (b)
single-bridge current controller; (c) parallel current controller (dual
voltage
sources);
(d) parallel current controller (single voltage source).
even when the switching frequency is limited to a few
hundred Hertz, as shown in the experimental results.
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Satoshi Ogasawara
(M87) was bom in Kagawa
Prefecture, Japan, on July 27, 1958. He received
the
B.S.,
M.S., and Dr.Eng. degrees in electrical
engineering from the Nagaoka University
of
Technology, Niigata, Japan, in 1981, 1983 and
1990, respectively.
Since 1983, he has been a Research Associate
at the Nagaoka University of Technology. He is
engaged in research
on
ac motor drives.
Dr. Ogasawara is a member of the Institute of
Electrical Engineers of Japan.
Jin
Takagaki was bom in Tochigi Prefecture,
Japan,
on
December
1,
1962. He received the
B.S. and M.S. degrees in electrical engheering
from the Nagaoka University of Technology,
Niigata, Japan, in 1984 and 1986, respectively.
Since 1986, he has been with Mitsui Petro-
chemical Industries, Ltd.
Mr. Takagaki is a member of the Institute of
Electrical Engineers of Japan.
Hirofumi Akagi (M87) was bom in Okayama
Prefecture, Japan,
on
August 19, 1951. He re-
ceived the B.S. degree from the Nagoya Institute
of Technology, Nagoya, Japan, in 1974 and the
M.S. and Ph.D. degrees from the Tokyo Insti-
tute of Technology, Tokyo, Japan, in 1976 and
1979, respectively, all in electrical engineering.
From 1979 to 1991, he was Assistant and then
Associate Professor in the electrical engineering
department at Nagaoka University
of
Technol-
ow.
In 1987. he was a visiting scientist at the
-1
Massachusetts Institute
2
Technolo& for ten month;. Since 1991, he
has been Professor in the electrical and electronic engineering depart-
ment at Okayama University. He is engaged in research
on
ac motor
drives, active power filters, and high-frequency inverters.
Dr. Akagi is a member of the Institute of Electrical Engineering of
Japan. He was a recipient of the IEEE/IAS Committee Prize Paper
Awards in 1980, 1983, and 1990, and the IEEE/ IAS Best Prize Transac-
tions Paper Award in 1991.
Akira Nabae F90)was bom in Ehime, Japan,
in 1924. He received the B.E. degree from the
University of Tokyo and the Dr. of Eng. degree
from Waseda University.
He joined Toshiba Corporation in 1951. From
1951 to 1970, he was engaged in the research
and development of converter and inverter tech-
nology at Tsurumi Works Engineering Depart-
ment. From 1970 to 1978, he was involved in the
research and development of power electronics,
especially ac drive systems, at the Heavy Appa-
ratus Engineering Laboratory. From 1978 to 1990, he was a Professor at
the Nagaoka University of Technology. Since 1990, he has been a
Professor Emerius of the university and a Professor at the Tokyo
Institute of Polytechnics.
Dr. Nabae received IEEE/IAS Static Power Converter Committee
Prize Paper Awards in 1980 and 1983, the I EE of Japan Transaction
Paper Award, and the Fukuda Award in 1985.
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