atf280e a rad-hard reprogrammable fpgamicroelectronics.esa.int/mpd2007/atf280e.pdf · esa/estec 3rd...
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ATF280E A Rad-Hard reprogrammable FPGA
ESA/ESTEC 3rd Microelectronics Presentation Days 2007
Valérie Ho-Shui-LingThibaud Gaillard
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 2
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
Overview
n ATMEL rad-hard FPGA family
n The ATF280E FPGA
n ATMEL FPGA architecture overview
n The AT69170E serial EEPROM
n Securing the ATF280E configuration
n ATF280E hardware & software design tools
n Key dates
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 3
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
AT40KEL040 ATMEL rad-hard FPGA
n The first generation, the AT40KEL040, is a fully compatible rad-hard version of the commercial AT40K40AL
nNo need for SEU mitigation while designing with it
nAT40KEL040§ AT56KRT 0.35um technology (same as MH1RT ASIC)§ All memory points are SEU hardened:
- Core-cell DFF / FreeRAM- Configuration Memory & Controller
§ TID tested up to 300 Krad§ 7 E-5 error/device/day in GEO
nDeveloped under CNES contract n° 721/00/8286/00 andn° 03/1433
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 4
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
AT40KEL040 Overview
nKey features§ 46K gates equivalent ASIC gates
§ 20 MHz clock speed
§ 2304 core-cells (each 2 LUT + 1 DFF)
§ 18 Kbit SRAM/TPRAM (144 modules of 32x4)
§ 3.3V Core and I/Os with 5V-tolerance
§ MQFPF-160 (129 User I/O) / MQFPF-256 (233 User I/O) packages
n Experience and lessons learned:§ Average 50% density (specific designs may go higher)
§ Average 10 MHz clock speed (specific designs may go higher)
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 5
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
AT40KEL040 Design Examples
n SODERN§ CNES Megha-Tropic project
§ Includes a Spacewire interface
nKONGSBERG§ ESA Gaia project
§ Solar array self-deployment system
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 6
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
ATF280E Overview
nATMEL’s second generation rad-hard FPGA§ AT58KRHA 0.18um technology (same as ATC18RHA ASIC)
§ Heavy ions induced SEU Fault-Tolerance by design
§ SET hardening (clocks and reset)
§ TID up to 300 Krad
§ 1 E-6 error/device/day in GEO
nDeveloped under CNES contract n° 04/1643/00 - 12245
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 7
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
ATF280E Key Features
n 280K equivalent ASIC gatesn 50 MHz clock speedn 14400 core-cells (each 2 LUT + 1 DFF)n 115 Kbit SRAM/TPRAM (900 modules of 32x4 blocks)n 1.8V Core / 1.8V and 3.3V I/Osn LVDS: 8 Rx + 8 TxnCold-sparing and 3.3V PCI-compliant I/Os
nMCGA 472 (308 User I/O) / MQFP-256 (150 User I/O) packages
nConfiguration load integrity checknConfiguration self-integrity checknBoundary scan interface
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 8
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
ATF280E Block-Diagram
FPGACore
120 x 120 core-cells30 x 30 FreeRAMs
Config.SRAM
Boundary Scan
Controller
LVDS Interface8 Rx / 8 Tx
UserI/O
ConfigurationSelf Integrity
Checker
Config.Control
POR
ConfigurationLoad
Checker
DifferentialClocks
8 Global / 4 Fast
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 9
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
FPGA Architecture Overview
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 10
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
Efficient Routing Architecture
n Efficient functions using almost only cell to cell connections
n FreeRAM uses very few global routing (address) and local (data) routing bus (free otherwise)
n Most of the routing structure is still available even if using all core-cells and FreeRAM
Cell to bus connection Cell to cell connection FreeRAM to bus connection
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 11
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
D QLUT
LUT
A
CD
CARRY
PRODUCT
or
DSP/Multiplier Mode
PRODUCT(registered)
B
D Q
LUT
A
B
C
Q
or
Synthesis Mode
Q(registered)
D
LUT
LUT
ABC
CARRY
Arithmetic Mode
D Q
Q
or
Q (registered)
D Q
LUT
LUT
Cin
CARRY
Counter Mode
Q
Tri-State/Mux Mode
2:1
MU
XA
B
C
Q
OE
Core-Cell Modes
n Efficient operators only use 1 core-cell / bit
n Fast multi-bit operators using cell to cell diagonal/orthogonal connections
n Pipelining (DFF) possible inside core-cell
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 12
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
Example of Optimized Function
X3Y0 X2Y0 X1Y0 X0Y0
X3Y1 X2Y1 X1Y1 X0Y1
X3Y3 X2Y2 X1Y2 X0Y2
X3Y3 X2Y3 X1Y3 X0Y3
X3 X2 X1 X0
Pi Ci
Ci+1Pi+1
Y0
Y1
Y2
Y3
P7 P6 P5 P4 P3 P2 P1 P0
+
Pi
Ci Xi
Yi
Ci+1
Pi+1
Parallel Multiplier Cell
>> Key to High-Performance Processing
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 13
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
AT69170E Overview
nATMEL’s first rad-hard by design serial EEPROM§ AT58K85RHA 0.18um technology
§ 5 E-7 error/device/day target in GEO
§ TID expected up to 60 Krad
nATF280E configuration download companion chip
nDeveloped under ESA contract n° 19083/05/NL/FM - COO1
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 14
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
AT69170E Key Features
n 4 Mbit Rad Hard EEPROM
n 512 bytes Pages
n FPGA serial configuration interface
n Standard TWI programming interface
n 3.3V Supply Voltage
n FP18 Package
n Endurance: 10K cycles
nData retention: 10 years
POR TWIInterf
Serial-izer
EEPROMCore
AT69170E
Memory Controller
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 15
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
Securing FPGA Configuration
n SRAM-based FPGAs reload their configuration on power-up
[1] Configuration Load checker (CRC) secures bitstream download
[2] Configuration Self-Integrity checker secures internalconfiguration during operation
POR TWI
Interf.Serial-izer
EEPROMCore
AT69170E
Memory Controller
FPGACore
Config.SRAM
Boundary Scan
ControllerLVDS Interface
UserI/O
Config.Self Int.Checker
Config.Control
POR
Config.Load
Checker
ATF280E
DifferentialClocks
1
2
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 16
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
ATF280E Compact-PCI Evaluation Board
n Compact PCI plug-in format:§ 6U format, 32 bit, 33MHz interface
§ Suitable for Peripheral slot
n On-board ATMEL devices§ ATF280E (MCGA-472)
§ AT69170E / 4 x AT17LV010 EEPROM
§ AT60142 + AT68166 SRAM
n Front-panel connectors§ 2 x Mini-DB9 (LVDS: 4Tx + 4Rx)
§ 8 x SMB (LVDS: 2Tx + 2Rx)
§ 1 x RJ45 (LVDS: 2Tx + 2Rx)
§ 1 x DB9 (RS232)
n On-board supply for standalone use
n On-board clock sources
n Probe / extension capability
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 17
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
ATF280E Design Tools
n Front-End§ MENTOR Modelsim for VHDL/VERILOG simulation§ MENTOR Precision Synthesis
- VHDL / Verilog entry- Automatic IDS Macro detection and mapping
nBack-End§ ATMEL Figaro IDS
- Automated Place & Route- VHDL / Verilog netlist export with SDF back-annotation- Bitstream generation
§ ATMEL Configurator Programming Tool- ATMEL EEPROM support- Used during development and ISP in final application
March, 8th 2007ESA/ESTEC 3rd Microelectronics Presentation Days 18
Third Edition of the Microelectronic Presentation Days ESA Noordwijk, March 7_8, 2007
Key Dates
nATF280E§ Design completed
§ Silicon in debug
§ Prototypes for Beta customers in end Q2 2007
§ Space qualification Q4 2007
nAT69170E§ On going design
§ First silicon in Q3 2007
§ Prototypes for Beta customers Q4 2007
§ Space Qualification Q1 2008
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