cascaded multilevel inverter

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A Prototype model of Field Programmable Gate Array (FPGA) Based Nine Level Cascaded Multilevel Inverter is to be designed and Implemented to produce AC output voltage of desired magnitude and frequency.

Xilinx software is used in FPGA for producing SPWM gating signals to the MOSFETs for producing the required AC output voltage.

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B.Shanthi, Natarajan.S.P, “FPGA based Fuzzy Logic Control for Single Phase Multilevel Inverter”.

International Journal of Computer Applications (0975-8887)

Volume9-No:3,November 2010.

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Azli, N.A. and Yatim, A.H.M.2001 Modular Structured Multilevel Inverter (MSMI) for high power Multilevel Inverter (MSMI). In: Proceedings of the 4th IEEE International Conference on Power Electronics and Drive Systems PEDS’01, Vol.2, 598-604.

Lai, J.S.and Peng, F.Z.: Multilevel Converters-A New Breed of Power Converters. In: IEEE Trans. Ind. Application., May/June 1996, Vol. 32, 509-517.

Carrara, G. and Gardella, S., Marchesoni M.,Salutari R.,Sciutto G.. A New Multilevel PWM Method: A Theoretical Analysis. In: IEEE Trans. Power Electron, July 1992, Vol. 7, 497–505.

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A proto type Single Phase Nine Level Cascaded Multilevel Inverter with Sinusoidal Pulse Width Modulation (SPWM) technique is implemented.

A Cascaded Multilevel Inverter consists of four full wave bridge inverters connected in series on the AC output side. Each bridge can create three different voltage levels in ac output allowing an overall Nine Level AC output voltage.

FPGA Programmable Logic Device developed by Xilinx is used for SPWM generator to supply the approximate signals to the Power Inverter Switches.

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PWM GENERATIOR

MODEL IN XILINIX

DOWNLOADED TO

I/O PORT OF FPGA

CASCADEDNINE LEVEL INVERTER

LC FILTER&

LOAD

OPTO COUPLER

&MOSFET DRIVER

+ DC input -

Nine levelAC output

BLOCK DIAGRAM

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Proto type model of a Single Phase Nine Level Cascaded MLI has been fabricated for an output voltage of 48v(Peak-Peak). The MOSFET switches are used in the power circuit.

Gating signals are generated from FPGA Controller. Driver circuit is used to amplify the signals.

Hardware model consists of the following circuits Power circuit. FPGA controller circuit. Driver and opto coupler circuit. Power supply unit.

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FPGA controller is used to generate sinusoidal pulse width modulation gating signals to the switches.

Xilinix software is used for SPWM generator to supply the approximate signals to the power inverter switches.

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An FPGA consists of an array of logic blocks, surrounded by programmable I/O blocks, and connected with programmable interconnect. A typical FPGA contains from 64 to tens of thousands of logic blocks and an even greater number of flip-flops.

Each logic cell can independently take on any one of a limited set of personalities.  The individual cells are interconnected by a matrix of wires and programmable switches. 

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Key components and features  Clock source.  Switches and leds.  Character led screen.  Rc232 serial port. Ps/2/mouse/key board port.  Analog to digital converter & digital to analog

converter. Pwm generator.

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* 100,000-gate Xilinx Spartan-3E XC3S100E FPGA in a 144-Thin Quad Flat Pack package (XC3S100E-TQ144) # 2,160 logic cell equivalents # Four 18K-bit block RAMs (72K bits) # Four 18x18 pipelined hardware multipliers # Two Digital Clock Managers (DCMs)

32 Mbit Intel Strata Flash * 3 numbers of 20 pin header to interface VLSI based

experiment modules 8 input Dip Switches * 8 output Light Emitting Diodes (LEDs) * On Board programmable oscillator (3 to 200 MHz)

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16x2 Alphanumeric LCD

* RS232 UART

* 4 Channel 8 Bit I2C based ADC & single Channel DAC

* PS/2 Keyboard/Mouse

* Prototyping area for user applications

* On Board configuration flash PROM XCF01S

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Opto coupler is used to isolate the control circuit from power circuit.

An Driver circuit is designed to connect the gate directly to a voltage bus with no intervening resistance other than the impedance of the driver circuit switch.

Gate driver acts as a high-power buffer stage between the PWM output of the control device and gates of the primary switching MOSFET (or) IGBT.

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Isolate the control circuit from power circuit. The 6N137 consist of a high emitting diode and a one chip

photo IC. This unit is 8−lead DIP package.

Pin Details 1 : N.C.

2 : Anode 3 : Cathode 4 : N.C. 5 : GND 6 : Output(Open collector) 7 : Enable 8 : VCC

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19

20

+15V

0

+15V

+15V

+15V

+15V

+15V

S2'

G2'

S1'

G1'

S4'

S3'

G3'

G4'

PWM Input 3'

8

7

5

3

2

6

20k

PWM Input 4'

8

7

5

3

2

6

U1

IR2110

1

7

1011

12

132

639

5

LO

HO

HINSHDN

LIN

VSSCOM

VBVCCVDD

VS

18V2

10k

U2B

4584

3 4

14

7

20k20K

0.1uF

1

20.1uF

1

2

10uf/63V4

10 k

20k1

20k

PWM Input 1'

8

75

3

2

6

20K2

20k1

4.7k

4.70 k

20K

PWM Input 2'

8

7

5

3

2

6

10 k

10uF / 63V

.01u

1 2

U2A

4584

1 2

14

7

FR107

U2B

4584

3 4

14

7

18V2

18V

20kU1

IR2110

1

7

1011

12

132

639

5

LO

HO

HINSHDN

LIN

VSSCOM

VBVCCVDD

VS

FR107

20k

10uf/63V0.1uF

1

2

10k

0.1uF

1

2

20k

18V

18V

10uf/63V4

20K2 18V

FR107

U2A

4584

1 2

14

7 FR107

10uf/63V

4.70 k

4.7k

4506

4506

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Single Phase Cascaded Nine Level Inverter with Sinusoidal Pulse Width Modulation (SPWM) technique is implemented by using FPGA controller.

It consists of four full bridge inverters connected in series on the AC output side.

Each bridge can create three different voltage levels (+Vdc,0,-Vdc) in ac output allowing an overall nine level ac output voltage.

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It is used to supply dc output voltage to the Inverter and FPGA driver circuit.

RATINGS

Primary Voltage= 230v AC

  Secondary Voltage = 0-9 v AC and 15-0-15v AC

  Regulator

  IC - 7805 and 7812 = Positive Voltage Regulator (+5v and +15v).

 IC - 7812 = Negative Voltage Regulator (-15v)

 Diode = 1N4007

  Capacitor = 4700µf/16v,4700µf/25v and 10µf/63v

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T1

T2

T3

T4

T5

T6T7T8T9T10

T11

T12T13

T14T15T16

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32

MI RMSvoltage

FRQ(Hz)

THD P-P (+)voltage

(-)voltage

MAX voltage

AVGvoltage

100 16.4 49.71 0.0 +24.4 -23.6 17.9 16.3

99 16.0 49.28 0.0 23.6 -23.3 16.6 16.0

98 16.1 48.73 0.0 24.0 -24.0 16.6 15.9

97 15.7 48.54 2.9 23.2 23.0 16.7 15.7

96 15.71 47.81 4.0 23.6 23.6 16.7 15.6

95 15.4 47.33 4.3 24.0 23.6 15.9 15.4

94 15.2 46.93 5.8 24.0 23.3 16.7 15.3

93 15.0 46.50 7.4 23.3 22.6 15.7 15.3

92 15.0 45.85 4.7 23.3 22.6 15.6 14.9

91 14.7 45.42 4.3 23.6 23.0 15.9 15.0

OUTPUTS OF CASCADED NINE LEVEL INVERTER

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90 14.6 44.81 3.9 24.4 23.6 16.7 14.7

89 14.4 44.21 3.3 23.3 22.0 15.7 14.4

88 14.3 43.79 3.7 23.3 22.3 15.7 14.2

87 14.1 43.45 3.4 23.3 21.6 16.1 14.1

86 13.9 42.90 3.4 24.4 22.0 16.1 14.0

85 13.8 42.32 3.8 23.0 22.0 16.1 13.7

84 13.6 47.91 3.8 23 21.3 16.1 13.7

83 13.7 41.47 4.2 24.7 22.3 16.8 13.6

82 13.3 40.97 4.7 22.0 20.6 16.1 13.2

81 13.2 40.30 4.5 20.0 20.6 16.1 13.2

80 12.0 0.0 0.0 21.3 20.3 0.0 12.9

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TOTAL HARMONIC DISTORTION OUTPUT WITH 5.8%

The performance of multilevel inverter (MLI) with fundamental and PWM switching schemes are studied through simulation using Matlab/Simulink.

It is observed that for Nine Level Multilevel Inverter, the THD is less in the case of PWM switching scheme. It is further identified that fundamental switching scheme gives better performance as the number of levels increases.

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B,shanthi,natarajan.S.P,” fpga based fuzzy logic control for single phase multilevel inverter”,international journal of computer applications(0975-8887) volume 9- n0:3,november 2010.

Azli, N.A. and Ning W.S. 2004 Application of Fuzzy Logic in Regulating a Multilevel Inverter output. In:Proceedings of 2004 International Conference on Power System Technolpgy, Singapore, 21-24.

Azli, N.A. and Wong, S.N. 2005 Development of a DSP based Fuzzy PI Controller for an Online Optimal PWM Control Scheme for a Multilevel Inverter. In: Proceedings of IEEE International Conference on Power Electronics and Drive Systems PEDS’05, 1457-1461.

Carrara, G. and Gardella, S., Marchesoni M.,Salutari R., Sciutto G.. A New Multilevel PWM Method: A Theoretical Analysis. In: IEEE Trans. Power Electron, July 1992, Vol. 7, 497–505.

Yan Deng, Hongyan Wang, Chao Zhang, Lei Hu and Xiangning He. 2005 Multilevel PWM Methods Based on Control Degrees of Freedom Combination and its Theoretical Analysis. In: Proceedings of the IEEE IAS Conference Record no.: 0-7803-9208-6 /05, 1692 – 1699

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