cifer: coherent interconnect and fpga enabling reuse order ... · many open source designs. •...
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Distribution Statement A – Approved for Public Release, Distribution Unlimited
www.darpa.mil
Design & Security: Posh Open Source Hardware (POSH) | Intelligent Design of Electronic Assets (IDEA)
CIFER: Coherent Interconnect and FPGA Enabling ReuseDavid Wentzlaff (Princeton University) and Christopher Batten (Cornell University)ORDER: Open-Source Rooted Design Experts with ReputeDavid Wentzlaff (Princeton University), Michael Taylor, and C-J Richard Shi (University of Washington)
CIFER: Coherent Interconnect and FPGA Enabling Reuse ORDER: Open -Source Rooted Design Experts with ReputeOverview: Create best-of-breed, open source, hardware blocks:• Scalable coherent memory system IP block
• On-chip Network Generator• Configurable, Field Programmable Gate Array (FPGA) IP block
Overview: • Support IDEA CAD tool performers by providing
System-on-Chip (SoC) design expertise along with many open source designs.
• Independent team of hardware design experts with a strong track record in open source and open collaboration, and design in advanced process nodes.
• Provide requirements, feedback, designs, and real world design experience to tool teams.
• Test IDEA CAD tools and tape-out multiple chips, boards, and packages with open source IDEA-created CAD tools.
LLC Cache Slice+
Directory Cache
Modified OpenSPARC T1
Core
LLC Cache Slice+
Directory Cache
Private Cache
PicoRV32RISC-V Core
Private Cache
P-MeshRouters
Scalable Coherent Memory System IP Block
P-MeshRouters
LLC Cache Slice+
Directory Cache
Ariane64-bit RISC-V
Core
Private Cache
P-MeshRouters
DDR Memory Controller
Ethernet Controller
PS/2 Keyboard UART
VGA/HDMI FramebufferMIAOW GPGPUWishbone SDHC
Controller
P-MeshCrossbars
Princeton Reconfigurable Gate Array (PRGA)• Open Source FPGA generator• Highly customizable• Highly scalable
– Capable of generating commercial-class FPGAs• Highly extensible
– Modularized workflow: replaceable and/or add steps– Supports different types of configuration circuitry
• Uses open-source CAD tools (VPR, Yosys), but does not modify other tools
PRGA Tool Chain• Synthesis: Yosys• Pack, Place, & Route: VPR
– Uses, but does not modify, latest upstream VPR• Bitstream generator: PRGA Bitgen Framework
– Generates bitstream using VPR outputs– Extensible to support custom configuration
circuitry types
github.com/PrincetonUniversity/prga
prga.readthedocs.io
• Heterogeneous SoC multicore/manycoreframework
• Integrate many different core types– OpenSPARC T1– RISC-V 64/32-bit
• Integrate many I/O devices– Ethernet, UART– DDR3/4
• Configurable On-Chip and Off-Chip Network– Mesh / Ring / Butterfly / Torus
• Extensibly integrates other POSH open source IP
Approach: Adapt ideas from Open Source Software Testing to Open Source Hardware Testing
● Statically generate test vectors that satisfy constraints
● Strong support in SystemVerilog with associated libraries (UVM)
● Rarely used in open-source HW design
● No open-source Verilog simulator supports UVM (UVM for SystemC exists)
● Dynamically generate test vectors that satisfy constraints
● Auto-shrink failures to generate minimal failing test cases
● First popularized with the Haskell QuickCheck library
● Emerging methodology in open-source SW design
● Customizable random generation strategies (currently adapting for fixed bitwidth types)
● Sophisticated auto-shrinking● Stateless and stateful testing● Caches counter examples
enabling “true” random testing
from hypothesis import givenfrom hypothesis.strategies \import text
@given( text() )def test_decode_inverts_encode(s):assert decode(encode(s)) == s
Constraint -Based Property -Based Adapt OSS Testing for OSH!
Example of Hypothesis with PyMTLStateful Testing
enq(data=59488)deq() -> 59488enq(data=8637)deq() -> 8637enq(data=18754)enq(data=37951)deq() -> 59488enq(data=23589)enq(data=17602)deq() -> 37951enq(data=35695)enq(data=43506)deq() -> 23589deq() -> 17602deq() -> 35695enq(data=50664)enq(data=227)enq(data=64506)deq() -> 43506
def test_state_machine():run_test_state_machine(
RTL2FLWrapper( QueueRTL(Bits16,4) ), QueueFL(Bits16,4) )
• Hypothesis will automatically compare a QueueFL reference component to a wrapped QueueRTL component by randomly calling methods with random data
• Hypothesis + Python’s powerful reflection features means we can create a property-based random test in just four lines of code!
github.com/cornell-brg/pymtl
github.com/PrincetonUniversity/openpiton
TurboXAUI SerDes TurboXAUI SerDes
Debug BaseJump I/O
DeepLearning
Accelerators
BaseJumpManycore
OpenPitonCores
Turb
oXAU
I Ser
Des
Turb
oXAU
I Ser
Des
FMC
DC/DC
SixPack SiP packageBaseJump
PCB
Turb
oXAU
I Ser
Des
Turb
oXAU
I Ser
Des
RISC-V cores
Deep Reinforcement Supervisors
AAA
A A A
AADRL ASIC
OpenPiton Design Benchmark
• Based on the OpenPiton open-source research processor
• 24 different modules– Variety of sizes, functionalities,
core counts• 636 “pickled” Verilog designs
– Instantiation of modules with different configuration parameters
• Includes floorplan and .sdc files for two configurations
FPGA bridge
Chip
Chip bridge
Tile
Dynamic node
L1.5
L2
SPARC
EXU
FFU
IFU
ifu_esl
ifu_esl_counter
ifu_esl_fsm
ifu_esl_htsm
ifu_esl_lfsr
ifu_esl_rtsm
ifu_esl_shiftreg
ifu_esl_stsm
LSU
MUL
TLU
FPU
Pico
github.com/PrincetonUniversity/OPDB
IDEA Analog Test Cases• Colla ting pre-exis ting, developed for other
projects , and developed for ORDER analog tes t cases into tes t suite
• Hierarchica l schematics• CDL files describe circuit (SPICE Netlis t)• Documenta tion and s imula tion results to enable
others to match results
Eye Diagram for TurboXAUI Transmitter
*******************************************************************
* Libra ry Name: AP_SerDes* Ce ll Name: Bias_v2* View Name: s chematic
************************************************************************
.SUBCKT Bias_v2 AVDD AVSS CALIN1[3] CALIN1[2] CALIN1[1] CALIN1[0] CALIN3[3] + CALIN3[2] CALIN3[1] CALIN3[0] CALIN5[3] CALIN5[2] CALIN5[1] CALIN5[0] + CALIN7[3] CALIN7[2] CALIN7[1] CALIN7[0] CALIP1[3] CALIP1[2] CALIP1[1]+ CALIP1[0] CALIP3[3] CALIP3[2] CALIP3[1] CALIP3[0] CALIP5[3] CALIP5[2] + CALIP5[1] CALIP5[0] CALIP7[3] CALIP7[2] CALIP7[1] CALIP7[0] Ibg In_1m In_3m + In_5m In_7m Ip_1m Ip_3m Ip_5m Ip_7m*.PININFO CALIN1[3]:I CALIN1[2]:I CALIN1[1]:I CALIN1[0]:I CALIN3[3]:I *.PININFO CALIN3[2]:I CALIN3[1]:I CALIN3[0]:I CALIN5[3]:I CALIN5[2]:I *.PININFO CALIN5[1]:I CALIN5[0]:I CALIN7[3]:I CALIN7[2]:I CALIN7[1]:I *.PININFO CALIN7[0]:I CALIP1[3]:I CALIP1[2]:I CALIP1[1]:I CALIP1[0]:I *.PININFO CALIP3[3]:I CALIP3[2]:I CALIP3[1]:I CALIP3[0]:I CALIP5[3]:I *.PININFO CALIP5[2]:I CALIP5[1]:I CALIP5[0]:I CALIP7[3]:I CALIP7[2]:I *.PININFO CALIP7[1]:I CALIP7[0]:I AVDD:B AVSS:B Ibg:B In_1m:B In_3m:B In_5m:
github.com/uwidea /UW-IDEA_AnalogTes tCases
As the externa l des ign advisors , we will be us ing the IDEA/POSH infras tructure to build 14 and 7nm prototypes , ca lled AADRL (Acce le ra tor ASIC for Deep Reinforcement Learning)
• OpenPiton re lease 11 brings RISC-V SMP Linux• CIFER is deve loping transducers be tween cores
and sca lable coherent memory sys tem (e .g. Ariane , Black Parrot, PICORV32)
• ORDER is leveraging des igns cases based on OpenPiton as tes t cases for IDEA CAD tool deve lopers
• www.openpiton.org
L2 Cache Slice+
Directory Cache
P-MeshRouters
(3)
L1.5CachePULP Ariane
RISC-V Core
BSG SystemVerilog to Verilog Converter (bsg_sv2v)
github.com/bespoke-s ilicon-group/bsg_sv2v
BSG Pipeclean Suitegithub.com/bespoke-s ilicon-group/bsg_pipeclean_suiteCollection of designs used to stress
test new CAD flows. Each design isstresses a different aspect of theCAD flow with increasing complexity.
Designs make use of the IDEADimensionless (IDF) specification.Floorplan and timing constraint filesare dimensionless meaning that allunits are expressed in terms ofproperties of the process rather thanconcrete units (such as microns orpicoseconds).
Scalable Coherent Memory System IP Block
This material is based on research sponsored by the Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) under agreements No. FA8650-18-2-7846 and FA8650-18-2-7852. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) or the U.S. Government.
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