cmos amplifiers

CMOS AMPLIFIERS

• Simple Inverting Amplifier

• Differential Amplifiers

• Cascode Amplifier

• Output Amplifiers

• Summary

Simple Inverting Amplifiers

Small Signal Characteristics

How do you get better matching?

Inverter with diode connection load

2

1

221

1

m

m

mdsds

m

in

outv g

g

ggg

g

v

vA

12

21

12

21'

'

LW

LW

LW

LW

K

K

v

vA

P

N

P

N

in

outv

2221

11

mmdsdsout gggg

r

High gain inverters

Current source load or push-pull

• Refer to book for large signal analysis

• Must match quiescent currents in PMOS and NMOS transistors

• Wider output swing, especially push-pull

• Much higher gain (at DC), but much lower -3dB frequency (vs diode load)

• About the same GB

• Very power dependent

Small signal

High gain! Especially at low power.

21

21

dsds

mm

in

outv gg

gg

v

vA

21

1

dsds

m

in

outv gg

g

v

vA

Dm Ig 21 Dds Ig 1

D

vI

KA

21

1

dsdsout gg

r

))(1(|)|(2

)1(|)|(2

))(1()(2

)1()(2

22

2

2

2

2

22

22

1

1

2

1

11

oV

PTPinGGPDDoxP

DSPTPSGoxP

D

oV

NTinGGoxN

DSNTGSoxN

D

vVvVVL

WC

VVVL

WCI

vVvVL

WC

VVVL

WCI

DD

DD

Key to analysis by hand:• Use level 1 or 3 model equations• Use KCL/KVL

PTCDDoxP

ds

mTCDDoxP

m

NTCDDoxN

ds

TCDDoxN

m

DDoCDDGGPCDDGG

C

NPTTPoxPoxN

VEVL

WCg

gVEVL

WCg

VEVL

WCg

VEVL

WCg

VVEVVEVV

E

VVL

WC

L

WC

2

2

22

12

22

2

1

11

1

11

2

2

1

1

)2/)((2

)2/)((

)2/)((2

)2/)((

2/,2/)(,2/)(

:ispoint operating then used, is offset battery a and

,,|| suppose,22

Let

Dependence of Gain upon Bias Current

Transfer function of a system

Systeminput u output y

)()1(

)1()()()(

11

1

11

10 susasasa

sbsbsbAsusHsy

nn

nn

mm

mm

)()1()1)(1(

)1()1(

21

10

su

ps

ps

ps

zs

zs

A

n

m

0)()1( 11

1 sysasasa n

nn

n When u(s) = 0, y(s) satisfies:

These dynamics are the characteristic dynamics of the system. The roots of the coefficient polynomial are the poles of the system.

When y(s) = 0, u(s) satisfies:

0)()1( 11

1 susbsbsb m

mm

m These dynamics are the zero dynamics of the system. The roots of the coefficient polynomial are the zeros of the system.

Frequency Response of CMOS Inverters

Poles of CMOS Inverters

Let vin = 0, x = 0, VDD = 0, VSS = 0.

yCGS1, CGS2, CBS1, CBS2 are all short

CGD1, CGD2, CBD1, CBD2, CL in parallel

C’L = Ctotal = CGD1+ CGD2+ CBD1+ CBD2+ CL

Total conductance from y to ground:

go = gds1 + gds2

KCL at node y:

0)()1(

0)()(

0)()(

0

'

'

'

sys

sygsC

tygdt

tdyC

i

L

o

Cg

oL

oL

Therefore system pole is: '1L

o

C

gp

Zeros of CMOS Inverters

Let vin = x = u, VDD = 0, VSS = 0.

gds1, gds2 also short

CGD1, CGD2, are in parallel, CBD1, CBD2, CL are all short

No current in them

KCL:

0)()]()[(

)()()()(

2121

2121

suggsCC

gtugtudt

tduC

dt

tduC

mmGDGD

mmGDGD

Zero is:21

211

GDGD

mm

CC

ggz

Zeros of CMOS CS Load Amp

Let vin = u, X=0, VDD = 0, VSS = 0.

gds1, gds2 also short

CGS2, CGD2, CBD1, CBD2, CL are all short

No current in them

KCL:

Zero is:

1 1

1 1

( )( )

[ ] ( ) 0

GD m

GD m

du tC u t g

dtC s g u s

1

11

GD

m

C

gz

Input output transfer function

)1(

)1(

)1(

)1(

)(

'21

21

2121

21

1

10

L

dsds

GDGD

mmdsds

mm

C

ggs

CC

ggs

gg

gg

pszs

A

sA

When s=j0, A(0) 21

210

dsds

mm

gg

ggA

When w∞, A(s) 1'

21

L

GDGD

C

CC

|p1|=g0/CL’

|z1|=gm/Cgd

=GB*CL’/Cgd

|A0 | =gm/go

0 dB

Unity gain

frequency

=|A0p1|

=GB

=gm/CL’

Acl=1/

-3dB frequency of closed loop=*GB

Unity gain feedback

A(s)

0 1

0 1 1

(1 )( )

1 ( ) 1 (1 )c

A s zA sA

A s A s z s p

0 1 1

1 1 0 0 1 1

1 1 00

0 1 1

For Closed-loop pole: 1 (1 ) 0

(1 ) ( ) 0

(1 )

A s z s p

z p A A p z

z p As A p

A p z

Closed-loop zero: z1

If a step input is given, the output response is

By the final value theorem:

0 1

0 1 1

(1 ) 1( )

1 (1 )step

A s zY s

A s z s p s

0

0

( )1step

Ay t

A

By the initial value theorem:

0 1 0 1 0 1

0 1 1 1 0 1 1

/( 0 )

/ 1step

A z A p A py t

A z p z A p z

Final settling determined by A0

need high gainSettling speed determined by A0p1=GB=UGF,

need high gain bandwidth product

-1

0

01

A

A

0 1

1

A p

z

0 1 decayA p te

Gain bandwidth product

'21

'21

21

2110

L

mm

L

dsds

dsds

mm

C

gg

C

gg

gg

ggpAGB

C’L = Ctotal = CGD1+ CGD2+ CBD1+ CBD2+ CL

LDjDjoxoxL CLWCLWCLWCLWCC 221121'

22

21

1

121 EB

oxPEB

oxNmm V

L

WCV

L

WCgg

When CL ≈ C’L, W↑GB↑, but it saturates, when

LDjDjoxox CLWCLWCLWCLWC 221121

22

2

221

1

1

22 EBoxP

EBoxN

D VL

WCV

L

WCI

Note:

If VEB1 and VEB2 are fixed, W1/L1 and W2/L2

must be adjusted proportionally, and they are

proportional to DC power.

22

2

221

1

1

22 EBDDoxP

EBDDoxN

DDD VVL

WCVV

L

WCIVP

11

2

2

11

1

1 2,

2

EBDDEB

oxP

EBDDEB

oxN

VV

PV

L

WC

VV

PV

L

WC

)11

(222

211121

EBEBDDEBDDEBDDmm VVV

P

VV

P

VV

Pgg

)11

()),((

2

)11

(2

2121

21'

EBEBDDL

EBEBDDL

VVVWWCC

P

VVVC

PGB

Therefore:

P is proportional to W1, W2CL constant, but C(W1,W2) proportional to W1, W2When C(W1, W2) << CL, GB proportional to PWhen C(W1,W2)CL or >CL, GB saturates

P

GB

Linear increase region

),(

2

),(

2

21

1

21'1

WWCC

W

L

IC

WWCC

I

C

gGB

L

DoxN

L

D

L

m

For given current or power (current source load)

Initially, as W1 increased, GB increases

But GB will reach a max, and then drop as W1 increases

NOISE IN MOS INVERTERS

22

2

2

121

0

2n

m

mn

Vout e

g

gee

in

22

2

1

2212

22

nm

mn

v

outeq e

g

ge

A

ee

21

22

2

1

221

2 1n

n

m

mneq

e

e

g

gee

NN

PPneq BK

BK

L

Lee

'

'2

2

121

2 1

constant; :noise 1/fFor 2 BfWL

Ben

Dm IL

WKg

'2

N

P

DN

DPneq B

LfW

LfW

B

LIWK

LIWKee 11

2211'

22'

21

2

/2

/21

To minimize:

1) L2 >>L12) En1 small 1

2

2'

1'

L

L

WK

WKgain

P

N

For thermal noise

Noise in Push-Pull current source load Inverter

Differential Input, single-ended output single stage Amplifier

N-Channel

vin+vin-

P-channel

Large Signal Eq. in a N-channel Differential pair

iD1=0, when iD2=ISS and VGS2=VT+(2ISS/)0.5

=0.51(VGS1-VT)2

=(2ID1/1)0.5

21

2

21212

42

222

22

DDSSID

DDDDID

iiIv

iiiiv

21

22

21212

42

4)2

(2

4424

DDID

SSSSSS

DDDDSSSSID

iiv

III

iiiiIIv

22121

242

2 )(44 DDDDSS

IDIDSS iiiiI

vvI

4

422

21ID

IDSSDD

vvIii

Solving for iD1 and iD2

VON1=VON2=(ISS/)0.5iD1=iD2=ISS/2

2

422

21 422,

SS

ID

SS

IDSSSSDD I

v

I

vIIii

N-Channel Input Pair Differential Amplifier

C.M. Load

C.M. Bias

Simplecurrentreference

Voltage transfer curve

P-Channel Input Pair Differential Amplifier

Voltage transfer curve

INPUT COMMON MODE RANGE

VG1=VG2=ViCM

VSDSAT1=VSDSAT2

=VON

VD1=VD3=VSS+VT3+VON

VG1min=VD1-|VT1|

VG1max=VDD-VSD5SAT-|VT1|-VON

Output Range

Vomin=Vss+Von4

Vomax=Vicm –|VT2|

So what’s the vo range

What’s for the N-chcircuit.

SMALL SIGNAL ANALYSIS

AV

Common Mode Equivalent Circuit, with perfect match

iC1

iC1=VIC/(1/gm1

+2rds5)

ro1≈1/gm3

ACM≈1/ 2rds5gm3

1 2 41 5 3 2 4

13

1 5

/ ( )1

/1

vdm m ds dsm ds m ds ds

mvcmm

m ds

A g g gCMRR g r g r r

gA gg r

If not perfectly matched

iC1

io=iIC

is a fraction

go1≈ gds4 + gds2/2Av5

≈ gds4

CMRR=Av/ACM= gm1/gm5

ACM ≈ gm5 / 2gds4

equations. all on to

respect withderivative partial take small, const Let

d

dic

sTGGDD

oDDTpGDD

soTsd

icD

GDDTpGDD

sGTsd

icD

v

vV

VVVIII

VVVVV

VVVVv

VI

VVVVV

VVVVv

VI

,)1

12

12

122

12

122

525

521

42

34

2

22

2

332

33

31

21

1

Formal detailed analysis

d

sTGG

d

D

d

D

d

GoDDTpGDD

d

oTpGDD

d

s

d

oTs

dic

d

ssoTs

dic

d

D

d

GTpGDD

d

GGDDTpGDD

d

s

d

GTs

dic

d

ssGTs

dic

d

D

v

VVV

v

I

v

I

v

VVVVVV

v

VVVV

v

V

v

VVV

vV

v

VVVVV

vV

v

I

v

VVVV

v

VVVVVV

v

V

v

VVV

vV

v

VVVVV

vV

v

I

52521

3434

42

34

2

22

222

33

23

3

33333

31

21

3111

2

1

2

22

2

11

2

2

1

22

2

11

2

ic

Gds

ic

Gm

ic

GTpGDD

ic

GGDDTpGDD

ic

s

ic

Gds

ic

sm

ic

s

ic

GTsic

ic

ssGTsic

ic

D

ic

icd

v

Vg

v

Vg

v

VVVV

v

VVVVVV

v

V

v

Vg

v

Vg

v

V

v

VVVv

v

VVVVVv

v

I

v

vv

33

33

33

23

3

33333

311

31

21

3111

2

1

1

2

11

,0)2

equations. all on to respect withderivative partial take

variable, tindependen as Let

ic

sds

ic

sTGG

ic

D

ic

D

ic

ods

ic

Gm

ic

oTpGDD

ic

GoDDTpGDD

ic

s

ic

ods

ic

sm

ic

s

icTsic

ic

ssoTsic

ic

D

v

Vg

v

VVV

v

I

v

I

v

Vg

v

Vg

v

VVVV

v

VVVVVV

v

V

v

Vg

v

Vg

v

V

v

VoVVv

v

VVVVVv

v

I

552521

43

4

42

34

3434

22

222

222

2

2

1

1

2

11

SLEW RATE: the limit of the rate of change of the output voltage

Max |CLdvo/dt|=ISS

C’Ldvo/dt=i4-i2

Slew Rate = ISS/C’L

ISS

ISSISS

0Output swing: Vosw

GB frequency: fGB

vo(t)=Voswsin(2fGBt)

Max dvo/dt =Vosw2fGB

To avoid slewing: ISS > C’L Vosw2fGB

Parasitic Capacitances

CT: common mode only

CM: mirror cap = Cdg1 + Cdb1 + Cgs3 + Cgs4 + Cdb3

COUT = output cap= Cbd4 + Cbd2 + Cgd2 + CL

• Impedances– rout = rsd2 || rds4 = 1 / (gds2 + gds4)

– rM = 1/gm3 || rds3 || rds1 ≈ 1/ gm3

– Hence the output node is the high impedance node

• When vi=0, slowest discharging node is output node with dominant pole

p1 = -1/(C’outrout), where C’out = Cout+ Cgd4

• Approximate transfer function

AV(s) = AV/(s/p1─1)

When vG1=vG2=0(AC)

KCL at D1:

omdsdsgdM

gdD

DmdsdsoD

gdD

M

vgggsCC

sCv

vgggdt

vvdC

dt

dvC

3314

41

13311

41

)(

0)()(

KCL at D2:

144424

14421

4

)())((

0)()(

Dmgdodsdsgdout

DmodsdsDo

gdo

out

vgsCvggsCC

vgvggdt

vvdC

dt

dvC

omgdgd

omdsdsgdMdsdsgdout

vgsCsC

vgggsCCggsCC

)(

)))(()((

444

3314424

Gain bandwidth product

• Gain AV(0) = gm1 / (gds2 + gds4)

• Bandwidth ≈ |p1| ≈ (gds2 + gds4) / C’out

• GBW ≈ gm1 / C’out

• gm1 = {2*ID1CoxW1/L1}½

– increase gm1 increase GBW

– increase W1 increase GBW• But C’out has Cdb2 and Cgd2 W1

– Once Cdb2 and Cgd2 become comparable to CL, increasing W1 reduces GBW

Other poles and zeros

M3

M2

M5

M1

M4

Vb2

VDD

VOUT

CL

Vi+ Vi-

Cgd4

(1+AV4)Cgd4

Cgd4

Second pole at D1

r = 1/gm3

C = CM +

(1+AV4)Cgd4

p2 = CM + (1+AV4)Cgd4

─ gm3

AV4 = gm4/gds4

M3

M2

M5

M1

M4

Vb2

VDD

VOUT

CL

Vi+= - Vi-

Vi-

Unstable zero at Cgd2

Enforce vo=0, float vin.

ids2, ids4 = 0

Cgd2 dvi-/dt= gm2 vi-

z1 = gm2/Cgd2

M3

M2

M5

M1

M4

Vb2

VDD

VOUT

CL

Vi+ Vi-

For zero at D1:

For diff, Vi+ = - Vi-

which is set by Cgd2

Both Cgd4 and Cgd1 to gnd

Ctot = CM + Cgd4

z2 = CM + Cgd4

─gm3

• A better approximation of TF:AV(s)=AV(s/z1-1)(s/z2-1)/(s/p1-1)(s/p2-1)

• If p1 is dominant, |p1|<<|p2|,|z1|,|z2|; AV(s)≈AV/(s/p1-1)

• If p1 is non-dominant, at low frequency, AV(s)≈AV /(s/p1+s/p2-s/z1-s/z2 -1)

• 1/peq≈ 1/p1+1/p2-1/z1-1/z2 ≈ 1/p1+1/p2-1/z2 ,

since |z1| >> |z2|, |p1|, |p2|; ≈ 1/p1, if AV4 is not

very large

• In either case, BW ≈ p1

frequency response

AV

-90

-180PM

p1 p2 z2z1

UGF

All in abs val

Observations

• PM ≈ 90 – tan-1(UGF/z1) GBW should be at least 2~3 times lower than z1 to

ensure good phase margin at UGF There is conflict between AV and PM

• If z2 not = p2, UGF < AV*p1

• Design approaches• make z1 high higher than UGF

• make Cgd2 small, gm1 large

• make z2 close to p2 better 1st order approx. • make AV4 small

• make p1 low large AV

• make gds2 and gds4 small

Design Steps

• Select Iss based on– GB & V_osw, SR, or P_max

• Select W1/L1 based on– GB = gm/CL’, Assuming CL’ = (1.1~1.5)CL– Maximize z1 (minimize Cgd2)

• Select W4/L4 based on– ICMR, – Small Av4

• Select W5/L5 based on– ICMR

NOISE Model

Input equivalent noise source

• Total output noise current is found as,

• Let

• Then

How does this affect Av4 and go?

Cascoding

• Objectives– Increase ro

– Increase AV

– Remove feed forward from vin to vo

– Remove unstable zero

• Methods– Direct cascoding– Folded cascoding

CMOS CASCODE AMPLIFIERS

VDD

Vbb

Vin

CL

Rb

Vout-min increase by VON2

Vout-max decreased if aCascoded source used

Output swing is a big Problem in low voltageApplications

VDD

Vin

CL

Rb

Vbb

Vin

CL

Vyy

Vxx

VDDQ: How should you set the bias?Q: what is Vout-max?

ro =

AV =

ro at D1?

vD1

vin

=

Cascoded current source load

Vbb

Vin

CL

Vyy

Vxx

VDDHigh frequency model

AV(s) =AV0(s/z1 -1)…

(s/p1-1)(s/p2-1)…

For poles, short input, and compute the time constants at each node. For zeros, float input but require vo = 0. (don’t short vo!)

Consider only the effect of the lower half circuit.

Vbb

Vin

CL

Vyy

Vxx

VDDShort vin, float vo:

At the high impedance node

r =rds1(gm2+gmb2)rds2

C =CL+Cdb2+Cgd2

p1 = -1/RC

At the low impedance node

r =1/(gm2+gmb2+gds1+gds2)

C =Cgd1+Cdb1+Cgs2+Csb2

p2 =

Vbb

Vin

CL

Vyy

Vxx

VDDEnforce vo=0, float vin.

At the G1-D node

iCo=0, no current cross line, and iCgd2=0id2, id3 = 0, gm2vgs2=0

Was the unstable zero removed?

vs2=0

igds1=0

sCgd1vin=gm1vin

Gain bandwidth product

• If |p1| << |p2|, |p3|,…, |p1| << |z1|, |z2|,…

– BW ≈ |p1|

– GBW ≈ gm1/Co

• Otherwise– AV(s) ≈ AV/(s/p1+s/p2…-s/z1-s/z2… - 1)

– 1/BW ≈ 1/p1+2/p2…-1/z1-2/z2… = RC1 + RC2 + …

VDD

Vbb

Vin

CL

Rb

VDD

Any enhancement?

Note: rds2, Rb 1/ID2

gm2 √ID2

Effects on:

ro, AV

Co, GBW

Slew rate

VDD

Vbb

Vin

CL

Rb

Another possible modification

Effects on:

ro, AV?

Co, GBW?

Slew rate?

poles?

zeros?

VDD

Vin CL

Folded cascoding

Which I source should be cascoded?

ro, AV?

Co, GBW?

Slew rate?

poles?

zeros?

Vbb

OUTPUT AMPLIFIERS

• Requirements– Provide sufficient output power in the form of

voltage or current.– Avoid signal distortion for large signal swings.– Be power efficient.– Provide protection from abnormal conditions.

• Types of Output Stages– Class A amplifier.– Source follower.– Push-Pull amplifier ( inverting and follower).– Negative feedback (OP amp and resistive).

Power efficiency

• It is most power efficient at maximum signal level

• Let VSS= ─VDD, Vin is sinusoidal such that Vout reaches Voutmax

• PRL = ½ (Voutmax)2/RL

• Psupply>=average((VDD or VSS)*IRL) =VDD*average(Voutmax*sin()/RL) =2*VDD*Voutmax/RL/

• Power efficicy = PRL/Psupply<=/4 (78%)

CLASS A AMPLIFIER

ro, AV, z, p as before

Power effic = PRL

Psupply

= 0.5voutmaxIQ

IQ(VDD-VSS) < 25%

VSS= -VDD, Voutmax=VDD-Vdssat

SOURCE FOLLOWER

or VSS+VT

Push-pull

Push-pull inverting amp

Implementation

PUSH-PULL SOURCE FOLLOWER

If Vo = 0

Bias current well controlled

Vo swing is very limited

If Vosp=Vosn=0

If A(Vosp-Vosn)<<Vov

Combining the previous two:

At quiescent,Vo=v1+vgs4-vgs1=v1

This requires(W/L)1:W/L)2= (W/L)4:W/L)5

Example error amplifier

M15 is like a resistor connecting the drain and gate of M17, leaving M17 as level shifted diode connection. I17 =Ib. By CM connection, I13 = I14 = m*Ib. I11=I12=Itail/2. I15=I16=I13-I12=m*Ib-It/2. When vi != vo, I12 varies from 0 to Itail. Hence, need m*Ib > Itail.

Super source follower

VDD

Vin

Vo

Vo => I1 =(gm1+gmb1)Vo

VGS2= ro1(gm1+gmb1)Vo

I2 = gm2ro1(gm1+gmb1)VoI1

I2

go=gm2ro1(gm1+gmb1) +(gm1+gmb1)+go2

≈gm2ro1(gm1+gmb1)Gm ≈gm1+gm1ro1gm2

AV=Gm/go≈gm1

gm1 + gmb1

Ex: rework these when I1 and I2 have finite ros.

VDD

Vin

Vo

I1

I2

If we re-arrange witha flipped version, we get this push-pullsuper source follower

Ex: provide a transistorlevel implementation.Comment on powerefficiency.