design of electronics, trigger and data acquisition system for the proposed ino prototype detector
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B.Satyanarayana(For INO collaboration)
Department of High Energy Physics
Tata Institute of Fundamental ResearchHomi Bhabha Road, Colaba, Mumbai, 400 005
E-mail: bsn@tifr.res.in
Design of electronics, trigger and data acquisition system for the proposed INO
prototype detector
XVI DAE-BRNS Symposium on HEP SINP, Kolkata Nov 29 - Dec 3, 2004 2
INO prototype detector• Detector and signal specifications
– Detector dimensions: 1m X 1m X 1m – 14 layers of RPCs with 6cm iron plates interleaved.– Two signal planes orthogonal to each other and each having 32 pick-up strips– Total channels = 32 X 14 X 2 = 896– Pulse height = 100 to 300mV; Rise time = < 1 ns– Pulse width = ~50ns; Rate ~ 1KHz
• Trigger information– Expected trigger rate is few Hz– Required Trigger logic is m X n fold, where – m = 1 to 4; no. of consecutive channels in a layer – n = 5 to 1; no. of consecutive layers with m fold in each layer – ie m x n = (1 x 5) OR (2 x 4) OR (3 x 3) OR (4 x 2)
• Information to be recorded on a trigger – Absolute arrival time of the trigger – Track identification (XYZ points in RPC layers)– Direction of track ( TDC information)– Miscellaneous information and calibration data
• Monitoring health of the detector
XVI DAE-BRNS Symposium on HEP SINP, Kolkata Nov 29 - Dec 3, 2004 3
Readout scheme for prototype X-plane RTC Y Final X Trigger TDC Event Scalers
FEE Control Logic Read Data &
Monitor Monitor Scalers CAMAC Controller
LAN
PC (LINUX)
CAMAC
1 2 8 9 10 14
1 2 8 9 10 14
Front End Electronics
Trig & TDC Router
Y-p
lane
XVI DAE-BRNS Symposium on HEP SINP, Kolkata Nov 29 - Dec 3, 2004 4
32-channel front-end module 1 2 3 ……………………………………………………………32
Threshold
Mon SI
Mon SO
Addr & Control
Event Trig
Eve SI Eve SO
FPGA
32 ECL Comparators
Trigger 0 Logic (ECL)
&
Timing signal
Trigger 1 M fold Logic
( CPLD )
Level Translator & Wave shaper (32+8)
SHIFT REGISTER ( 48 bit )
Board ID (SW8)
Monitor
MUX unit ( 40 : 1 )
Module Selection
LV
DS
EVE (SW4) MON(SW4)
Counter
XVI DAE-BRNS Symposium on HEP SINP, Kolkata Nov 29 - Dec 3, 2004 5
Prototype detector trigger logic
Front End Electronics X-Plane Y-Plane Level-0
Level 1 S1….S8 S1…S8 S1…S8
1F,2F……4F 1F,2F……4F 1F,2F……4F 1F,2F……4F (LVDS interface)
Level-2 ( Back end )
F1(14)…………..F4(14) F1(14)…………..F4(14) (
OR
L1P1
(mF)
L14P1
(mF) L14P2
(mF) L1P2
(mF)
P1 (m x n fold)
P2 (m x n fold)
Final Trigger
S1=1+9+17+25 S2=2+10+18+26 ………. S8=8+16+24+32
Trigger & TDC signals Router
Trigger & TDC signals Router
XVI DAE-BRNS Symposium on HEP SINP, Kolkata Nov 29 - Dec 3, 2004 6
Readout scheme for final detectorThe keywords are channel count and fast timing
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