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Design Design Technology and Technology and Computer Aided Computer Aided DesignDesign
2
Outline
• Automation: synthesis
• Verification: hardware/software co-simulation
• Reuse: intellectual property cores
• Design process models
3
• Design task– Define system functionality
– Convert functionality to physical implementation while• Satisfying constrained metrics
• Optimizing other design metrics
• Designing embedded systems is hard– Complex functionality
• Millions of possible environment scenarios
• Competing, tightly constrained metrics
– Productivity gap• As low as 10 lines of code or 100 transistors produced per day
Introduction
Who is winning?
4
Improving productivity
• Design technologies developed to improve productivity
• We focus on technologies advancing hardware/software unified view– AutomationAutomation
• Program replaces manual design
• Synthesis
– ReuseReuse• Predesigned components
• Cores
• General-purpose and single-purpose processors on single IC
– VerificationVerification• Ensuring correctness/completeness of each design step
• Hardware/software co-simulation
Reuse
Specification
Implementation
Automation
Verification
Who is winning?
5
Automation: synthesis
• Early design automation was mostly for hardware
• Software complexity increased with advent of general-purpose processor
• Different techniques for software design and hardware design
– Caused division of the two fields
• Design tools evolve for higher levels of abstraction
– Different rate in each field
• Hardware/software design fields rejoining– Both can start from behavioral description in
sequential program model– 30 years longer for hardware design to reach this
step in the ladder• Many more design dimensions• Optimization critical
Implementation
Assembly instructions
Machine instructions Logic gates
Logic equations / FSM's
Register transfers
Sequential program code (e.g., C, VHDL)
Compilers(1960s,1970s)
Assemblers, linkers(1950s, 1960s)
Behavioral synthesis(1990s)
RT synthesis(1980s, 1990s)
Logic synthesis(1970s, 1980s)
Microprocessor plus program bits
VLSI, ASIC, or PLD implementation
The codesign ladder
6
Hardware/software parallel evolution
• Software design evolution– Machine instructions– Assemblers
• convert assembly programs into machine instructions
– Compilers • translate sequential programs into assembly
• Hardware design evolution– Interconnected logic gates– Logic synthesis
• converts logic equations or FSMs into gates
– Register-transfer (RT) synthesis • converts FSMDs into FSMs, logic equations,
predesigned RT components (registers, adders, etc.)
– Behavioral synthesis• converts sequential programs into FSMDs
Implementation
Assembly instructions
Machine instructions Logic gates
Logic equations / FSM's
Register transfers
Sequential program code (e.g., C, VHDL)
Compilers(1960s,1970s)
Assemblers, linkers(1950s, 1960s)
Behavioral synthesis(1990s)
RT synthesis(1980s, 1990s)
Logic synthesis(1970s, 1980s)
Microprocessor plus program bits
VLSI, ASIC, or PLD implementation
The codesign ladder
Physical Physical DesignDesign
PlacementPlacement
CLB netlist
Assign logic to cells
S S S S
L
SS
L
S
L
S
L
SS
L
S
L
S
L
SS
L
S
L
S
RoutingRouting
S S S S
L
SS
L
S
L
S
L
SS
L
S
L
S
L
SS
L
S
L
S
Realize the interconnection by turning onswitches of routing resources.
Placement & Routing MethodsPlacement & Routing Methods
• Placement - simulated annealing is the commonly used method.
• Routing - routability-driven and timing-driven.
• Time-consuming design tasks.
• Architectural dependent.
HDL-based Design Flow for HDL-based Design Flow for Multi-FPGA Multi-FPGA DesignsDesigns
HDL descriptionHDL description
HDL synthesis
Netlists
Partitioning
Partitioned netlists
Basic Partitioning Basic Partitioning TechniquesTechniques
• The min-cut partitioning: – The Kernighan-Lin algorithm. – The Fiduccia and Mattheyses algorithm. – The Krishnamurthy algorithm.
• The ratio-cut algorithm.
• A variety of clustering algorithms.
Multi-FPGA PartitioningMulti-FPGA Partitioning• Constraints:
1. Fixed number of I/O pins in a device.
2. Fixed number of CLBs in a device.
3. Utilization of all devices.
• Objectives: • 1. Cost minimization. • 2. Delay minimization.
Circuit-Level Partitioning MethodsCircuit-Level Partitioning Methods
• Multiway partitioning methods based on the min-cut algorithm.
• Interconnect minimization by cell replication.
• Clustering-based partitioning methods - cone.
• Combining top-down partitioning and bottom-up clustering methods.
Considerations for Multi-FPGA Considerations for Multi-FPGA PartitioningPartitioning
• Limited IO-pin and logic resources.
• Logic utilization is predominated by IO-pin limitation.
• How to alleviate the IO-limitation problem is the key to improve the logic utilization of FPGA chips.
Combining HDL Synthesis Combining HDL Synthesis and Partitioningand Partitioning
Bridging HDL synthesis and partitioning?
HDL description
HDL synthesis
Netlists
Partitioning
Partitioned netlists
Design ConsiderationsDesign Considerations
HDL Spec.
Application-Oriented Synthesis
Module-based
Bit-sliced Function-based
Fine-grained
Varying coding styles
Datapath-dominatedControl-dominated
There are two main coding styles: datapath dominated and control dominated
Coding StylesCoding Styles
Top
M1 M2 M11 M12 M21 M22
Top
Mod1
Mod1_1
Mod1_2
Mod2
Mod2_1
Mod2_2
Top Top
M1 M2
M11 M12 M21 M22
flattened
hierarchical
The FSMD Coding StyleThe FSMD Coding Style
CU
CU1
CU2
DP
DP1
DP2
Top Top
CU DP
CU1 CU2 DP1 DP2
This design style used for FSMD is the same as we were doing so far in
the class. It is good for small and medium processors
Integrated HDL-Synthesis and Partitioning Integrated HDL-Synthesis and Partitioning MethodologyMethodology
HDL descriptions
Module-basedHDL synthesis
Fine-grainedHDL synthesis
Bit-sliced-based HDL synthesis
Circuit-levelpartitioning
Covering-based partitioning
Bit-sliced-based partitioning
P&R
FPGAs
Placement and
routing
There are three There are three basic synthesis and basic synthesis and
partitioning partitioning methodologiesmethodologies
Module-based HDL SynthesisModule-based HDL Synthesis
Top
M1 M2 Mn
Use, reuse and generate new
types of hierarchical
modules
RAM, ROM, ALU, SHIFTER, COUNTER
We plan modules top to bottom
We build modules bottom to top
Fine-Grained HDL SynthesisFine-Grained HDL Synthesis
Top
M1 M2 Mn
P1 Pm
F1 F2
Clusters
NAND, NOR,
Transistor, Buffer
processes
The concept of process The concept of process is used in VHDL and is used in VHDL and
other languagesother languages
It can be combinational It can be combinational or sequentialor sequential
A Process ExampleA Process Example
Process{P1}input[0:3] i1,i2;input i3;output[0:3] o1;output o2;o1 = i1 + i2;o2 = i1[0] & i3;
i1i2 i3
4
4
+
o1 o2
&
4
P1
o1[0] o1[3]
o2
f1.0 f1.3
f2
o1
Example of a process Example of a process with natural with natural partitioningpartitioning
Functional-based ClusteringFunctional-based Clustering
Design
Module{M1}
Process{P1}
Process{P2}
Module{M2}
Design
M1 M2
P1 P2
f1 f2
Example of a module with Example of a module with partitioning to processespartitioning to processes
Bit-Sliced-Based SynthesisBit-Sliced-Based Synthesis
Mux[0:7] Mux[0:5]Mux
Mux
Adder
[0] [5] [7]
Adder[0:7]
One way of designing an adder with One way of designing an adder with muxes is bit-slice partitioningmuxes is bit-slice partitioning
Space wasted
Functional ClusteringFunctional Clustering
Mux
Mux
Adder
DP[0]
[7]
[5]
[7]
[0]
[0]
DP[0]
DP[7]
DPMux[0]
Mux[0]
Mux[7]
Adder[7]
Adder[0]
These trees show different ways of partitioning or clusteringThese trees show different ways of partitioning or clustering
Partitioning = top down, clustering = bottom upPartitioning = top down, clustering = bottom up
An HDL-based Design FlowAn HDL-based Design Flow
HDL design specification
RTL synthesis
Logic synthesis
Physical synthesis
FPGAsFPGAs
Verification(Simulation)
Verification versus validation versus simulation
Design SpecificationDesign Specification
• HDLs - VHDL and Verilog.
• Why needs an HDL-based design methodology?
• Target Applications.
• Coding Styles.
• Design representation.
• Design entry.
Topics to discussTopics to discuss
Why we need an HDL-based Design Why we need an HDL-based Design MethodologyMethodology
Then NowNow
Schematic capture
Component mapping & may be some logic optimization
Place & route
Layouts
HDL designspecification
Synthesis
Place & route
Layouts
Design complexity
In SOFTWARE : assembly language => high-level language
Target Applications and Layout Target Applications and Layout ArchitecturesArchitectures
• Datapath dominated designs : DSPsDSPs and processors.processors.
• Control dominated designs: controllerscontrollers and communicationcommunication chips.
• Mixed type of designs.
• Bit-sliced stacks.
• Standard cells.
• Macro-cell-based.
• FPGAs.
Layout Layout architecturesarchitectures
applicationsapplications
So many variants. So little time. You must be laborious in industry
HDL Coding Styles versus Design QualityHDL Coding Styles versus Design Quality
HDLspec1
HDLspec2
HDLspec3
Synthesis system
Design1 Design2 Design3
Ideas?
You can concentrate on ideas and use
yours and other people
experience
You can create many variants also for many technologies
Coding Styles and Design RepresentationCoding Styles and Design Representation
• Hierarchical style
• Structural style
• Random style
• FSMD
• Behavioral level
• Logic level
• Gate level
module MUX2(o,i1,i2,sel);output[1:4] o; input[1:4] i1,i2;input sel; reg[1:4] o;always case(sel) 1’b0: o = i1; 1’b1: o = i2; endcaseendmodule
module MUX2(o,i1,i2,sel);output[1:4] o; input[1:4] i1,i2;input sel; assign o[1] = ((sel&i1[1])|(~sel&i2[1])); assign o[2] = ((sel&i1[2])|(~sel&i2[2])); assign o[3] = ((sel&i1[3])|(~sel&i2[3])); assign o[4] = ((sel&i1[4])|(~sel&i2[4]));endmodule
RTL RTL SynthesisSynthesis
• HDL compilation.
• Design representation.
• Component selection.
• Component generation.
• Resource sharing.
34
Register-transfer synthesisRegister-transfer synthesis• Converts FSMD to custom single-purpose processor
– Datapath• Register units to store variables
– Complex data types• Functional units
– Arithmetic operations• Connection units
– Buses, MUXs– FSM controller
• Controls datapath
– Key sub problems:• Allocation
– Instantiate storage, functional, connection units• Binding
– Mapping FSMD operations to specific units
35
Behavioral synthesisBehavioral synthesis• High-level synthesisHigh-level synthesis• Converts single sequential program to single-purpose processor
– Does not require the program to schedule states
• Key sub problemsKey sub problems– Allocation– Binding– Scheduling
• Assign sequential program’s operations to states• Conversion templates
• Optimizations importantOptimizations important– Compiler
• Constant propagation, dead-code elimination, loop unrolling– Advanced techniques for allocation, binding, schedulingallocation, binding, scheduling
• You add registers creating a pipeline
Ideally a totally automated tool with AI Ideally a totally automated tool with AI techniques should go through all good techniques should go through all good
subspaces of the design spacesubspaces of the design space
Three dimensional space of area,
latency and cycle times
3 solutions to Control Data Flow Graph
Concurrent statements
registers
Functional units
40
System synthesisSystem synthesis• Convert 1 or more processes into 1 or more processors (system)
– For complex embedded systems• Multiple processes may provide better performance/power• May be better described using concurrent sequential programs
• TasksTasks– Transformation
• Can merge 2 exclusive processes into 1 process• Can break 1 large process into separate processes• Procedure inlining• Loop unrolling
– Allocation• Essentially design of system architecture
– Select processors to implement processes– Also select memories and busses
We were doing such transformations when we designed:
1. the sorter,
2. sorter absorber
3. and Walsh Transform circuits in our Friday meetings.
41
System synthesis (continued)
• Tasks (cont.)Tasks (cont.)– Partitioning
• Mapping 1 or more processes to 1 or more processors
• Variables among memories
• Communications among buses
– Scheduling• Multiple processes on a single processor
• Memory accesses
• Bus communications
– Tasks performed in variety of orders
– Iteration among tasks common
1. Partitioning for test
2. Partitioning for layout
3. Partitioning to chips
4. Partitioning to boards
42
System synthesis (continued)• Synthesis driven by constraints
– E.g.,• Meet performance requirements at minimum cost
– Allocate as much behavior as possible to general-purpose processor• Low-cost/flexible implementation
– Minimum # of SPPs used to meet performance
• System synthesis for GPP only (software)– Common for decades
• Multiprocessing• Parallel processing• Real-time scheduling
• Hardware/software codesign– Simultaneous consideration of GPPs/SPPs during synthesis– Made possible by maturation of behavioral synthesis in 1990’s
Special Special purpose purpose
processorprocessor
General General purpose purpose
processorprocessor
43
Temporal vs. spatial thinkingTemporal vs. spatial thinking
• Design thought process changed by evolution of synthesis
• Before synthesis– Designers worked primarily in structural domain
• Connecting simpler components to build more complex systems– Connecting logic gates to build controller
– Connecting registers, MUXs, ALUs to build datapath
– “capture and simulate” era• Capture using CAD tools
• Simulate to verify correctness before fabricating
– Spatial thinking• Structural diagrams
• Data sheets
44
Temporal vs. spatialspatial thinking (cont)
• After synthesisAfter synthesis– “describe-and-synthesize” era
– Designers work primarily in behavioral domain
– “describe and synthesize” era• Describe FSMDs or sequential programs
• Synthesize into structure
– Temporal thinking• States or sequential statements have relationship over time
• Strong understanding of hardware structure still important– Behavioral description must synthesize to efficient structural
implementation
45
Verification Verification • Ensuring design is correct and complete
– Correct• Implements specification accurately
– CompleteComplete• Describes appropriate output to all relevant input
• Formal verification– Hard– For small designs or verifying certain key properties only
• Simulation– Most common verification method
46
Formal verificationFormal verification• Analyze design to prove or disprove certain properties
• Correctness example– Prove ALU structural implementation equivalent to behavioral
description• Derive Boolean equations for outputs• Create truth table for equations• Compare to truth table from original behavior
• Completeness exampleCompleteness example– Formally prove elevator door can never open while elevator is
moving• Derive conditions for door being open• Show conditions conflict with conditions for elevator moving
47
SimulationSimulation• Create computer model computer model of your specific designof your specific design
– Provide sample input
– Check for acceptable output
• CorrectnessCorrectness example– ALU
• Provide all possible input combinations
• Check outputs for correct results
• CompletenessCompleteness example– Elevator door closed when moving
• Provide all possible input sequences
• Check door always closed when elevator moving
Simulation part of validation
48
Simulation only “Increases confidence”
• Simulating all possible input sequences impossible for most systemsimpossible for most systems– E.g., 32-bit ALU
• 232 * 232 = 264 possible input combinations• At 1 million combinations/sec• ½ million years to simulate• Sequential circuits even worse
• Can only simulate tiny subsettiny subset of possible inputs– Typical values– Known boundary conditions
• E.g., 32-bit ALU– Both operands all 0’s– Both operands all 1’s
• Increases confidenceIncreases confidence of correctness/completeness• Does not proveDoes not prove
49
Advantages of simulationAdvantages of simulation over physical implementation
• Controllability– Control time
• Stop/start simulation at any time
– Control data values• Inputs or internal values
• Observability– Examine system/environment values at any time
• Debugging– Can stop simulation at any point and:
• Observe internal values
• Modify system/environment values before restarting
– Can step through small intervals (i.e., 500 nanoseconds)
50
DisadvantagesDisadvantages of simulation
• Simulation setup timesetup time– Often has complex external environmentscomplex external environments– Could spend more time modeling environment than system
• Models likely incomplete– Some environment behavior undocumented if complex environment– May not model behavior correctly
• Simulation speed much slower than actual execution– Sequentializing parallel design
• IC: gates operate in parallel• Simulation: analyze inputs, generate outputs for each gate 1 at time
– Several programs added between simulated system and real hardware• 1 simulated operation:
– = 10 to 100 simulator operations– = 100 to 10,000 operating system operations– = 1,000 to 100,000 hardware operations
Vision
speech
robot
51
Simulation speed
• Relative speeds of different types of simulation/emulation– 1 hour actual execution of SOC (system on a chipsystem on a chip)
• = 1.2 years instruction-set simulation
• = 10,000,000 hours gate-level simulation
10,000,000 gate-level HDL simulation
register-transfer-level HDL simulation
cycle-accurate simulation
instruction-set simulation
throughput model
hardware emulation
FPGA 1 day
1 hour
4 days
1
10
100
1000
10000
100,000
1,000,000
IC
1.4 months
1.2 years
12 years
>1 lifetime
1 millennium
52
Overcoming long simulation time
• Reduce amount of real time simulated– 1 msec execution instead of 1 hour
• 0.001sec * 10,000,000 = 10,000 sec = 3 hours
– Reduced confidence• 1 msec of cruise controller operationcruise controller operation tells us little
• Faster simulatorFaster simulator– Emulators
• Special hardware for simulations
– Less precise/accurate simulatorsLess precise/accurate simulators• Exchange speed for observability/controllability
53
Less precise/accurate simulatorsLess precise/accurate simulators
• Don’t need gate-level analysis for all simulations– E.g., cruise control
• Don’t care what happens at every input/output of each logic gate– Simulating RT components ~10x faster– Cycle-basedCycle-based simulation ~100x faster
• Accurate at clock boundaries only• No information on signal changes between boundaries
• Faster simulator often combined with reduction in real time– If willing to simulate for 10 hours
• Use instruction-set simulatorinstruction-set simulator• Real execution time simulated
– 10 hours * 1 / 10,000 (divide by ten thousand)– = 0.001 hour– = 3.6 seconds
54
Hardware/software co-Hardware/software co-simulationsimulation
• VarietyVariety of simulation approaches exist– From very detailed
• E.g., gate-level model
– To very abstract• E.g., instruction-level model
• Simulation tools evolved separately for hardware/software– Recall separate design evolution– Software (GPP) – general purpose
• Typically with instruction-set simulator (ISS = instruction-set simulation)
– Hardware (SPP) - special purpose• Typically with models in HDL environment
• Integration of GPP/SPP on single IC creating need for merging simulation tools
55
Integrating GPP/SPP simulationsIntegrating GPP/SPP simulations
• Simple/naïve way– HDL model of microprocessor
• Runs system software• Much slower than ISS (instruction set simulation)• Less observable/controllable than ISS
– HDL models of SPPs– Integrate all models
• Hardware-software co-simulator– ISS for microprocessor– HDL model for SPPs– Create communication between simulators– Simulators run separately except when transferring data– Faster– Though, frequent communication between ISS and HDL model slows frequent communication between ISS and HDL model slows
it downit down
56
Minimizing communication to speed-up Minimizing communication to speed-up simulationsimulation
• Memory sharedMemory shared between GPP and SPPs– Where should memory go?
– In ISS• HDL simulator must stall for memory access
– In HDL?• ISS must stall when fetching each instruction
• Model memory in both ISS and HDL– Most accesses by each model unrelated to other’s accesses
• No need to communicate these between models
– Co-simulator ensures consistency of shared data
– Huge speedups (100x or more) reported with this techniqueHuge speedups (100x or more) reported with this technique
57
Design process modelDesign process model• Design process model describes order that
design steps are processed– Behavior description step– Behavior to structure conversion step– Mapping structure to physical implementation
step
• Waterfall model– Proceed to next step only after current step
completed
• Spiral model– Proceed through 3 steps in order but with less
detail– Repeat 3 steps gradually increasing detail– Keep repeating until desired system obtained– Becoming extremely popular (hardware &
software development)
Behavioral
Structural
Physical
Waterfall design model
BehavioralStructural
Physical
Spiral design model
58
Waterfall method
• Not very realistic– Bugs often found in later steps that must be fixed in
earlier step• E.g., forgot to handle certain input condition
– Prototype often needed to know complete desired behavior
• E.g, customer adds features after product demo– System specifications commonly change
• E.g., to remain competitive by reducing power, size– Certain features dropped
• Unexpected iterations back through 3 steps cause missed deadlines– Lost revenues– May never make it to market
Behavioral
Structural
Physical
Waterfall design model
59
Spiral method
• First iteration of 3 steps are incomplete
• Much faster, though– End up with prototype
• Use to test basic functions• Get idea of functions to add/remove
– The experience with the original iteration helps in following iterations of 3 steps
• Must come up with ways to obtain structure and physical implementations quickly
– E.g., FPGAs for prototype • silicon for final product
– May have to use more tools• Extra effort/cost
• Could require more time than waterfall method– For instance when correct implementation first time with
waterfall
BehavioralStructural
Physical
Spiral design model
60
General-purpose processorGeneral-purpose processor design models
• Previous slides focused on SPPs
• Can apply equally to GPPs– Waterfall modelWaterfall model
• Structure developed by particular company
• Acquired by embedded system designer
• Designer develops software (behavior)
• Designer maps application to architecture– Compilation
– Manual design
– Spiral-like modelSpiral-like model• Beginning to be applied by embeddedapplied by embedded system designers
61
SpiralSpiral-like model for embedded system designs
• Designer develops or acquires architecture• Develops application(s)• Maps application to architecture• Analyzes design metrics
• Now makes choice– Modify mapping– Modify application(s) to better suit architecture– Modify architecture to better suit application(s)
• Not as difficult now– Maturation of synthesis/compilers– IPs can be tuned (Intellectual Property)
• Continue refining to lower abstraction level until particular implementation chosen
Architecture Application(s)
Mapping
Analysis
Y-chart
How to Deal with Design How to Deal with Design Complexity?Complexity?
• Moore’s Law: Number of transistors that can be packed on a chip doubles every 18 months while the price stays the same.
• Hierarchy: structure of a design at different levels of description
• Abstraction: hiding the lower level details.
Using abstractions in VHLD
In FPGA design you usually do not care about the lowest level but this
may sacrifice the quality of the design, even its realistic realistic
applicabilitityapplicabilitity
Levels of Abstractions & Corresponding Views
Synthesis is more Synthesis is more formalized and abstractformalized and abstract
Such system does not yet Such system does not yet exist as natural language exist as natural language
synthesis is weak and synthesis is weak and limited.limited.
This is similar to all our examples so far from Friday meetingsThis is similar to all our examples so far from Friday meetings
70
EmulatorsEmulators• General physical device system mapped to
– Microprocessor emulatorMicroprocessor emulator• Microprocessor IC with some monitoring, control circuitry
– SPP emulatorSPP emulator• FPGAs (10s to 100s)
• Usually supports debugging tasks
• Created to help solve simulation disadvantages– Mapped Mapped relatively quickly
• Hours, days
– Can be placed in real environmentreal environment• No environment setup time• No incomplete environment
– Typically faster faster than simulation• Hardware implementation
71
Disadvantages of emulators
• Still not as fastnot as fast as real implementations– E.g., emulated cruise-control may not respond fast enough to keep not respond fast enough to keep
control of carcontrol of car
• Mapping still time consumingtime consuming– E.g., mapping complex SOC to 10 FPGAs
• Just partitioning into 10 parts could take weeks
• Can be very expensivevery expensive– Top-of-the-line FPGA-based emulator: $100,000 to $1mill
– Leads to resource bottleneck• Can maybe only afford 1 emulator
• Groups wait days, weeks for other group to finish using
72
Reuse: intellectual Reuse: intellectual property coresproperty cores
• Commercial off-the-shelf (COTSCOTS) components– Predesigned, prepackaged ICs– Implements GPP or SPP– Reduces design/debug time– Have always been available
• System-on-a-chip (SOCSOC)– All components of system implemented on single chip– Made possible by increasing IC capacities– Changing the way COTS components sold
• As intellectual property (IP) rather than actual ICAs intellectual property (IP) rather than actual IC– Behavioral, structural, or physical descriptions– Processor-level components known as cores
• SOC built by integrating multiple descriptions
73
What types of Cores can we purchase?What types of Cores can we purchase?
• Soft core– Synthesizable behavioral
description
– Typically written in HDL (VHDL/Verilog)
• Firm core– Structural description
– Typically provided in HDL
• Hard core– Physical description
– Provided in variety of physical layout file formats
Behavior
Physical
Structural
Processors, memories
Registers, FUs, MUXs
Gates, flip-flops
Transistors
Sequential programs
Register transfers
Logic equations/FSM
Transfer functions
Cell Layout
Modules
Chips
Boards
Gajski’s Y-chart
74
Advantages/disadvantages of hard core
• Ease of use– Developer already designed and tested core
• Can use right away
• Can expect to work correctly
• Predictability– Size, power, performance predicted accurately
• Not easily mapped (retargeted) to different process– E.g., core available for vendor X’s 0.25 micrometer CMOS process
• Can’t use with vendor X’s 0.18 micrometer process
• Can’t use with vendor Y
75
Advantages/disadvantages of soft/firm cores
• Soft coresSoft cores– Can be synthesized to nearly any technology– Can optimize for particular use
• E.g., delete unused portion of core– Lower power, smaller designs
– Requires more design effort– May not work in technology not tested for– Not as optimized as hard core for same processor
• Firm coresFirm cores– Compromise between hard and soft cores
• Some retargetability• Limited optimization• Better predictability/ease of use
76
New challenges to processor providers related to wide use of cores
• Cores have dramatically changed business model
– Pricing modelsPricing models• Past
– Vendors sold product as IC to designers– Designers must buy any additional copies
• Could not (economically) copy from original
• Today– Vendors can sell as IP– Designers can make as many copies as needed
• Vendor can use different pricing models– Royalty-based model
• Similar to old IC model• Designer pays for each additional model
– Fixed price model• One price for IP and as many copies as neededOne price for IP and as many copies as needed
– Many other models used
77
IP protectionIP protection• Past
– Illegally copying IC very difficult• Reverse engineering required tremendous, deliberate effort• “Accidental” copying not possible
• Today– Cores sold in electronic format
• Deliberate/accidental unauthorized copying easier• Safeguards greatly increased• Contracts to ensure no copying/distributing• Encryption techniques
– limit actual exposure to IP
• Watermarking Watermarking – determines if particular instance of processor was copied– whether copy authorized
78
New challenges to processor users with respect to use of cores
• Licensing arrangements– Not as easy as purchasing IC– More contracts enforcing pricing model and IP protection
• Possibly requiring legal assistance
• Extra design effort– Especially for soft cores
• Must still be synthesized and tested• Minor differences in synthesis tools can cause problems
• Verification requirements are more difficult– Extensive testing for synthesized soft cores and soft/firm cores mapped to particular
technology• Ensure correct synthesis• Timing and power vary between implementations
– Early verification is critical• Cores buried within IC• Cannot simply replace bad core
79
Summary on design technologies and methodologies
• Design technology seeks to reduce gap between IC capacity growth and designer productivity growth
• Synthesis has changed digital design
• Increased IC capacity means sw/hw components coexist on one chip
• Design paradigm shift to core-based design
• Simulation essential but hard
• Spiral design process is popular
80
Questions for the midterm• Embedded systems are common and growing
– Such systems are very different from in the past due to increased IC capacities and automation tools – Indicator: National Science Foundation just created a separate program on Embedded Systems (2002).
• Give examples and describe design methodologies and technologies for them.• New view at synthesis:
– Embedded computing systems are built from a collection of processors, some general-purpose (sw), some single-purpose (hw)
– Hw/sw differ in design metrics, not in some fundamental way– Memory and interfaces necessary to complete system– Days of embedded system design as assembly-level programming of one microprocessor are fading
away
• Propose the complete design methodology for some selected narrow application but very fast time to market , such as robot toys.
• Need to focus on higher-level issues – State machines, concurrent processes, control systems– IC technologies, design technologies
• There’s a growing, challenging and exciting world of embedded systems design out there. There’s also much more to learn.
• Enjoy learning for midterm!Enjoy learning for midterm!
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Sources of Slides
Embedded Systems Design: A Unified Hardware/Software Introduction, (c)
2000 Vahid/Givargis
• Dr. Aiman H. El-Maleh• Computer Engineering Department• King Fahd University of Petroleum & Minerals
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