ece680: physical vlsi designqli/ece680/chapter7 timing issue.pdf600 mhz – 0.35 micron cmos t cycle...

ECE680: Physical VLSI DesignECE680: Physical VLSI DesignECE680: Physical VLSI DesignECE680: Physical VLSI Design

Chapter VIIChapter VII

Timing Issues in Digital CircuitsTiming Issues in Digital Circuits

(chapter 10 in textbook)(chapter 10 in textbook)

GMU, ECE 680 Physical VLSI Design 1

Synchronous TimingSynchronous Timing

(Fig 10‐1)

(Fig. 10‐1)

CombinationalLogic

R1 R2Cin Cout Out

T > t + t + tT > tc ‐ q + tlogic + tsu

thold < tc – q, cd + tlogic, cd

hold c q, cd logic, cd

Timing DefinitionshLatch Parameters

Clk PW

D thold

PWm tsu

Q tc-q td-q

Delays can be different for rising and falling data transitionsGMU, ECE 680 Physical VLSI Design 3

Register ParametersRegister Parameters

D thold

Q tc-q

Delays can be different for rising and falling data transitionsGMU, ECE 680 Physical VLSI Design 4

Clock UncertaintiesClock Uncertainties

4 Power Supply

Power Supply

Interconnect6 Capacitive Load

Devices

5 Temperature7 Coupling to Adjacent Lines

1 Clock Generation

Sources of clock uncertainty

Clock NonidealitiesClock Nonidealities

• Clock skew– Spatial variation in temporally equivalent clock edges; deterministic + random, tSK

Cl k jitt• Clock jitter– Temporal variations in consecutive edges of the clock signal; modulation + random noiseg ;

– Cycle‐to‐cycle (short‐term) tJS– Long term tJL

• Variation of the pulse width – Important for level sensitive clocking

Clock Skew and JitterClock Skew and Jitter

ClkClktSK

Clk tJS

• Both skew and jitter affect the effective cycle time

• Only skew affects the race margin

Tclk + δ – 2tjitter > tc ‐ q + tlogic + tsu

δ 2t t t t

δ + 2tjitter + thold < tc – q, cd + tlogic, cd

Clock SkewClock Skew

# of registersg

Earliest occurrenceof Clk edge

Latest occurrenceof Clk edgeg

Nominal – /2g

Nominal + /2

Clk delayInsertion delayMax Clk skew

Positive and Negative SkewPositive and Negative Skew

R1 R2 R3R1In Combinational

LogicD Q

tCLK1CLK tCLK2

R2D Q Combinational

R3• • •D Q

(a) Positive skew

delay delay

R1In Combinational

LogicD QR2D Q Combinational

R3• • •D Q

(b) Negative skew

tCLK2 tCLK3

delay CLK

Positive SkewPositive Skew

CLK1TCLK

1 3CLK1

Launching edge arrives before the receiving edge

Negative SkewNegative Skew

TCLK +

1 3CLK1 1 3

Receiving edge arrives before the launching edge

Timing ConstraintsTiming Constraints

R1 R2R1D Q Combinational

LogicIn

tCLK tCLK1 tCLK2

tc qtc q, cd

tlogictlogic, cdq

tsu, tholdg

Minimum cycle time:T T ‐ = tc‐q + tsu + tlogic

Worst case is when receiving edge arrives early (positive )

Timing ConstraintsTiming ConstraintsR1

CombinationalInR2

D Q CombinationalLogic

CLK tCLK1

tc qtc q, cdtsu, thold

tlogictlogic, cd

su, hold

Hold time constraint:t(c‐q, cd) + t(logic, cd) > thold +

Worst case is when receiving edge arrives lateRace between data and clock

Impact of JitterImpact of Jitter

CLK-tji tter

t j itter

tji tter

ICombinationalREGS

In Logic

tc-q , tc-q, cdt log ict l i dq q, log ic, cdtsu, thold

tjitter

Longest Logic Path in Edge‐Triggered Systems

ClkTSU

TClk-Q TLM

Latest point of launching

Earliest arrivalf lof launching of next cycle

Clock Constraints in Edge‐Triggered Systems

If launching edge is late and receiving edge is early the data will not be too late if:If launching edge is late and receiving edge is early, the data will not be too late if:

T + T + T < T T T Tc-q + TLM + TSU < T – TJI,1 – TJI,2 -

Minimum cycle time is determined by the maximum delays through the logic

2Tc-q + TLM + TSU + + 2 TJI < T

Skew can be either positive or negativeSkew can be either positive or negativeGMU, ECE 680 Physical VLSI Design 16

Shortest PathShortest Path

E li t i t

Earliest point of launching

TClk-Q TLm

ClkClkTH

Data must not arrivebefore this timeNominal

clock edge Example 10.1

Clock Constraints in Edge‐Triggered Systems

If launching edge is early and receiving edge is late:

T + TLM – TJI 1 < TH + TJI 2 + Minimum logic delay

Tc-q + TLM TJI,1 < TH + TJI,2 +

Tc-q + TLM < TH + 2TJI+

Tclk + δ – 2tjitter > tc ‐ q + tlogic + tsu

How to counter Clock Skew?

Negative Skew

EG EG log O t

log Out

InPositive Skew

Clock Distribution

Positive Skew

Data and Clock Routing

Flip‐Flop – Based TimingFlip Flop Based Timing

Flip-flopSkew

p opdelayLogic delay

TFlip-flop

TSUTClk-Q

Representation after i S Ci i 996

Tclk + δ – 2tjitter > tc ‐ q + tlogic + tsuM. Horowitz, VLSI Circuits 1996.

clk jitter c q logic su

Flip‐Flops and Dynamic LogicFlip Flops and Dynamic LogicLogic delay

TSUTClk-Q

Logic delayP hPrechargeEvaluateEvaluatePrecharge

Flip‐flops are used only with static logicp p y g

Latch timingLatch timing

tD-QWhen data arrives

to transparent latch

Latch is a ‘soft’ barrierD

tClk-Q When data arrives to closed latch

Data has to be ‘re-launched’

Single‐Phase Clock with LatchesSingle Phase Clock with Latches

Tskl Tskl TsktTskt

Latch‐Based DesignLatch Based DesignL1 latch is transparentwhen = 0

L2 latch is transparent when = 1

when = 0 when = 1

L1L t h Logic L2

L t hLatch g Latch

Slack‐borrowingSlack borrowing

In CLB AL1 L2 L1

CLB BQDIn CLB_A QD QD

CLB_Btpd,A tpd,Ba b c d e

CLK1 CLK2 CLK1

a valid b val id

tDQ tpd,B

c valid d valid

tDQe valid

slack passed to next stage

Latch‐Based TimingLatch Based TimingSkew

Static logic

L2 latchL1

Latch Logic L2Latch

L1 latch

Logic Longpath

Can tolerate skew!

Shortpathpath

Clock Distribution

H-tree

Clock is distributed in a tree-like fashion

More realistic H‐treeMore realistic H tree

[Restle98][Restle98]

The Grid SystemThe Grid System

Driver

DriverD

GCLK GCLK

•No rc-matching•Large power

Driver

Example: DEC Alpha 21164

Clock Frequency: 300 MHz - 9.3 Million Transistors

Total Clock Load: 3.75 nF

Power in Clock Distribution network : 20 W (out of 50)( )

Uses Two Level Clock Distribution:

Si l 6 t d i t t f hi• Single 6-stage driver at center of chip• Secondary buffers drive left and right side

clock grid in Metal3 and Metal4clock grid in Metal3 and Metal4Total driver size: 58 cm!

21164 Clocking21164 Clocking

• 2 phase single wire clock, di ib d l b ll

tcycle= 3.3ns

distributed globally

• 2 distributed driver channels– Reduced RC delay/skew

trise = 0.35ns tskew = 150ps

Clock waveform

– Improved thermal distribution

– 3.75nF clock load

– 58 cm final driver width

final drivers

• Local inverters for latching

• Conditional clocks in caches to reduce powerreduce power

• More complex race checking

• Device variationLocation of clock

pre‐driver

Location of clockdriver on die

Clock Drivers

Clock Skew in Alpha Processorp

EV6 (Alpha 21264) ClockingEV6 (Alpha 21264) Clocking600 MHz600 MHz –– 0.35 micron CMOS0.35 micron CMOS

tcycle= 1.67ns

600 MHz 600 MHz 0.35 micron CMOS0.35 micron CMOS

trise = 0.35ns tskew = 50psGlobal clock waveform

• 2 Phase, with multiple conditional buffered clocks

– 2.8 nF clock load

– 40 cm final driver width

• Local clocks can be gated “off” to save power

• Reduced load/skew

• Reduced thermal issues

• Multiple clocks complicate raceMultiple clocks complicate race checkingPLL

21264 Clocking21264 Clocking

EV6 Clock ResultsEV6 Clock Resultsps5

101520

30531031520

253035

32032533035

330335340

GCLK Skew

50 345

GCLK Rise Times(at Vdd/2 Crossings) (20% to 80% Extrapolated to 0% to 100%)

EV7 Clock HierarchyEV7 Clock HierarchyActive Skew Management and Multiple Clock Domains

NCLK(Mem Ctrl)

+ widely dispersed drivers

+ DLLs compensate static and low‐frequency

q yvariation

+ divides design and ifi ti ff t

verification effort

- DLL design and verification is added

GCLK(CPU Core)L2

SYSCLK

+ tailored clocksSYSCLK

Self-timed and Asynchronous DesignSelf timed and Asynchronous DesignFunctions of clock in synchronous design

1) Acts as completion signal

2) Ensures the correct ordering of events

Truly asynchronous design

1) Completion is ensured by careful timing analysis

2) Ordering of events is implicit in logic

1) Completion is ensured by careful timing analysis

Self‐timed designSelf timed design

1) Completion ensured by completion signal2) Ordering imposed by handshaking protocol

Synchronous Pipelined DatapathSynchronous Pipelined Datapath

QLogic

Block #1 DR2

QLogic

Block #2 DR3

QLogic

Block #3

tpd,reg tpd1CLK tpd2 tpd3

Advantages: Easy to integrate

disadvantages: Frequency assume the worst case of logicy g Frequency assume the worst case of logic

Self‐Timed Pipelined DatapathSelf Timed Pipelined Datapath

Req Req Req Req

St t DSt t D St t D

Req Req Req Req

Ack Ack Ack ACKHS HS HS

Start DoneStart Done Start Done

R2 OutF2In

R1 F1 R3 F3

tpF2tpF1 tpF3

Completion Signal GenerationCompletion Signal Generation

NETWORKIn Out

DELAY MODULEStart Done

Using Delay Element (e.g. in memories)

Completion Signal GenerationCompletion Signal Generation

Using Redundant Signal Encoding

Completion Signal in DCVSLCompletion Signal in DCVSLVDD VDD

Start DoneB0

PDN PDNIn1In2In2

Self‐Timed AdderSelf Timed Adder

P P P P

StartVDD

Start DoneP0

C0 C1 C2 C3 C4 C4 C4

St tStart

C4C0 C1 C2 C3 C4 (b) Completion signal

(a) Differential carry generation

Completion Signal Using Current Sensingp g g g

Inputs Static CMOS LogicReg

Output tdelay

StartGNDsense

Current Sensor

toverlap

Min Delay Generator

tpd-NOR

Output valid

Hand‐Shaking ProtocolHand Shaking Protocol

ReqReq

3RECEIVERSENDER

11Data(a) Sender-receiver configuration

(b) Ti i di

cycle 1 cycle 2Sender’s actionReceiver’s action

(b) Timing diagramTwo Phase Handshake

Event Logic – The Muller‐C ElementgA B Fn1

0 0 0F

(b) Truth table(a) Schematic

VDD VDDVDD

(a) Logic

(b) Majority Function

(c) DynamicGMU, ECE 680 Physical VLSI Design 47

2-Phase Handshake Protocol2 Phase Handshake Protocol

Sender Recei erDataSenderlogic

Receiverlogic

Data ready Data accepted

Handshake logic

Advantage : FAST - minimal # of signaling events (important for global interconnect)Disadvantage : edge - sensitive, has state

Example: Self-timed FIFOExample: Self timed FIFO

R1In Out

EnReqi

Acki Acko

All 1s or 0s -> pipeline emptyAlternating 1s and 0s -> pipeline full

2‐Phase Protocol2 Phase Protocol

ExampleExample

From [Horowitz]

ExampleExample

4-Phase Handshake Protocol4 Phase Handshake Protocol

2 4Req

Sender’s action

Receiver’s action

3 5Ack

1 1Data

Cycle 1 Cycle 2

Slower, but unambiguous

Also known as RTZ

4-Phase Handshake Protocol4 Phase Handshake ProtocolImplementation using Muller‐C elements

Senderlogic

Receiverlogic

Data ready Data accepted

Handshake logic

Self‐Resetting LogicSelf Resetting Logic

PrechargedLogic Block

completiondetection

(L1) (L2) (L3)

VDDVDD

Post‐charge

intout

Clock‐Delayed DominoClock Delayed DominoGND

CLK1 CLK2 (to next stage)

Pulldown

Q1 (also D2)

PulldownNetwork

Asynchronous‐Synchronous Interfacey y

Asynchronoussystem

Synchronous system

Synchronization

Synchronizers and ArbitersSynchronizers and Arbiters

• Arbiter: Circuit to decide which of 2 events occurred first

• Synchronizer: Arbiter with clock as one of the inputs

• Problem: Circuit HAS to make a decision in limited time which decision is not importanttime ‐ which decision is not important

• Caveat: It is impossible to ensure correct operation• But we can decrease the error probability at theBut, we can decrease the error probability at the expense of delay

A Simple SynchronizerA Simple Synchronizer

int I1D Q

• Data sampled on rising edge of the clock

• Latch will eventually resolve the signal value• Latch will eventually resolve the signal value,but ... this might take infinite time!

Synchronizer: Output TrajectoriesSynchronizer: Output Trajectories

Si l l d l f fli fl

0.00 100 200 300

time [ps]

Single-pole model for a flip-flop

Mean Time to FailureMean Time to Failure

ExampleExampleTf = 10 nsec = TT 50Tsignal = 50 nsectr = 1 nsect = 310 psect = 310 psecVIH - VIL = 1 V (VDD = 5 V)

N(T) = 3.9 10-9 errors/secN(T) 3.9 10 errors/secMTF (T) = 2.6 108 sec = 8.3 yearsMTF (0) = 2.5 sec

Influence of NoiseInfluence of NoiseUniform distributionaround VM

p(v)around VM

logarithmic d ti

Treduction

0 VIL VIH Still UniformInitial Distribution

Still Uniform

Low amplitude noise does not influence synchronization behaviorp y

Typical SynchronizersTypical Synchronizers2

2 phase clocking circuit

Using dela lineUsing delay line

Cascaded Synchronizers Reduce MTFCascaded Synchronizers Reduce MTF

S S SIn O1 O2 Out

Sync Sync Sync

ArbitersArbiters

Req1 Ack1Req1

Ack2Arbiter

Req2Ack1

(a) Schematic symbol

(b) l iR 1 (b) ImplementationReq1

A (c) Timing diagramVT gap

BAck1 t

( ) g g

metastable

PLL‐Based SynchronizationPLL Based Synchronization

Chip 1 Chip 2

DigitalS t

Chip 1

DigitalSystem

Chip 2

System

Divider

System

PLLfsystem = N x fcrystal

referenceclock

fcrystal 200<Mhz

ClockBuffer

CrystalOscillator

fcrystal 200 Mhz

PLL Block DiagramPLL Block Diagram

Phasedetector

Chargepump

Loopfilter VCO

Referenceclock

Upvcont

Divide by

Localclock

Divide byN

SystemClock

Phase DetectorPhase Detector

Output before filtering

reflocalclock

Output

localclock

Output

Output (Low pass filtered)(a) (b)

Output (Low pass filtered)

Transfercharacteristic

180 90 90 180 phase error (deg)-180 -90 90 180 phase error (deg)(c)GMU, ECE 680 Physical VLSI Design 71

Phase‐Frequency DetectorPhase Frequency Detector

D QRst UP

UP = 0DN = 1

UP = 0DN = 0

UP = 1DN = 0 A

(a) schematic (b) state transition diagram

(c) Timing waveforms

PFD Response to FrequencyPFD Response to Frequency

PFD Phase Transfer CharacteristicPFD Phase Transfer Characteristic

Average (UP-DN)

phase error (deg)2

Charge PumpCharge PumpVDD

UP To VCO Control Input

PLL SimulationPLL Simulation

1 2 3 4 5Time ( s)

Clock Generation using DLLsClock Generation using DLLs

Delay‐Locked Loop (Delay Line Based)

Phase ChargeDL

Det PumpFilter

Phase‐Locked Loop (VCO‐Based)

PD CP VCO÷N

Filter

Delay Locked LoopDelay Locked Loop

Phase Charge VCDLFREF

UC VPhase

detectChargepump VCDLPH D

C VCTRL

(c)GMU, ECE 680 Physical VLSI Design 78

DLL‐Based Clock DistributionDLL Based Clock Distribution

VCDL DigitalCi it晻�VCDL

Circuit晻�

PhaseDetector

VCDL DigitalCircuit晻�GLOBAL CLK

PhaseDetector

ece680: physical vlsi designqli/ece680/chapter7 timing issue.pdf600 mhz – 0.35 micron cmos t cycle...

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