integer multipliers - concordia university

Integer Multipliers

Multipliers

• A must have circuit in most DSP applications

• A variety of multipliers exists that can be chosen

based on their performance

• Serial, Serial/Parallel,Shift and Add, Array, Booth,

Wallace Tree,….

multiplier

converter

Converter

converter

Multiplication Algorithm

Yn-1X0 Yn-2X0 Yn-3X0 …… Y1X0 Y0X0

Yn-1X1 Yn-2X1 Yn-3X1 …… Y1X1 Y0X1

Yn-1X2 Yn-2X2 Yn-3X2 …… Y1X2 Y0X2

… … … …

…. …. …. …. ….

Yn-1Xn-2 Yn-2X0 n-2 Yn-3X n-2 …… Y1Xn-2 Y0Xn-2

Yn-1Xn-1 Yn-2X0n-1 Yn-3Xn-1 …… Y1Xn-1 Y0Xn-1

-----------------------------------------------------------------------------------------------------------------------------------------

P2n-1 P2n-2 P2n-3 P2 P1 P0

X= Xn-1 Xn-2 ………..……X0 Multiplicand

Y=Yn-1 Yn-2……………….Y0 Multiplier

1. Multiplication AlgorithmsImplementation of multiplication of binary numbers boils down to how to do the additions.

Consider the two 8 bit numbers A and B to generate the 16 bit product P. First generate the 64

partial Products and then add them up.

MU( Multiplier Unit)

Control Unit

Storage

Multiplier DesignXA

Serial Register

Reset=0

CLK CLK/(N+1)

X: x3x2x1x0 Y:y 3y2y1y0

Input Sequence for G1:

00x3x2x1x00 x3x2x1x0 0x3x2x1x0 0x3x2x1x0

00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0

Reset:010000100001000010000

Serial Multiplier

Serial Register

Reset=0

CLK CLK/(N+1)

Si: the ith bit of the final result

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=1

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Ci: the only carry from column i

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Sij: the jth partial sum for column i

Cij: the jth partial carry from column i

Reset:010000100001000010000

S20 0S

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=1

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=1

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=1

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial Register

Reset=0

CLK CLK/(N+1)

Reset:010000100001000010000

Serial / Parallel

Multiplier

8 bit Adder

INPUT Ain (7 downto 0)

Result (7 downto 0)Result (15 downto 8)

INPUT Bin (7 downto 0)

REGBREGC

Shift AND Add Multiplier X

Synchronous Shift and Add Multiplier

controller

Multiplication process:

5 states: Idle, Init, Test, Add, and Shift&Count.

Idle: Starts by receiving the Start signal;

Init: Multiplicand and multiplier are loaded into a load

register and a shift register, respectively;

Test: The LSB in the shift register which contains the

multiplier is tested to decide the next state;

Synchronous Shift and Add Multiplier ControllerDesign

Add: If LSB is ‘1’, then next state is to add the new partial product to the

accumulation result, and the state machine transits to shift&count state ;

Shift&Count: If LSB is ‘0’, then the two shift register shift their contains

one bit right, and the counter counts up by one step. After that, the state

machine transits back to test state;

When the counter reaches to N , a Stop signal is asserted and the state

machine goes to the idle state;

Idle: In the idle state, a Done signal is asserted to indicate the end of

multiplication.

Multiplicand

n-bit AdderShift and Add

Control Logic

An ...C

Multiplier

Qn ...

Shift Right

n-bit Multiplier:

Q0=1: Multiplicand is added to register A; the result is stored in register A; registers C, A, Q are shifted to the right

one bit

Q0=0: Registers C, A, Q are shifted to the right one bit

4-bit AdderShift and Add

Control Logic

Multiplier

Shift Right

Multiplicand

1 0 1 1

0 000 1 101

Example: 4-bit Multiplier

Initial Values XA

Control Logic

Multiplier

Shift Right=0

Multiplicand

1 0 1 1

1 110 1 101

First Cycle--Add

Control Logic

Multiplier

Shift Right=1

Multiplicand

1 0 1 1

0 101 1 011

First Cycle--Shift XA

Control Logic

Multiplier

Shift Right=1

Multiplicand

1 0 1 1

1 1110 010

Second Cycle--Shift

Control Logic

Multiplier

Shift Right=0

Multiplicand

1 0 1 1

1 101 1 111

Third Cycle--Add XA

Control Logic

Multiplier

Shift Right=1

Multiplicand

1 0 1 1

0 011 1 111

Third Cycle--Shift

Control Logic

Multiplier

Shift Right=0

Multiplicand

1 0 1 1

0 100 1 111

Fourth Cycle--Add

Control Logic

Multiplier

Shift Right=1

Multiplicand

1 0 1 1

1 000 1 111

Fourth Cycle--Shift

4*4 Synchronous Shift and Add Multiplier DesignLayout Design

Floor plan of the 4*4 Synchronous

Shift and Add Multiplier

Comparison between Synchronous and Asynchronous

Approaches

Example : (simulated by Ovais Ahmed)

Multiplicand = 100010012 = 8916

Multiplier = 101010112 = AB16

Expected Result = 1011011100000112 =5B8316

Regular structure based on add and shift algorithm.

Addition is mainly done by carry save algorithm.

Sign bit extension results in a higher capacitive load and

slows down the speed of the circuit.

Array MultiplierX

Addition with CLA

Four-bit Adder

Product (A*B)

A = a3a

B = b3b

Array Multiplier with CSA

Total of 16

**Pij =A

Critical Path with Array Multipliers

HAFAFA FA

Two of the possible paths for the Ripple-Carry based 4*4 Multiplier

Area = (N*N) AND Gate + (N-1)N Full-Adder

Delay = τ HA + (2N-1) τFA

Wallace Tree

Array Multiplier + Wallace Tree

599/25/2017 Concordia VLSI Lab 59

Convert negative partial products to positive representation

• No sign-extension required

)2*2*(*)2*2*(*2

k yyxxYX

kkk xyyxyxyx

2211 2*2*)2*2**(

Baugh-Wooley Algorithm

examples of 5-by-5 Baugh-Wooley

FAFA FA FA

FAFA FA FA FAFA

a4b0' a3b0a1b0a2b0 a0b0

P9 P8 P7 P6 P5 P4 P3 P2 P1

a3b1 a2b1a1b1

a0b2a3b2 a2b2 a1b2

a4' b4'

a0b3a3b3 a2b3 a1b3

a0'b4a4b4

a3'b4 a2'b4 a1'b4

The schematic logic circuit diagram of a 5-by-5 Baugh-Wooley two’s complement array multiplier

a7 a6 a5 a4 a3 a2 a1 a0

* a7 a6 a5 a4 a3 a2 a1 a0

--------

-------

------

--------

-------

------

--------

-------

------

--------

-------

------

--------

-------

------

--------

-------

------

--------

a7*a0 a6*a0

0 a4*a0

0 a2*a0

0 a0*a0

1 a6*a1 a5*a1

1 a3*a1

1 a1*a1

2 a5*a2 a4*a2

2 a2*a2

2 a0*a2

a7*a3 a6*a3

3 a4*a3 a3*a3

3 a1*a3

4 a6*a4 a5*a4

4 a3*a4 a2*a4

4 a0*a4

5 a5*a5 a4*a5

5 a2*a5 a1*a5

6 a6*a6

6 a4*a6 a3*a6

6 a1*a6 a0*a6

7 a5*a7

7 a3*a7 a2*a7

7 a0*a7

--------

-------

------

--------

-------

------

--------

-------

------

--------

-------

------

--------

-------

------

--------

-------

------

--------

5 a7*a4

3 a7*a2 a7*a1

0 a6*a0 a5*a0

0 a3*a0

0 a1*a0 ‘0' a0

Squarer using Baugh-Wooley Algorithm

a1a0a1

‘0’

a4a2a6a0

a5a2a7a0

a5a3a7a1

a2a3a0‘0’ a0

‘0’a3a3a4

a5a4a7a2

a6a7a4

S0S1S2S4S5S6S7S8S9S10S11S12S13S14S15 S3

Example of an 8bit squarerX

Array Multiplier

32bits by 32bits multiplier

Booth (Radix-4) Multiplier

Radix-4 (3 bit recoding) reduces number of partial products to be

added by half.

Great saving in area and increased speed.

A = -an-12n-1 + an-22

n-2 + an-32n-3 + …. + a12 + a0

B = -bn-12n-1 + bn-22

n-2 + bn-32n-3 + …. + b12 + b0

· Base 4 redundant sign digit representation of B is

(n/2) - 1

B = 22i Kii = 0

Ki is calculated by following equation

Ki = -2b2i+1 + b2i + b2i-1 i = 0,1,2,….(n-2)/2

3 bits of Multiplier B, b2i+1, b2i, b2i-1, are examined and

corresponding Ki is calculated.

B is always appended on the right with zero (b-1 = 0), and n is

always even (B is sign extended if needed).

The product AB is then obtained by adding n/2 partial products.

(n/2) - 1

AB = P = 22i Ki Ai = 0

Booth Algorithm

Decoding of multiplier to generate signals for hardware use

Xi+1 Xi Xi-1 OP NEG ZERO TWO

0 0 0 0 0 1 0

1 0 0 2 1 0 1

0 1 0 1 0 0 0

1 1 0 1 1 0 0

0 0 1 1 0 0 0

1 0 1 1 1 0 0

0 1 1 2 0 0 1

1 1 1 0 1 1 0

Booth Algorithm

A Booth recoded multiplier examines

Three bits of the multiplicand at a time

It determine whether to add zero, 1, -1, 2, or -2 of that rank of

the multiplicand.

The operation to be performed is based on the current two bits

of the multiplicand and the previous bitXi+1 X Xi-1 Zi/2

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 2

1 0 0 -2

1 0 1 -1

1 1 0 -1

1 1 1 0

BIT M is

21 20 2-1OPERATION

multiplied

Xi Xi+1 Xi+2

0 0 0 add zero (no string) +0

0 0 1 add multipleic (end of string) +X

0 1 0 add multiplic. (a string) +X

0 1 1 add twice the mul. (end of string) +2X

1 0 0 sub. twice the m. (beg. of string) -2X

1 0 1 sub. the m. (-2X and +X) -X

1 1 0 sub . the m. (beg. of string) -X

1 1 1 sub. zero (center of string) -0

Booth Algorithm- dot notation

Multiplicand A = ● ● ● ●Multiplier B = (●●)(●●)

Partial product bits ● ● ● ● (B1B0)2A40

Partial product bits ● ● ● ● (B3B2)A41

Product P = ● ● ● ● ● ● ● ●

The following example is used to show how the calculation is done properly.

Multiplicand X = 000011

Multiplier Y = 011101 0 1 1 1 0 1 0

After booth decoding, Y is decoded as to multiply X by +2, -1, +1 separately, then shift the partial

product two bits and add them together.

X* +1 000000000011

X* -1 1111111101

X* +2 00000110

--------------------------------------------

000001010111

Example

Added to

multiplier

Sign Extension

Sign extension

Traditional sign-extension scheme

• Segment the input operands based on the size of

embedded blocks

• Multiply the segmented inputs and extend the sign bit of

each partial products

• Sum all partial products

Segmented input

operands

Sign extension

Final result

partial

products

Booth Algorithm-Example 1

Example 1:

011101 (+29)

000011 (+3)

+2 -1 +1

000000000011111111110100000110

0000010101111 (+87)

Booth Algorithm Example 2

011101 (+29)

111101 (-3)

+2 -1 +1

111111111101000000001111111010

1111101010011

2s complement of

multiplicand

Notice sign

extensions

Booth Algorithm-Example 3

100011 (-29)

111101 (-3)

-2 +1 -1

000000000011111111110100000110

0000010101111

Shifted 2s

complement

Notice the sign

extensions

Comparison of Booth and parallel

multiplier shift and Add

Please note that each operand is 17 bit ie. the 17th bit is the sign bit. Also

negative numbers are entered as 1’s complement, this is why you need to

add the S in the right hand side of the diagram. If you use 2’complement

then the S’s on right side of the diagram can be removed

Template to reduce sign extensions for Booth

Algorithm

Comparison of Template and the sign

extension

Sign template Sign extension

Using the Template 25 * -35

Sign bit

0 0 0 1 1 0 0 1

Add SS 1 1 0 1 1 1 0 1 0

Add inverted S

Add Inverted sign and add 1

1 0 0 0 0 0 1 1 0 0 1 * 1

Add Inverted sign bit 1 0 1 1 1 0 0 1 1 1 * -1

1 0 0 1 1 0 0 1 0 * 2

No sign bit 1 1 0 0 1 1 1 * -1

1 1 1 1 0 0 1 0 0 1 0 1 0 1

This is a –ve number. Convert it

0 0 0 0 1 1 0 1 1 0 1 0 1 1

512 256 64 32 8 2 1 = 875

Example of using the template25 * - 35 with -35 as the multiplier. Using 8 bit representation

Booth Multiplier Components

Multiplier

Multiplicand

Booth Encoder

PPU (Partial products unit)

PPA(Partial products adding unit)

Product

+ + + + + + + + + + +

+ + + + + + + + +

P0P1P2P3P4P5P6P7P8P9P10P11P12P13P14P15P16

+++++++++++++++

+ + + + + + +

+ + + + +

Partial Product PP0,PP1,PP2(15 downto 0)

Partial Product PP3(15 downto 0)

Ripple Carry Adder

Critical Path

Pipeline Register

+ + + + + + + + + + +

+ + + + + + + + +

P0P1P2P3P4P5P6P7P8P9P10P11P12P13P14P15P16

+++++++++++++++

+ + + + + + +

+ + + + +

Partial Product PP0,PP1,PP2(15 downto 0)

Partial Product PP3(15 downto 0)

Ripple Carry Adder

Critical Path

Pipeline Register

Wallace Tree and Ripple Carry Adder Structure.

Of 8*8 multiplier With PipelineX

Mulbegin

Mulend

FSMCLR

Q16 32

reg_2left32

B 37Y 37

D 37 Q 37

CLRRegister37

FinishCLK

CLRCounter20

StartMulbegin

Doubleshift

QA(0-2)

Doubleshift

Mulend

CLK Finish

Result

not used

Mulend

Q16 17

reg2right17

=0; A16=0

=1, A16=1

endcheck

complement

Q16 32

reg_2left32

Q16 32

reg_2left32

*2 (shifter)

mux4-32

Mul11 Mul12

expansion

Hardware implementation of

Booth with shift and addX

Simulation PlanX

32-bit Signal

Generator A

32-bit Signal

Generator B

Behavioral Multiplier

64-bit

Comparator

A[31:0]

Result

Failed

Number

P[63:0]

B[31:0]

My_P[63:0]

My Multiplier

Array MultiplierModified Booth

Multiplier

Wallace Tree

Multiplier

Modified Booth-

Wallace Tree

Multiplier

Twin Pipe

Serial-Parallel

Multiplier

Testing the DesignX

Simulation For Parallel MultipliersXA

Signed

Number:

Unsigned

Number:

Simulation For Signed S/P MultipliersX

There are 340 ns

delay between the

result and the

operators because

of the D flip-flops

delay.

FPGA after implementation, areas of

programming shown clearlyX

Another implementation of the above after pipelining, the place and

rout has paced the design in different places.

Spartacus FPGA board

Testing the multiplication system

Comparison of MultipliersXA

Table 7. Performance comparison for two’s complement multipliers By Chen Yaoquan, M.Eng. 2005

Multiplier

Modified Booth

Multiplier

Wallace-Tree

Multiplier

Modified Booth-

Wallace

Multiplier

Twin Pipe

Serial-

Parallel

Multiplier

Behavioral

Multiplier

Area – Total CLB’s

(#)3076.50 2649.50 3325.50 2672.50 490.00 2993.50

Maximum Delay

D(ns)35.78 24.43 18.93 18.53 107.52 (3.36x32) 49.33

Total Dynamic

Power P (W)7.52 6.33 7.46 6.41 0.28 6.24

Delay ·Power

Product (DP)

(ns W)268.98 154.64 141.14 118.76 30.62 307.58

Area•Power

Product (AP)

(# W)23128.20 16771.60 24793.93 17127.79 139.54 18665.07

Area•Delay

Product (AD)

(# ns)1.10E+05 6.47E+04 6.30E+04 4.95E+04 5.27E+04 1.48E+05

Area•Delay2

Product

(# ns2)

3.94E+06 1.58E+06 1.19E+06 9.18E+05 5.66E+06 7.28E+06

Table 7. Performance comparison for Unsigned multipliers By Chen Yaoquan, M.Eng. 2005

Multiplier

Modified Booth

Multiplier

Wallace-Tree

Multiplier

Modified

Booth-

Wallace

Multiplier

Twin Pipe

Serial-

Parallel

Multiplier

Behavioral

Multiplier

Area – Total CLB’s

(#)3280.50 2800.00 3321.50 2845.50 487.00 3003.00

Maximum Delay

D(ns)37.23 25.33 18.93 18.33 107.52 44.50

Total Dynamic

Power P (W)7.57 6.66 7.32 6.66 0.29 6.26

Delay ·Power

Product (DP)

(ns W)281.88 168.77 138.60 122.13 30.66 278.53

Area•Power

Product (AP)

(# W)24837.98 18656.40 24319.36 18959.57 138.89 18795.78

Area•Delay

Product (AD)

(# ns)1.22E+05 7.09E+04 6.29E+04 5.22E+04 5.24E+04 1.34E+05

Area•Delay2

Product

(# ns2)

4.55E+06 1.80E+06 1.19E+06 9.56E+05 5.63E+06 5.95E+06

The relation of Area

and Delay for

behavioral

multiplier --

"banana curve" 2950

0 20 40 60 80

Area (#)

Delay (ns)

Series1

Change the value of “set_max_delay” in Script file (ns)

0 10 20 30 40 50 60 >60

Area(#) 3014.

Power(w) 6.649

Delay(n

s)31.98 31.98 30.93 30.08 39.93 49.88 59.63 59.63

By Chen Yaoquan, M.Eng. 2005

Multiplier

Modified

Multiplier

Wallace-

Multiplier

Modified

Booth-

Wallace

Multiplier

Twin Pipe

Serial-

Parallel

Multiplier

Behavioral

Multiplier

Area Medium Small Large Small Smallest Medium

Critical Delay Medium Fast Very Fast Fastest Very Large Large

ConsumptionLarge Medium Large Medium Smallest Medium

Complexity Simple ComplexMore

Complex

ComplexSimple Simplest

Implement Easy Medium Difficut Difficut Easy Easiest

Pipelining SimulationX

Synthesis for Signed MultipliersXA

ArrayModified Booth

Wallace Tree

Modified Booth

-Wallace TreeTwin Pipe S/P Behavioral

Synthesis for Unsigned MultipliersXA

ArrayModified Booth

Wallace Tree

Modified Booth

-Wallace TreeTwin Pipe S/P Behavioral

Conclusion X

• Modified Booth and Wallace Tree are the best

techniques for high speed multiplication.

• Wallace Tree has the best performance, but it is

hard to implement.

• Booth algorithm based multipliers have lower area

among parallel multipliers.

• For behavioral multipliers, the area will increase

while the delay decreases.

ComparisonArray

Multiplier

Modified

Multiplier

Wallace Tree

Multiplier

Modified Booth

& Wallace Tree

Multiplier

Twin Pipe Serial-

Parallel

MultiplierArea – Total

CLB’s (#)

1165 1292 1659 1239 133

Maximum Delay

(ns) 187.87ns 139.41ns 101.14ns 101.43ns

22.58ns

(722.56ns)

Consumption at

highest speed

16.6506m

(at 188ns)

23.136mW

(at 140ns)

30.95mW

(at 101.14ns)

30.862mW

(at 101.43ns)

2.089mW

(at 722.56ns)

Delay Power

Product (DP)

(ns mW)

3128.15 3225.39 3130.28 3130.33 1509.42

Area Power

Product (AP)

(# mW)

19.397 x

29.891 x 103 51.346 x 103 38.238 x 103 277.837

Area Delay

Product (AD)

(# ns)

218.868 x

180.118 x

167.791 x 103 125.671 x 103 96.101 x 103

Area Delay2

Product(AD2)

(# ns2)

41.119 x

25.110 x 106 16.970 x 106 12.747 x 106 69.438 x 106

NOTICE

The rest of these slides are for extra information only

and are not part of the lecture

Array Addition

Addition

binary

numbers

using the

Wallace

principal

RESULT 32 Adder37

REGSTER37

LAST_RESULT 37

B BEGIN0 CLK

MULT320

COUNTER20 INVERTER

FINISH0 END0

Baugh-Wooley two's complement

multiplier:

FAFA FA FA

FAFA FA FA FAFA

a4b0' a3b0a1b0a2b0 a0b0

P9 P8 P7 P6 P5 P4 P3 P2 P1

a3b1 a2b1a1b1

a0b2a3b2 a2b2 a1b2

a4' b4'

a0b3a3b3 a2b3 a1b3

a0'b4a4b4

a3'b4 a2'b4 a1'b4

The schematic logic circuit diagram of a 5-by-5 Baugh-Wooley two’s complement array multiplier

Example of Baugh-Wooley Two’s Complement Multiplication

p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 P

a4' a3'b4 a2'b4 a1'b4 a0'b4

a4 a3 a2 a1 a0

b4 b3 b2 b1 b0

a4b0' a3b0 a2b0 a1b0 a0b0

a4b4 a4b3' a3b3 a2b3 a1b3 a0b3

b4' a4

1 1 1 0 1 1 1 1 1 1

0 0 1 0 0

0 1 1 0 1

1 1 0 1 1

1 0 0 0 0

0 1 0 1 1

0 0 1 0 1 1

0 1 0 1 1

0 0 0 1 0 0 0 0 0 1

1 0 0 0 0

0 1 1 0 1

0 0 1 0 1

0 0 0 0 0

0 1 1 0 1

0 0 0 0 0 0

0 1 1 0 1

0 0 0 1 0 0 0 0 0 1

0 1 1 0 0

1 0 0 1 1

1 1 0 1 1

0 0 0 1 1

1 0 0 0 1 1

1 0 0 0 0

1 1 1 0 1 1 1 1 1 1

1 0 0 1 0

0 1 1 0 1

1 1 0 1 1

0 1 1 0 1

0 0 1 1 0 1

0 0 0 0 0

Cluster MultipliersX

Divide the multiplier into smaller multipliers

Cluster MultipliersXA

Multiplier

A8~A7 A3~A0

Multiplier

Final Addition Stage

Multiplier

Multiplicand

B8~B7 B3~B0

Multiplier

44 4 4

EN3 EN2 EN1 EN0

P8-bit cluster low power multiplier

The circuit used

to generate the

enable signal

Cluster Multipliers

• Dividing the multiplication circuit into clusters

(blocks) of smaller multipliers

• Applying clock gating techniques to disable the

blocks that are producing a zero result.

• Features

– Low Power (claims 13.4 % savings)

Multiplexer-Based Array MultipliersXA

jj ZyxP

jjjjj yXYxZ 021 ...XXXX jjj

Two types of cells:

Cell 1: produce the terms Zij2j and includes a full adder of

carry save adder array

Cell 2: produce the terms xjyj 2j and includes a full adder of

carry save adder array

Multiplexer-Based Array Multipliers

• Characteristics

– Faster than Modified Booth

– Unlike Booth, does not require encoding logic

– Requires approximately N2/2 cells

– Has a zigzag shape, thus not layout-friendly

• Improvement

– More rectangular layout

– Save up to 40 percent area without penalties

– Outperforms the modified Booth multiplier in both

speed and power by 13% to 26%

Gray-Encoded Array Multiplier XA

Dec Hyb Dec Hyb Dec Hyb Dec Hyb

0 0000 4 0100 -8 1100 -4 1000

1 0001 5 0101 -7 1101 -3 1001

2 0011 6 0111 -6 1111 -2 1011

3 0010 7 0110 -5 1110 -1 1010

• 2’s complement Hybrid Coding

– Having a single bit different for consecutive values

– Reducing the number of transitions, and thus power ( for

highly correlated streams ).

Gray-Encoded Array Multiplier XA

An 8-bit wide 2’s complement radix-4 array multiplier

Gray-Encoded Array Multiplier

• Characteristics

– Uses gray code to reduce the switching activity

of multiplier

– Saves 45.6% power than Modified Booth

– Uses greater area(26.4% ) than Modified Booth

Ultra-high Speed Parallel Multiplier

• How to ultra-high speed?

– Based on Modified Booth Algorithm and Tree

Structure (Column compress)

– Chooses efficient counters (3:2 and 5:3)

– Uses the new compressor (faster 20% )

– Uses First Partial product Addition (FPA)

Algorithm (reducing the bits of CLA by 50%)

Ultra-high Speed Parallel Multiplier XA

Calculate the

partial products as

soon as possible.

The final CLA is

only 16-bit instead

of 32-bit.

Divide into 3 rows

or 5 rows only

(most efficient).

Calculation process using parallel counter in case of 16x16

---Totally reduce delay by about 30%

ULLRLF Multiplier

• ULLRLF stands for Upper/Lower Left-to-

Right Leapfrog.

• Combine the following techniques:

– Signal flow optimization in [3:2] adder array

for partial product reduction,

– Left-to-right leapfrog (LRLF) signal flow,

– Splitting of the reduction array into upper/lower

parts.

ULLRLF MultiplierXA

1) Signal flow optimization in [3:2] adder array

-- For n = 32, the delay is reduced by 30 percent.

-- The power is saved also.

PPij is always connected to pin A Sin/Cin are connected to B/C ,

most Sin signals are connected to C

ULLRLF MultiplierX

2) Left-to-Right Leapfrog (LRLF) Structure

-- The delay of signals is more balanceable.

-- Low power.

The sum signals skip

over alternate rows.

ULLRLF MultiplierX

3) Upper/Lower Split Structure

-- The long path of data path be broken into parallel short

paths, there would be a saving in power.

-- The delay of Partial Products Reduction is reduced.

Only n+2 bits

ULLRLF MultiplierXA

Floorplan of ULLRLF (n = 32)

•ULLRLF multipliers have

less power than optimized

tree multipliers for n ≤ 32 while

keeping similar delay and

• With more regularity and

inherently shorter

interconnects, the ULLRLF

structure presents a

competitive alternative to tree

structures.

Signed Array MultiplierXA

A29A31

A31 A30

A30 A0

A2 A1 A0

A3 A2 A1

FA FAFA

A30 A1 A0

32-bit carry look ahead adder

P63 P62 P61 P34 P33 P31 P30 P2 P1 P0P3

STAGE 4 TO 30

(Each stage includes 32 AND gates, 31 full adders ,1 half adder and 1 NOT gate)

32*32-Bit Array Multiplier for Signed Number

One stage of carry

save adder

Unsigned Array MultiplierXA

FA FA HA

HAHA FAFA

A30 A0

A30 A1 A0

A2 A1 A0

A3 A2 A1

FA FAFA

A30 A1 A0

P63 P62 P61 P33 P32 P31 P30 P2 P1 P0P3

STAGE 4 TO 30

(Each stage includes 32 AND gates, 31 full adders and 1 half adder)

32*32-Bit Array Multiplier for Unsigned Number

One stage of carry

save adder

Signed Modified Booth MultiplierX

................................{

…............................1 E .............................................................1 E ................................….........................1 E ..................................S….......................1 E ..................................S.........................1 E ..................................S...........................1 E ..................................S...........................1 E ..................................S...........................1 E ..................................S..........….............1 E ..................................S...........................1 E ..................................S...........................1 E ..................................S...........................1 E ..................................S...........................1 E ..................................S...........................1 E ..................................S...........................1 E ..................................S...........................1 E ..................................S...........................1 E ..................................S.............................1 E ............................. ..S.....................................

6 3 6 0 5 5 5 0 4 5 4 0 3 5 3 0 2 5 2 0 1 5 1 0 5 0

32*32-bit Booth Multiplier for

Signed Number

E = The inversion of sign bit in each row

S = the B i+1 bit in the three encoded bits

16 rows of partial products

B i-1 B B i+1

Signed Modified Booth

MultiplierXA

SEL SEL SEL SEL SEL SEL

A0 0A1A2A3A4

SEL SEL SEL SEL

A0 0A1A2

FA FA FA

SEL SEL SEL

A0 0A1

SEL SEL SEL SEL SEL SEL

A31 A31 A30 A29 A28 A27 A26

FA FA FAFAHA

SEL SEL SEL SEL

A31 A31 A30 A29 A28

SEL SEL

A31 A31 A30

HA FA HA HA HA HA HA

INVERT00

P0P1P2P3

INVERT2

P63 P62 P61 P60 P5

STAGE 3 TO 15

(Each stage includes 33 PP selectors, 31 full adders ,1 half adder and 1 NOT gate)INVERT n

Encoder

B[1:0]0

B[3:1]

B[5:3]

B[31:5]

INVERT0

INVERT1

INVERT2

INVERT n

One stage

32*32-Bit Modified Booth Multiplier for Signed Number

Unsigned Modified Booth MultiplierX

…............................1 S' .............................................................1 S' .................................….........................1 S' ...................................S….......................1 S' ...................................S.........................1 S' ...................................S...........................1 S' ...................................S...........................1 S' ...................................S...........................1 S' ...................................S..........….............1 S' ...................................S...........................1 S' ...................................S...........................1 S' ...................................S...........................1 S' ...................................S...........................1 S' ...................................S...........................1 S' ...................................S...........................1 S' ...................................S...........................1 S' ...................................S...........................1 S' ...................................S.................................................................S...........................

................................{

6 3 6 0 5 5 5 0 4 5 4 0 3 5 3 0 2 5 2 0 1 5 1 0 5 0

32*32-bit Booth Multiplier for

unsigned Number

S = the B i+1 bit in the three encoded bits

S' = The inversion of S

B i-1 B B i+1

17 rows of partial products

Unsigned Modified Booth MultiplierXA

SEL SEL SEL SEL SELSEL_

A0 0A1A2A3A4

SEL SEL SEL

A0 0A1A2

FA FA FA

SEL SEL

A0 0A1

SEL SEL SEL SEL SEL

A31 A30 A29 A28 A27 A26

FA FA FAFAHA

SEL SEL SEL

A31 A30 A29 A28

A31 A30

FA HA HA HA HA HA HA

P0P1P2P3

P4P63 P62 P61 P5

Encoder

B[1:0]0

B[3:1]

B[5:3]

B[i+1, I, i-1]

One stage

32*32-Bit Modified Booth Multiplier for Unsigned Number

SEL SEL

A31 A30 A29

Encoder

00B[31]

X1[16]

X2[16]

S[16]SEL_

ENDSEL_

P32P33P34P35 P31

STAGE 3 TO 15

(Each stage includes 33 PP selectors, 32 full adders ,1 half adder and 1 NOT gate)

Wallace Tree multipliersX

32 partial products added in Wallace Tree Adder

64-bit Carry Look-ahead Adder

A[31:0] B[31:0]

C[63:0] S[63:0]

P[63:0]

Wallace Tree multipliers

............................................................................................................................ ... ........................................................................................................................ ....................................................... .................................................... . ................................................... . .................................................. ................................................. ..............................................................................................……......................................…….....................................…….............................................................................………............................………….......................………….....................………….........................…………..................……………..............……............... ......... ........... ....

................................................................. .......................................................... .. ......................................................................................................................... ....................................................... .................................................... . ................................................... . .......................................... ....... ...............................................…................................................................................................……......................................……......................................……...................................………………….................

............................................................................................................................ .. .............................................................................................................................................................................…...................................................……..............................................……....................................... ....….................................…………………............................ ...................... ........................

............................................................................................................................ .. ......................................................................................................................... ....................................................... .................................................... . ................................................... . ........................

............................................................................................................................ .. ......................................................................................................................... ....................................................... .................................................... . ................................................... . .......................................... ....... .

............................................................................................................................ .. ......................................................................................................................... ..............................................

............................................................................................................................ ...................................................................................................

................................................................................................................................. .

................................................................. ............................................................... .............................................................. ............................................................. ............................................................ ........................................................... .......................................................... ......................................................... ........................................................ ....................................................... ...................................................... ..................................................... .................................................... ................................................... ................................................. .................................................................................................................................................. .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................. ....................................... ..................................................................

................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ ....................................................................

• Use the 3:2 counters

and 2:2 counters

• Number of levels of

= log (32/2) / log (3/2)

• Irregular structure

• Fast

3:2 counter

....Carry

2:2 counter

Input:

Output:

Wallace Tree multipliersX

Carry Propagate/Generate unit

8-Bit BCLA

64-Bit Summation Unit

8-Bit BCLA

P63-P56G63-G56

P7-P0G7-G0

..................................

C7-C0C63-C56

C8PM1GM1

PM0GM0

C16PM2GM2

C24PM3GM3

C40PM5GM5

PM4GM4

C48PM6GM6

C56PM7GM7

64-Bit Carry Look Ahead Adder

B0 A63 .................................. A0

P63 .................................. P0 G63 .................................. G0

.....................................................................................

C55-C48 C47-C40 C39-C32 C31-C24 C23-C16 C15-C8

P63 .................................. P0 C63 .................................. C0

.......................................................................................S63 S0C64

2-level hierarchical

Modified Booth-Wallace Tree MultipliersX

Modified Booth-Wallace Tree MultipliersXA

• Use the 3:2 counters

and 2:2 counters

• Number of levels of

= log (16/2) / log (3/2)

• Irregular structure

• Fast

• Less area

Rearrage

........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................

PP Dot Matrix of Booth-Wallace

Multiplier for Signed Number

............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................

............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................

................................................

........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................

.........................................

......................................................................................................................................................................................................................................................................................................................................................................................................

..........................................................

....................................................................................................................................................................................................................................................................

...................................................................................................................................................................................................

..................................................................................................................................

Twin pipe serial-parallel multipliersXA

Parallel in – serial out

shift registers

Parallel in – serial out

shift registers

32-bit twin pipe serial-parallel

multiplier unitB31 B29 …… B3 B1

B30 B28 …… B2 B0

Load/Shift

Block diagram of 32*32-bit signed twin pipe serial-parallel

multiplier with serial/parallel conversion logic

Serial in – parallel out

shift registers

Serial in – parallel out

shift registers

P62 P60 ……………………… P2 P0

P63 P61 ……………………… P3 P1

Result_ready

A31 A30 …………………… A1 A0

Signed twin pipe serial-parallel

multipliersX

A31 A30

Even data bits on rising clock

Odd data bits on rising clock

…... B2 B0 0 0 reset

Product

product

falling_edge

rising_edge

…... B3 B1 0 0 reset

32*32-bit twin pipe serial-parallel multiplier

for signed number

Repeat 28 units more

B31 B29 …...

A30 A0

“Sign” control line and the sign-change hardware

Unsigned twin pipe serial-parallel

multipliersX

A31 A30

Even data bits on rising clock

Odd data bits on rising clock

…... B2 B0 0 0 reset

Product

product

falling_edge

rising_edge

…... B3 B1 0 0 reset

32*32 bit twin pipe serial-parallel multiplier

for unsigned number

Repeat 28 units more

• Don’t need the “Sign” control line and the sign-change hardware

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