l9 timing model wait
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Timing Model
VHDL uses the following simulation cycle to model thestimulus and response nature of digital hardware
Start Simulation
Update Signals Execute Processes
End Simulation
Delay
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Delay Types
Input
delayOutput
All VHDL signal assignment statements prescribean amount of time that must transpire before thesignal assumes its new value
This prescribed delay can be in one of threeforms:
Transport -- prescribes propagation delay only
Inertial -- prescribes propagation delay and minimuminput pulse width
Delta -- the default if no delay time is explicitly specified
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Delta Delay
A delta delay is a very small delay(infinitesimally).
It does not correspond to any real delay, andactual simulation time does not advance.
Delta delay allows for ordering of events thatoccur at the same simulation time during asimulation.
Each unit of simulation time can be considered
to be composed of an infinite number ofsimulation time plus an integral multiple ofdelta delays.
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Default signal assignment propagation delay if no delay isexplicitly prescribed
VHDL signal assignments do not take place immediately
Delta is an infinitesimal VHDL time unit so that all signalassignments can result in signals assuming their values at afuture time
E.g.
Supports a model of concurrent VHDL process execution Order in which processes are executed by simulator does not
affect simulation output
Delta Delay
Output
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Delta DelayAn Example without Delta Delay
What is the behavior of C?
1
IN:1->0A
B
C
NAND gate evaluated first:
IN: 1->0
A: 0->1
B: 1->0
C: 0->0
NAND gate evaluated first:
IN: 1->0
A: 0->1
B: 1->0
C: 0->0
AND gate evaluated first:
IN: 1->0A: 0->1
C: 0->1
B: 1->0
C: 1->0
AND gate evaluated first:
IN: 1->0A: 0->1
C: 0->1
B: 1->0
C: 1->0
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Delta DelayAn Example with Delta Delay
What is the behavior of C?
IN:1->0
1
A
B
C
Using delta delay schedulingUsing delta delay schedulingTime Delta Event
0 ns 1 IN: 1->0
eval INVERTER2 A: 0->1
eval NAND, AND
3 B: 1->0
C: 0->1
eval AND
4 C: 1->0
1 ns
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Transport Delay
Transport delay must be explicitly specified
I.e. keyword TRANSPORT must be used
Signal will assume its new value after specified
delay -- TRANSPORT delay exampleOutput
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Inertial delay model
An input value must be stable for a specifiedpulse rejection limit duration before the value isallowed to propagate to the output.
Example:
Z
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Inertial Delay
Provides for specification propagation delay andinput pulse width, i.e. inertia of output:
Inertial delay is default and REJECT is optional :Output
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Inertial Delay (cont.)
Example of gate with inertia smaller thanpropagation delay
e.g. Inverter with propagation delay of 10ns which
suppresses pulses shorter than 5ns
Note: the REJECT feature is new to VHDL 1076-1993
Output
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Signal Waveforms
It is possible to assign multiple values to asignal, each with a different delay value.
For example:
Phase1
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Wait Statement
Wait Statement: provides a way to suspend the executionof a process
process always suspends after execution the laststatement.
There are three basic forms of the waitstatement.
wait on sensitivity list;
wait until boolean-expression;
wait fortime-expression;
they may also combined in a singlewait statement:wait
on sensitivity-listuntil boolean-expressionfortime-expression;
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Wait Statement (cont.)
Examples:-
1. wait on A, B, C;
2. wait until A= B;
3. wait for10 ns;
4. wait on clock for20 ns;
5. wait until SUM >100 for50 ms;
the process suspends for a maximum of 50 ms
until the value of signal SUM is greater than 100. If the Boolean condition is not satisfied for 50ms, the process resumes from the statementfollowing the wait statement
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6. wait on clock until SUM> 100;continue to wait if SUM
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Wait Statement (cont.)
It is possible for a process not to have an explicitsensitivity list The process may have one ormore wait statements
- the process must have at least one wait statement;
- otherwise, it will never get suspended (infiniteloop)
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Wait Statement (Example)
process --no sensitivity list
variable temp1, temp2:BIT;
begin
temp1 := Aand B;
temp2 := C and D;
temp1 := temp1 ortemp2;
Z
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Wait example
WAIT0 : process
begin
wait on DATA;
sig_A
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Null Statement
Null Statement: is a sequential statement that doesnot cause any action to take place.
- Execution will continues with the next statement
can be used in an ifor in case statement
The format:
null;
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