other logic implementations

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Other Logic Implementations

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Pass gate/Transmission Gate

C=1 OUT=A

C=0 OUT=NO OUTPUT (OPEN CIRCUIT)

CMOS TRANSMISSION GATE (TG)

NMOS passes good logic ‘0’

PMOS passes good logic ‘1’

Pass Gate

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Multiplexer

C A B F C A B F

0 0 0 0 1 0 0 0

0 0 1 1 1 0 1 0

0 1 0 0 1 1 0 1

0 1 1 1 1 1 1 1

C=1 C=01

0A

0

1 B

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AND Gate

A B F

0 0 0

0 1 0

1 0 0

1 1 1

A=1 B=1

A=0 B=1

1

1

1

10

1

0

0 01

0

1

1

0

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OR Gate

A B F

0 0 0

0 1 1

1 0 1

1 1 1

0

1

0

0

0

1

0

1

01

0

1

A=0B=0

A=1B=0

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Delay Calculations of Pass gates

buffereqeqeq m

nmnRC )1(]

2

)1([69.0

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4-1 MUX

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High Current Delivery

For High Current requirements of L-H

transitions

For High Current requirements of H-L

transitions

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Tristate

EN IN OUT

0 0 0

0 1 1

1 0 X

1 1 X

1

0

0/1 1/0

0

Z0/1

1

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EX-OR Gate

A B F

0 0 0

0 1 1

1 0 1

1 1 0

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EX_OR1

0

0

0

1 1

A=1 B=0

1

1

0

1

0 0

A=1 B=1

1

01

A=1B=1

X1

0

1

1

0

0

0

1

A=0B=1

1

1

1 1

1

0

0

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X

12

EX-OR/NOR With Driving Output

A=0B=0

A=0B=1

0 0

1

0

0

0

0

1

1

0

10

10

X

0

An inversion of the left circuits

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PLA

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Example : PLA

cbabcy

acy

baabcy

3

2

1

)()(

)()(

1

1

1

1

1

bacbay

bacbay

baabcy

baabcy

baabcy

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Transistor level Implementation

Output lineInput Lines

Input Lines

Output Lines

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Pseudo-nMOS Implementation

Ground

Red is Input

Green is Ground

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Altera 40nm FPGA’ahttp://www.altera.com/literature/br/br-stratix-

iv-hardcopy-iv.pdf

Table 2. HardCopy IV E Devices Overview

Device (1) ASICGates

(2)

MemoryBits(3)

I/O Pins PLLs FPGAPrototype

HC4E2YZ 3.9M 8.1 296 - 480 4 EP4SE110

HC4E3YZ 9.2M 10.7 296 - 480 4 EP4SE230

HC4E4YZ 7.6M 12.1 - 13.3 392 - 864 4/8/12 EP4SE290

HC4E5YZ 9.5M 16.8 480 - 864 4/8/12 EP4SE360

HC4E6YZ 11.5M 16.8 736 - 880 8/12 EP4SE530

HC4E7YZ 13.3M 16.8 736 - 880 8/12 EP4SE680

Notes:1.Y = I/O count, Z = package type (see the product catalog for more information)

2.ASIC gates calculated as 12 gates per logic element (LE), 5,000 gates per 18 x 18 multiplier(SRAMs, PLLs, test circuitry, I/O registers not included in gate count)

3.Not including MLABs

CONCORDIAVLSI DESIGN LAB

Features Artix-7 Kintex-7 Virtex-7 Spartan-6 Virtex-6

Logic Cells 352,000 480,000 2,000,000 150,000 760,000

BlockRAM 19Mb 34Mb 68Mb 4.8Mb 38Mb

DSP Slices 1,040 1,920 3,600 180 2,016

DSP Performance (symmetric FIR)

1,248GMACS 2,845GMACS 5,335GMACS 140GMACS2,419GMACS

Transceiver Count 16 32 96 8 72

Transceiver Speed 6.6Gb/s 12.5Gb/s 28.05Gb/s 3.2Gb/s 11.18Gb/s

Total Transceiver Bandwidth (full duplex)

211Gb/s 800Gb/s 2,784Gb/s 50Gb/s 536Gb/s

Memory Interface (DDR3)

1,066Mb/s 1,866Mb/s 1,866Mb/s 800Mb/s 1,066Mb/s

PCI Express® Interface

Gen2x4 Gen2x8 Gen3x8 Gen1x1 Gen2x8

Agile Mixed Signal (AMS)/XADC

Yes Yes Yes   Yes

Configuration AES Yes Yes Yes Yes Yes

I/O Pins 600 500 1,200 576 1,200

I/O Voltage1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V

1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V

1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V

1.2V, 1.5V, 1.8V, 2.5V, 3.3V

1.2V, 1.5V, 1.8V, 2.5V

EasyPath Cost Reduction Solution

- Yes Yes - Yes

FPGA Comparison Table

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Sequential Circuits

For correct operation,

TW cl

Solution:

use a narrow clock pulse. (Impractical)

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Clocking Conditions

Condition to achieve proper operation:

Tcl

Problem: Clock Skew

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Two-phase Non-Overlapping clocking

Problems:

•Routing two Clock Nets,

•Lower Frequency of

Operation

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Sequential Circuits-Single Clock

Single clock to synchronize operationsSuitable for simple applications

-ve going edge

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Different Latches

Dynamic

Static latch with cross-coupled circuit

Static latch with clocked feedback

Buffered static latch with clocked feedback

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D-Latch and the Flip Flop Operations

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The Master Slave Flip Flop +ve edge of CLK 2

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Master Slave Flip Flop

Setup time=G4+G5+G6

Hold time=G1+G2

W1=G5+G6+G3

W2=G9+G10+G7

Cycle time=W1+W2

•CLK generated locally

•Typical arrangement,

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BeforeCP Active Edge 0 1 Data has to bet set stable

Set-Up TimeG4+G5+G6

0

0

01

0

1

1

0

X

X

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1

10

1

0

0

1

X

XHold TimeG1+G2

1

AfterCP Active Edge 1 0 Data has to bet set stable

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0

0

01

0

1

1

0

X

X

LOW VALUE, W2G3 +G5 +G6

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0

0

01

0

1

1

0

X

X

CLK HIGH , W1G7 +G9 +G10

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CMOS two phase double latch circuits

Static buffered

Static un-buffered CLK1=1 CLK2=1

Dynamic

CLK1=1 CLK2=1

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D Flip-Flop

clkreset

D Q

Edge Triggered, D Flip Flop

clk

D

reset

Q

NAND1

NAND2

NAND3

NAND4

NAND5

NAND6

S

R

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When CLK changes from 0 to 1

Case1, D=0: tsetup= t4, thold=t3

clk

D

reset

Q

NAND1

NAND2

NAND3

NAND4

NAND5

NAND6

S

R

Path for set up

Path for hold

Nand00 101 1101110

01

1

1

010 1

0

1

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When CLK changes from 0 to 1

Case2, D=1 tsetup=t4 + t1 thold= t2Path to set

up

clk

D

reset

Q

NAND1

NAND2

NAND3

NAND4

NAND5

NAND6

S

R

Path to hold

1

100

1

1

1

Nand00 101 1101110

0 1

1

011

1

1

0

0

1

1

1

1 0

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clk

D

reset

Q

NAND1

NAND2

NAND3

NAND4

NAND5

NAND6

S

R

When CLK changes from 0 to 1

Case1, D=0: tsetup= t4, thold=t3

Case2, D=1 tsetup=t4 + t1 thold= t2

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D Flip FlopRising Edge

Data Change

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D Flip-Flop with direct set and clear

Input Output

SD CD D C O O’

H L X X H L

L H X X L H

H H X X H H

On+1 O’n+1

L L L L H

L L H H L

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JK Flip-FlopInput Output

SD CD C J K O O’

H L X X X H L

L H X X X L H

H H X X X H H

On+1 O’n+1

L L L L No Change

L L H L H L

L L L H L H

L L H H O’n On

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Thank you !