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P-N Junction Doping Profile Extraction
via Inverse Modelling By
Tong Lee Too
Student No. 40157375
Submitted to the Department of Information Technology and Electrical Engineering on
23rd May 2003 in Partial Fulfilment of the Requirements for the Bachelor of
Engineering in Electrical Engineering at the University of Queensland
Supervisor: Associate Professor Y.T Yeow
ii
Tong Lee Too
6/45 Mitre Street
St Lucia QLD 4067
23rd May 2003
The Dean
Faculty of Engineering
University of Queensland
St Lucia 4067
Dear Sir,
In accordance with the requirements for the degree of Bachelor of Engineering
(Honours) in the division of Electrical Engineering, I hereby submit for your
consideration this thesis entitled “P-N junction doping profile extraction via inverse
modelling”. The work was performed under the supervision of Associate Professor Y.T
Yeow.
I declare that the work submitted in this thesis is my own, except as acknowledged in
the text and footnotes. This work has not been previously submitted for a degree at the
University of Queensland or at any other institution.
Yours sincerely,
____________
Tong Lee Too
iii
Acknowledgement
I would like to thank my supervisor, A. Prof Y.T. Yeow for his precious guidance, time
and advice for this project.
Following that, I would like to thank Ron Rasch from Centre for Microscopy and
Microanalysis for helping me take photograph of the wafers under test using the
electron microscope.
Next, I would like to thank Peter Allen who has been professional and helpful in
assisting me in setting up equipment required in this thesis.
Finally, I would like to thank my friends and family for their support and
encouragement throughout my undergraduate study at the University of Queensland. In
particular, I would like to thank Tan Yancun for helping me prove read this thesis.
iv
Abstract
With the increase complexity of device fabrication process and downsizing of
semiconductor devices, there is an increasing importance to measure the doping profile
of the final device [1]. Knowledge of doping profiles of semiconductors devices allows
the determination of electrical characteristics of the devices. Extracted doping profiles
can also act as an indicator of the fabrication process of the devices.
Over the years, many methods have been developed by researchers to extract doping
profiles of semiconductor devices. The conventional analysis of capacitance-voltage (C-
V) measurement is widely used for doping profile extraction due to its simplicity.
However, this analysis provides only an approximate value of the actual doping profile
of the device [2]. It could only extract doping profile of the less highly doped side of P-
N junctions and the extracted profile is limited.
In this thesis, a more accurate method of doping profile extraction for P-N junction is
presented. The conventional method is extended via an inverse modelling approach in
hope to overcome existing limitations. The inverse modelling process is done in device
simulator ATLAS. An initial estimate of the doping profile is treated as input and then
simulated to obtain a C-V curve in ATLAS. The parameters in ATLAS are adjusted
until the C-V curve obtained in the simulation best fits the C-V curve obtained from the
experiment. The doping profile that produces the C-V curve that best fits the measured
C-V curve is deemed to possess the profile of the actual device.
As an introduction, this thesis surveys the literature of P-N junction device physics and
conventional C-V technique. Next, the method adopted in this thesis will be presented
with experimental verification via measurements on an actual device. Doping profile for
the lightly doped side of the P-N junction has been extracted with the method purposed
and results matched with the expected result thus, proving the validity of the proposed
method.
v
Table of Content
Acknowledgement ...........................................................................................................iii
Abstract............................................................................................................................ iv
Table of Content ............................................................................................................... v
List of Figures and Tables ..............................................................................................vii
Chapter 1 .................................................................................................................... - 1 -
Introduction................................................................................................................ - 1 -
1.1 Introduction.................................................................................................. - 1 -
1.2 Literature review.......................................................................................... - 1 -
1.3 The Scope of This Work.............................................................................. - 2 -
1.4 Organization of this thesis ........................................................................... - 2 -
Chapter 2 .................................................................................................................... - 4 -
Theoretical Background............................................................................................ - 4 -
2.1 P-N junction Device Physics ....................................................................... - 4 -
2.1.1 P-N junction in Thermal Equilibrium.................................................. - 5 -
2.1.2 P-N Junction in Forward bias .............................................................. - 6 -
2.1.3 P-N Junction in Reverse Bias .............................................................. - 7 -
2.1.4 Capacitance Effect on P-N junctions ................................................... - 9 -
2.1.5 Capacitance Measurements on P-N junctions ................................... - 10 -
2.2 Conventional C-V Technique on P-N junction.......................................... - 12 -
2.2.1 Advantages of the Conventional C-V Technique .............................. - 12 -
2.2.2 Theory of the Conventional C-V Technique ..................................... - 13 -
2.2.3 Disadvantages and Limitations of the Conventional C-V Technique - 16 -
Chapter 3 .................................................................................................................. - 18 -
Inverse Modelling .................................................................................................... - 18 -
3.1 Introduction to Inverse Modelling ............................................................. - 18 -
3.1.1 Advantages of Inverse Modelling.......................................................... - 18 -
3.1.2 Existing Application of Inverse Modelling ........................................... - 19 -
3.2 Basis of Forward Modelling ...................................................................... - 19 -
vi
3.3 Implementation of Inverse Modelling ....................................................... - 21 -
Chapter 4 .................................................................................................................. - 25 -
Setup of Equipments and Software Coding .......................................................... - 25 -
4.1 Setting up the HP4275A LCR Meter......................................................... - 26 -
4.2 Setting up the HP4825 Multi-meter........................................................... - 29 -
4.3 Description of the LABVIEW Program .................................................... - 29 -
4.4 Device Simulation software ATLAS......................................................... - 32 -
4.4.1 Numerical Device Simulation in ATLAS.......................................... - 33 -
Chapter 5 .................................................................................................................. - 35 -
Discussion of Measurement Results ....................................................................... - 35 -
5.1 C-V Measurement from LABVIEW.......................................................... - 35 -
5.2 Doping Profile Extraction using conventional C-V technique. ................. - 41 -
Chapter 6 .................................................................................................................. - 44 -
Results from the Inverse Modelling process.......................................................... - 44 -
Chapter 7 .................................................................................................................. - 48 -
Summary and Conclusions ..................................................................................... - 48 -
Recommendations for Future Work and Reprise ...................................................... - 49 -
Bibliography .............................................................................................................. - 50 -
APPENDIX I – Setup of Equipment Used ................................................................ - 52 -
APPENDIX II - Source code for program in LABVIEW ......................................... - 53 -
APPENDIX III - Source code for program in ATLAS ............................................. - 57 -
vii
List of Figures and Tables
Figure 2.1.1: Energy band diagram P-N junction in thermal equilibrium-----------------5
Figure 2.1.2: Energy band diagram P-N junction in forward bias--------------------------6
Figure 2.1.3: Energy band diagram P-N junction in reverse bias---------------------------7
Figure 2.4.1: P-N junction in (a) Actual circuit, (b) Parallel equivalent circuit and (c)
Series equivalent circuit--------------------------------------------------------------------------10
Figure 2.2.1: An asymmetrically doped P-N junction under bias condition--------------13
Figure 3.2.1: Flow chart for forward modelling to extract electrical characteristics of
semiconductor devices ---------------------------------------------------------------------------20
Figure 3.3.1: Flowchart of the inverse modelling process used in this thesis------------22
Table 4.1: Summary of equipments and function--------------------------------------------25
Figure 4.1.1: Equipment setup for the thesis--------------------------------------------------27
Figure 4.1.2: The HP 4275A LCR meter connections to the die cast box----------------27
Figure 4.3.1: Flow chart showing operation of the LABVIEW program-----------------30
Figure 4.3.2: Graphical user interface of the program written in LABVIEW------------32
Figure 5.1.1: Measured capacitance versus voltage of the P-N junction under test-----35
Figure 5.1.2: Structure of a typical BJT transistor-------------------------------------------36
Figure 5.1.3: Actual photograph of the device under test-----------------------------------37
Figure 5.1.4: C-V response under different frequencies-------------------------------------39
Figure 5.1.5: C-V plot of the P-N junction under different A.C voltage------------------40
Figure 5.2.1: Doping profile extracted using convention C-V technique-----------------42
Figure 6.1: Measured and Simulated C-V Curve Superimposed--------------------------44
Figure 6.2: Measured conductance versus voltage curve-----------------------------------45
Figure 6.3: Extracted doping profile via the inverse modelling approach---------------46
- 1 -
Chapter 1 Introduction
Chapter 1
Introduction
1.1 Introduction
In today’s semiconductor industry, success hinges on the ability to produce complex
high-quality devices. As a result, accurate characterisation of semiconductor devices has
never been more crucial [3]. Accurate measurements of the doping profile of the devices
will enable several important electrical characteristics of the devices to be known. To
add, this enables the quality of the fabricated device to be known and the efficiency of
the fabrication process. These are the reasons for development of more efficient and
accurate methods for doping profile extraction.
1.2 Literature review
Over the years, many different methods have been developed to determine doping
profiles of semiconductor devices. These methods are classified into two main
categories: destructive, such as SIMS, RBS, spreading resistance and AFM, or non-
destructive, such as the capacitance-voltage (C-V) methods and sub-threshold current-
voltage methods [4].
The C-V technique has been used extensively for doping profile extraction due to its
advantages. It is simple to implement and requires few equipment and measurements
could be obtained easily. In addition, the C-V technique is a non-destructive process
where the device is not damaged after measurement. However, there are several
limitations to this method. The conventional C-V technique only allows doping profile
of the less highly doped side of the junction to be determined. Furthermore, this method
prevents doping profile of the device near surface to be determined. These limitations
are the driving force that encourages a new doping profile extraction technique to be
developed.
- 2 -
Chapter 1 Introduction
1.3 The Scope of This Work
The objective of this thesis is to develop a method to accurately evaluate the doping
profile of semiconductor devices via inverse modelling. The inverse modelling approach
is proposed to accurately determine the doping profile of the P-N junction via an
extension to the convention C-V technique. The advantages of this method are that it
maintains the non-destructive benefit of the conventional C-V technique and at the same
time overcome some of the limitations of the convention C-V technique mentioned
above.
In this inverse modelling approach, the output (C-V curve) is known and the input
(doping profile) will be determined. The output is obtained from measurement of the
wafer using LCR meter which is controlled by a program written in LABVIEW. The
input is an initial guess for the doping parameters for the simulation in ATLAS. A
numerical simulation is executed on the device to extract the C-V response. The C-V
curve from simulation is then compared with the measured C-V curve to see if they
match. If they do not match, the doping parameters are adjusted and the process is
repeated. The doping profile that produces the C-V curve that best fits the measured C-
V curve is deemed to be equivalent to the doping profile of the actual device.
1.4 Organization of this thesis
Chapter 2
This chapter will analyse qualitatively and quantitatively the P-N junction device
physics and the conventional C-V technique including its advantages and disadvantages.
Chapter 3
This Chapter will give a brief introduction to inverse modelling. An example of existing
applications of inverse modelling will be discussed. Finally, how inverse modelling is
implemented in this thesis will be presented.
- 3 -
Chapter 1 Introduction
Chapter 4
This chapter covers the technical design and description of the equipments and software
used in this thesis. In particular, the operation of the two equipment used HP7275A
LCR meter and HP4825 multi-meter will be explained. The program in LABVIEW used
to control the two meters will be explained. Lastly how simulation in ATLAS from
SILVACO is performed will be discussed.
Chapter 5
This chapter presents the results obtained from the experiment. Doping profile extracted
via the conventional technique together with discussion of the results will be put
forward.
Chapter 6
This chapter presents the results from the inverse modelling process. The focus will be
mainly on the results of the simulated and measured C-V response. This gives the result
of the extracted doping profile of the device under test.
Chapter 7
This chapter will summaries the thesis and conclude the successfulness of the thesis.
Finally, recommendation for future work will be discussed.
- 4 -
Chapter 2 Theoretical Background
Chapter 2
Theoretical Background
This chapter provides a theoretical background of various areas that is important for the
thesis. The two main areas of interest are device physics of P-N junction and discussion
of the conventional C-V technique for doping profile extraction.
2.1 P-N junction Device Physics
The P-N junction is one of the simplest devices of all semiconductor devices and it is of
greatest importance in modern semiconductor studies. This is because such junctions
form the heart of most rectifiers, transistors and photocells [5]. A P-N junction is simply
a junction of identical semiconductor but different doping. It is formed by doping donor
atoms on one side (N-side) and doping acceptor atoms on the other (P-side). Doping
agents can be introduced by diffusion at high temperature or by ion implantation. Ion
implantation has many advantages over diffusion and making it a much more popular
process as compared to diffusion [6].
Since P-N junction is the simplest of all semiconductor devices, having developed a
method of extracting doping profile for P-N junctions, the same method could be easily
extended to other more complicated devices like transistors. Therefore, the device under
test (DUT) chosen for this thesis is P-N junctions. It is essential to have a good
knowledge of the P-N junction physics and its reaction under applied voltage bias. As a
result, this section provides an in depth review of the basic P-N junction device physics.
- 5 -
Chapter 2 Theoretical Background
2.1.1 P-N junction in Thermal Equilibrium
Figure 2.1.1:Energy band diagram P-N junction in thermal equilibrium[7]
Figure 2.1.1 shows the energy band diagram of a P-N junction in thermal equilibrium.
By presenting the energy band diagram, it provides a deeper insight into the electrons
and holes transport of the P-N junction can be observed as it introduces the energy
dimension [7].
The first diagram shows a chemical-bond presentation with electrons and holes in the N-
type and P-type neutral regions as well as donor and acceptor ions in the depletion
region. Electrons diffusing from the N to P-side leave behind uncompensated donor ions
in the N-material. Similarly, holes leaving the P-region leave behind uncompensated
electrons holes
- 6 -
Chapter 2 Theoretical Background
acceptor ions. Therefore, as shown in the diagram, there is a region of positive space
charge near the N-side of the junction and negative charge near the P-side of the
junction. The depletion layer is created by the positive and negative charge caused by
electron-hole recombination.
For the P-N junction to be in thermal equilibrium, the current flowing through the
circuit is zero. This is shown in the band diagram, where electrons drift from the P-side
is cancelled by the electron diffusion from the N-side and vice versa for hole drift and
diffusion for the P-side. These four components combines to give zero net current flow
[7, 8].
2.1.2 P-N Junction in Forward bias
Figure 2.1.2:Energy band diagram P-N junction in forward bias [7]
- 7 -
Chapter 2 Theoretical Background
As shown in Figure 2.1.2, when P-N junction is in forward bias, the barrier height is
reduced by -VD. For an increase in forward bias voltage VD, the barrier height is
lowered. Therefore the number of majority carriers able to go over the barrier in the
depletion layers increases as well. This also means that the current of the majority
carriers flowing through the depletion layer is increased with an increase in forward bias
VD. This current flow is the diffusion current and will be much larger in magnitude to
the corresponding drift current [7].
The increase in the current of majority carriers means that the P-N junction is
conducting current thus implying that the conductance is high. The capacitance of
interest for P-N junction in forward bias is the transition-region capacitance. This
capacitance effect of the P-N junction will be discussed separately in chapter 2.1.4.
2.1.3 P-N Junction in Reverse Bias
Figure 2.1.3:Energy band diagram P-N junction in reverse bias [7]
- 8 -
Chapter 2 Theoretical Background
When P-N junction is in reverse bias, there are some reactions on the P-N junction
physics which makes it possible for doping profile extraction. …………………..The
depletion width dependence on reverse bias is one of such reactions and this reaction
allows doping profiles to be extracted. How this dependence enables doping profile
extraction will be discussed in Chapter 2.2.
As mentioned earlier, when the P-N junction is in thermal equivalent, there is a
depletion width formed by the donor and acceptor ions. When a reverse bias voltage is
applied to the P-N junction as shown in Figure 2.1.3, more electrons and holes are
attracted to the contact. As a result, more donor and acceptor ions appear at the
depletion region which in turn increases the depletion width. And as the reverse bias
voltage increases, the depletion width increases as well. This is the cause of the
depletion width dependence on reverse bias voltage which is the key to conventional C-
V doping profile extraction.
Due to the bias voltage, the P-N junction is no longer in thermal equilibrium. This also
means that there must be a current flow that works to bring the system back to
equilibrium. Referring to Figure 2.1.3, minority carriers can easily pass through the
junction as shown in the band diagram and the majority carrier is unable to overcome
the energy barrier. Compared to the equilibrium case, this minority carriers flow is not
compensated by electrons flow from the N-side and holes flow from the P-side. This
movement of minority carriers, often called leakage current created is very little. This
current flowing through the reverse-biased P-N junction does not increase with the
reverse bias. This current does not affect doping profile extraction greatly and will be
ignored [7].
- 9 -
Chapter 2 Theoretical Background
2.1.4 Capacitance Effect on P-N junctions
As discussed earlier, the depletion width dependence on bias voltage on P-N junction is
the key to doping profile extracting using the conventional technique. Capacitance of P-
N junction is the key to the work in this thesis hence will be studied in detail. There are
two types of capacitances associated with P-N junction. They are:
1. Depletion layer capacitance or transition-region capacitance Ct. This
capacitance is due to dipole in transition region.
2. Charge storage capacitance or diffusion capacitance Cd. This capacitance
arises from lagging behind of voltages as current changes.
Cd is proportional to the D.C operating current where the Ct is a function of the applied
voltage. On top of that, Cd is only significant under forward bias when direct current is
flowing which makes Ct a very ‘lossy’ capacitance. Ct on the other hand, is mainly of
significance under reverse bias [9].
The responses of the two capacitances differ at high frequency. That is the reason how
selection of measurement frequency affects the measured capacitanc. Diffusion
capacitance effect involves the movement of minority carriers. For this reason, there is a
delay between a change of applied voltage and the corresponding movement of charge.
This implies that the diffusion capacitance, Cd is sensitive to the measurement frequency.
As for the transition-region capacitance, it only involves the movement of majority
carriers which respond immediately to potential changes. As such, measurement of Ct is
the same up for all frequencies [9].
- 10 -
Chapter 2 Theoretical Background
2.1.5 Capacitance Measurements on P-N junctions
A P-N junction consists of a junction conductance G, series resistance rs and junction
capacitance C. Actual circuit of a P-N junction is in Figure 2.4.1 (a).
Figure 2.4.1: P-N junction in (a) Actual circuit, (b) Parallel equivalent circuit and (c)
Series equivalent circuit [10]
LCR (inductor L, capacitor C and resistor R) meters are commonly used to measure
capacitance of semiconductors devices. When making measurements of capacitance, the
LCR meter assumes that the device measured to be represented by parallel equivalent
circuit in Figure 2.4.1 (b) or series equivalent circuit in Figure 2.4.1 (c). This means that
when measuring capacitance CP using the parallel mode, there is a conductance GP in
parallel with the capacitance.
The measured capacitance, CP on a P-N junction is not the true capacitance of the
junction. And for the parallel equivalent circuit configuration, the measure capacitance
is given by [10]
22 )2()1( CfrGrCC
ssp π++= ---------Equation 2.1
(a) (b) (c)
- 11 -
Chapter 2 Theoretical Background
Where G is the conductance, rs is the series resistance and f the measurement frequency.
For P-N junction in reverse bias, conductance can be relatively low and the condition
rsG ⟨⟨ 1 is generally satisfied and Equation 2.1 is simplified to
2)2(1 CfrCC
sm π+
= ---------Equation 2.2
Equation 2.2 is commonly used for determining rs. In this thesis, these equations are
presented to show that measured capacitance is dependent on conductance. For P-N
junction is forward bias, conductance is high therefore capacitance of P-N junction
cannot accurately measured when the device is in forward bias [10]. How accurate
measurements of capacitance on P-N junctions will be discussed in Chapter 3.
Theory of P-N junction, P-N junction under different conditions and measurement of P-
N junctions has been discussed. Next, the convention C-V technique will be discussed.
How doping profile can be obtained from the capacitance measurement will be
explained.
- 12 -
Chapter 2 Theoretical Background
2.2 Conventional C-V Technique on P-N junction
This section provides a qualitative review of the conventional C-V technique. The
capacitance-voltage (C-V) method for one-dimensional doping profiling was discovered
by Schottky in 1942. Ever since, this has been a popular technique for doping profile
extraction. The advantages of the C-V- technique will be discussed showing why the C-
V technique is such a popular method.
Following that, an in depth discussion of the physics behind the C-V profiling technique
and key equations are explained showing why capacitance from P-N junction can be
used to extract doping profile of P-N junction. Assumptions made to derive those
equations will be discussed. These assumptions will be discussed as well. These
discussions will lead to the problems present in the C-V technique and the limitations to
the extracted doing profile using this method.
2.2.1 Advantages of the Conventional C-V Technique
The C-V (Capacitance-Voltage) technique has several desirable advantages in which
made it one of the most popular methods to extract doping profile of semiconductor
devices. The advantages are [10]
1. It is a simple technique where not many equipment are required for extracting
the capacitance and voltage.
2. Measurements can be taken directly from the device in which doping profile
needs to be evaluated
3. Doping profile can be extracted with little data processing.
4. It is a non-destruction method as the device is not damaged after measurement.
5. It is well established with available commercial equipment.
6. Its depth profiling capability is extended significantly for the electrochemical
profiling method.
- 13 -
Chapter 2 Theoretical Background
It is due to these advantages that made the conventional C-V technique popular. Next,
the theory and derivations of key equations the conventional C-V technique requires
will be discussed.
2.2.2 Theory of the Conventional C-V Technique
In 1942, W. Schottky pointed out that impurity distribution can be determined from the
C-V measurement. Until now, this method, commonly called the C-V technique is
widely used to determine impurity distribution of doping profiles of semiconductors
devices. The C-V technique exploits dependence of width of a space-charge region by a
reverse bias. This dependence made possible the C-V profiling method on Schottky
barrier diodes, P-N junctions, MOS capacitors and MOSFETs [10].
This section will first discuss the electrons and holes movement under a bias voltage,
and how this movement causes the depletion width dependence with regards to a bias
voltage. Next, derivations of key equations required for doping profile extraction using
this technique will be explained.
Figure 2.2.1: An asymmetrically doped P-N junction under bias condition
Let’s consider the asymmetrically doped junction shown in Figure 2.2.1. The figure
shows a DC voltage bias VB is applied to the N-side and the P-side connected to ground.
When VB is negative (P-N junction is reverse bias) electrons are attracted to the P-side
contact, holes are attracted to the other contact. As a result, there are more positive
VB
Vac
P
W
- Negative acceptor ions
N+
- Positive Donor ions
- 14 -
Chapter 2 Theoretical Background
donor ions on the N-side, and negative acceptor ions on the P-side appearing at the
depletion layer (with reference to the P-N junction in equilibrium).
For VB that is more negatively biased, more holes and electrons are attracted to the
contacts. This results in an increase in the positive donor and negative acceptor ions at
the depletion region. This increase in negative bias eventually extends the depletion-
layer width which in turn increases the depletion-layer charge. The reverse bias
eventually produces a space-charge region (scr) of width W. If the N+-side is 100 times
more heavily doped than the P-side, thus scr spreading into the P-side can be neglected
[7]. This is the reason why doping profile extraction using the conventional is limited to
the less highly doped side. The differential capacitance C is given by [10]
dVdQ
C s−= ---------Equation 2.1
Negative sign accounts for more negatively charge in the semiconductor scr and Qs is
the semiconductor charge increment. In order for the P-N junction to have overall
charge neutrality, sdQ is given by [10]
dWWqANdQ As )(−= ---------Equation 2.2
In order to arrive in equation 2.2, several assumptions were made. They are:
1. Depletion approximation - Mobile carrier densities p and n are assumed to be
zero in the depleted scr.
2. NA is assumed to be zero for the N-type substrate.
3. All acceptors and donors are assumed to be fully ionized at the measurement
temperature [10].
These assumptions are crucial because if acceptors or donors are not fully ionised, the
true doping density profile may not be extracted. Combining Equation 2.1 and 2.2, we
get [10]
- 15 -
Chapter 2 Theoretical Background
dVdWWqN
dVdQC A
S )(=−
= ---------Equation 2.3
In order to arrive at Equation 2.3, the term dV
WdN A )( is neglected or is assumed to be
zero. This assumption implies that NA does not vary over the distance dW. This also
means that the variation of NA over distance dW cannot be obtained with the C-V
technique [10].
The capacitance off a P-N junction is given by
WAK
C osε−= ---------Equation 2.4
Where mFXXK oS /1085.87.11 12−=ε , A is area of the P-N junction and W is width of
the depletion layer. From Equation 2.4, we can see that capacitance of P-N junction is
dependent on KS, dielectric constant of silicon, area of the device and depletion width.
Differentiating equation 2.4 with respect to voltage and substituting dVdW into equation
2.3 gives [10]
dVdCAqKs
CWNo
A2
3
)(ε
−= ---------Equation 2.5
Equation 2.5 can also be written as
dVCdAqKs
WN
o
A )/1(2)( 2
2ε−= ---------Equation 2.6
Equation 2.4, 2.5 and 2.6 are the key equations for doping profile extraction. In equation
2.5 and 2.6, the area of the device A is squared. Hence this makes the doping profile
- 16 -
Chapter 2 Theoretical Background
extraction using this method requires device area to be precisely known for accurate
doing profiling [10]. An example of consistence set of units is:
C = farads
W = centimetres (width of space charge region)
A = centimetres square
q = 1.6 X 10-19coulombs
oε = 8.85 X 10-14 farads/centimetre
KS = 11.7 (dielectric constant of silicon which is dimensionless) [11]
The set of constant units will prevent any errors to be made when using the C-V
technique to extract doping profile of P-N junctions. However, in the later part of the
thesis, these units need to be altered to coincide with the units used in device simulation.
Having discussed the theory of the C-V technique, it is obvious how doping
concentration of the lightly doped P-region can be obtained from a measurement of
capacitance. It would be of interest to take note that these equations were obtained by
assuming a one sided junction. By saying one sided junction, the junction is said to have
one side to be much more heavily doped than the other. Certain modifications must be
made in the case of a graded junction. However, this is not a major concern as most
semiconductor device or P-N junction have sharp step junctions [10].
From the discussion, it can also be deduced that several assumptions were made and
dependence of the C-V technique on parameters like area of devices. This leads to the
discussion of the disadvantages and limitations of the C-V technique in next section.
2.2.3 Disadvantages and Limitations of the Conventional C-V Technique
There are several limitations and disadvantages the C-V technique possesses preventing
doping profile of devices to be accurately determined. These disadvantages must be
identified so as to find the faults and thus improving or eliminating them. The
disadvantages and limitations of the convention C-V technique are [10]
- 17 -
Chapter 2 Theoretical Background
1. It can only extract doping profile of junction in reverse bias, where
conductance is small/negligible.
2. It is an approximation and only works for abrupt junctions.
3. The doping profile near the junction cannot be extracted due to the zero bias
space-charge region width.
4. The extracted profile is limited in depth by the voltage breakdown of the
device. This is serious in heavily doped regions.
5. It has limitation to the Debye limit.
6. It can only extract doping profile of the less highly doped side.
7. Area of device cannot always be accurately determined which affects the
doping profile extracted.
As shown, there are many disadvantages to the conventional C-V technique. Also the
limitations prevent doping profile to be extracted accurately. Subsequence chapters will
go on and explain how these limitations are overcome using the inverse modelling
approach.
- 18 -
Chapter 3 Inverse Modelling
Chapter 3
Inverse Modelling
3.1 Introduction to Inverse Modelling
Inverse modelling, or reverse engineering, is a general terminology in which the interim
physics and related phenomena are guessed from final results. It is widely used in all
area of studies including engineering. In this thesis, discussion of inverse modelling will
be limited only to semiconductor industry.
Crank et al. is one of the first to use inverse modelling for use in process/device
simulation or TCAD [12, 13].This chapter will discuss the advantages of inverse
modelling followed by existing application to inverse modelling. Finally, application of
inverse modelling to this thesis will be discussed.
3.1.1 Advantages of Inverse Modelling
Inverse modelling is popular in semiconductor industry due to its three major
advantages.
Firstly, inverse modelling enables simulators to be calibrated. For example, the physical
model parameters for processes and device characteristics can be calibrated. This
includes the in situ extraction of material parameters and geometrical parameters [14].
Secondly, inverse modelling enables process and device characteristics to be predicted.
This is commonly implemented with the use of simulators. However, simulators are
hardly calibrated and in some cases even not at all. Consequently, in those cases very
disappointing results are obtained and people are downgrading the importance of
simulations. In this thesis, with the 2-dimensional device simulator ATLAS, the inverse
modelling approach could be implemented to predict the device characteristics, in this
case the doping profile [14].
- 19 -
Chapter 3 Inverse Modelling
Thirdly, inverse modelling is also used to optimize processes, device characteristics and
circuit performance. In fact, this inverse modelling approach can be extended to
complete fabrication processes. In recent papers, this inverse modelling has been
extended for accurate 2 dimensional doping profile extraction for Metal Oxide Silicon
Field Effect Transistor, MOSFET’s [14].
Having discussed the advantages of inverse modelling, it is apparent why inverse
modelling have been chosen for doping profile extraction in this thesis. The next section
will discuss how researchers utilize inverse modelling for doping profile extraction.
3.1.2 Existing Application of Inverse Modelling
There are so many applications of inverse modelling to list. In this section, an existing
method of doping profile extraction via inverse modelling will be discussed.
Two-dimensional dopant profile extraction for MOSFET’s was demonstrated by C.Y.T.
Chiang and Y.T. Yeow by treating the source/drain-to-substrate junction as a gated
diode. In that paper, the small-signal capacitance of the diode measured as a function of
gate and source/drain bias is used as the target to be matched in an inverse modelling
process. The inverse modelling algorithm was written in MEDICI, a 2-D device
simulator [15].
This is one of the many applications where inverse modelling was applied to solve
problems. How inverse modelling is applied in this thesis for doping profile extraction
will be discussed next.
3.2 Basis of Forward Modelling
Before looking into inverse modelling or reverse engineering, it would be of interest to
introduce forward modelling. This will provide help in understanding inverse modelling.
- 20 -
Chapter 3 Inverse Modelling
Forward modelling is generally used in semiconductor device simulation such as
ATLAS and ATHENA. Devices are fabricated and the numerical simulations performed
in order to extract the desired results from the simulation. This is shown in Figure 3.2.1.
Figure 3.2.1: Flow chart for forward modelling to extract electrical characteristics of
semiconductor devices
Figure 3.2.1 shows a standard process of how forward modelling process is
implemented to extract electrical characteristics of devices. Here, the discussion will be
based on ATHENA and ATLAS as these are the main software for semiconductor
device fabrication and simulation.
Firstly, the device is fabricated in ATHENA. Each of the fabrication process like doping
of impurities, oxidation, etching etc are process to fabricate the device. Next, a device
simulation is run in ATLAS to extract electrical characteristics like C-V response of the
device.
This is the basis of forward modelling process. For inverse modelling, slight
modifications are made to this process. These changes will be discussed next, explaining
how inverse modelling is implemented in this thesis to solve problem.
Start
Fabricate Device
(ATHENA)
Numerical Simulation (ATLAS)
Extract simulation results (For example threshold
voltage)
Stop
- 21 -
Chapter 3 Inverse Modelling
3.3 Implementation of Inverse Modelling
In Figure 3.2.1 the forward modelling process, the fabrication process for the device is
known. The simulation result obtained after device simulation is the required result.
However, in this thesis, the problem is treated as a “black box” whose outputs
(experimental C-V curves) are known but whose inputs (the doping distributions) must
be found. In practice, the computer program most often enlisted for help in the search
for appropriate doping coefficients is a Levenberg-Marquardt nonlinear least-squares
solver [4].
ATLAS, a device simulation tool from SILVACO is used in this thesis for defining the
device. Numerical simulation of the device is also done in ATLAS. This part of the
thesis will go on and examine the implementation of the ATLAS for inverse modelling
of the thesis. Figure 3.3.1 shows the flowchart of the inverse modelling process used in
this thesis.
- 22 -
Chapter 3 Inverse Modelling
Figure 3.3.1: Flowchart of the inverse modelling process used in this thesis.
The first step of the inverse modelling process is to fabricate the device. This involves
defining a structure of the P-N junction in ALTAS. By this, it also refers to ‘fabricating’
the P-N junction just that the exact fabrication process is unknown and the P-N junction
is defined by several assumptions. This includes assumption for the doping profile for
the P-N junction.
Initial guess for doping profile
Numerical Simulation (Generate C-V curve)
Superimpose measured and simulated C-V plot
Did the two C-V curve matches
well?
Yes
No Adjust parameters doping parameters
for device
Device Fabrication
Start
Extracted Profile
Stop
- 23 -
Chapter 3 Inverse Modelling
In this thesis, a suitable doping profile model (Gaussian) has been chosen for the doping
profile of the more highly doped side. This is because modern semiconductors
fabrication process used ion implantation which corresponds to the Gaussian profile
assumed. Gaussian distribution of doping profile obeys this equation
∆
−−
∆= 2
2
)(2)(
exp2
)(p
p
p
d
RRx
RN
xNπ
---------Equation 5.1
Where dN is the Gaussian peak doping, pR∆ is the projected range and pR is the
projected range. A P+N junction is fabricated and a numerical simulation is used to
evaluate the junction capacitance for the assumed profile. The parameters dN , pR∆ and
pR will be adjusted in the inverse modelling process at each iteration.
Having made the assumption for the initial doping profile, the device is created. The
next step is to perform a numerical simulation on the device created. An A.C simulation
will be performed which allows C-V response of the P-N junction to be extracted. The
results from the simulation, the C-V response of the P-N junction is compared with the
measured C-V response of the device. Before comparing the two C-V curves, the
capacitance of both methods must be converted to capacitance per unit area for
consistency. This is because the simulated capacitance is in capacitance per unit width
where else the measured capacitance is in capacitance only. Hence for matching
purposes, both the measured and simulated capacitance has been converted to per unit
area.
All conversion for the capacitance to per unit area is done in Excel.
The combined plot of the two curves can be viewed in Excel. This will show clearly
whether the two curves matches well. Whenever the two curves do not agree, the
parameters dN , pR∆ and pR are adjusted and the device is fabricated again. The C-V
response from simulation is once again obtained and checked if it fits well with the
measured C-V response.
- 24 -
Chapter 3 Inverse Modelling
This process of repeatedly altering the parameters is carried out until the best fit of the
two C-V curve is obtained. The doping profile of the simulated P-N junction that has the
C-V response that provide the best fit with the measured C-V curve is deemed to
possess the doping profile same as the actual P-N junction.
This is how the device simulator ATLAS used in the inverse modelling approach in this
thesis. The inverse modelling approach used to extract doping of P-N junction has been
described. The results and accuracy of the inverse modelling approach will be discussed
in Chapter 6.
- 25 -
Chapter 4 Setup of Equipments and Software Coding
Chapter 4
Setup of Equipments and Software Coding
This chapter provides an overview on the technical design and description of the
equipment and software used in this thesis. Two main parameters to be measured in this
thesis are capacitance and voltage. A Hewlett Packard (HP) 4275A LCR Meter and a
HP 4825 Multi-meter is used to measure the capacitance and voltage respectively.
Accurate measurement on the device under test is crucial for accurate extraction of
doping profiles. Hence this chapter will first talk about how these two equipment are
setup for measurement.
Subsequently, the program written in LABVIEW used to control the LCR and multi-
meter will be discussed. This program controls the main functions of the two meters and
performs an average on the parameters measured to reduce measurement noise. The
program then saves averaged data for later processing.
Lastly, the simulation done in a device simulator SILVACO (ATLAS) will be discussed.
The simulator performs device simulation and the inverse modelling to extract the
doping profile.
Equipment/software Function
HP4275A LCR Measures capacitance of the P-N junction.
Supply bias voltage to the P-N junction.
HP4825 Multi-meter Measures voltage of the P-N junction.
LABVIEW program Controls the two meters and measures the capacitance and
voltage.
Record and plot the measured results.
SILVACO, ATLAS Perform device simulation and the inverse modelling to extract
the doping profile.
Table 4.1: Summary of equipment and respective function
- 26 -
Chapter 4 Setup of Equipments and Software Coding
4.1 Setting up the HP4275A LCR Meter
This section will first provide a brief introduction to the HP4275A LCR meter.
Subsequently, setting up the HP4275A LCR Meter for accurate measurement of
capacitance will be explained. Finally, effectiveness of the LCR meter used for
capacitance measurement will be reviewed.
The HP4275A LCR meter is a general purpose meter used to measure inductor (L),
capacitor(C) and resistor (R). The LCR meter has a built-in power supply and is capable
of supplying the bias voltage required for the P-N junction. In this thesis, the LCR meter
serves two main functions. They are to measure the capacitance of the device and to
supply the required voltage bias across the junction. The LCR meter is controlled by a
personal computer (PC) using a LABVIEW program. The PC is connected to the LCR
meter via GPIB interface and controls the operation of the LCR meter. This program
will be discussed in later section.
Figure 4.1.1 shows the equipment setup used in this thesis. The LCR meter is connected
to the PC via GPIB interface. The LCR meter is then controlled by a program written in
LABVIEW. For illustration purpose, the figure shows the four probes connected
directly to the device under test which is not the actual connection.
For accurate measurements, the lid of the die cast box must be covered at all times. This
is because when a semiconductor is irritated by light, electrons can be excited from the
valence band into the conduction band by the absorption of protons, provided the photon
energy is greater than Eg [16]. Where Eg is the energy of the band gap.
- 27 -
Chapter 4 Setup of Equipments and Software Coding
Figure 4.1.1: Equipment setup for the thesis
In fact, the actual connection of the LCR meter has the two high terminals of the LCR
meter connected to the high probe of the die-cast box and the two low terminals
connected to the low probe of the die-cast box. This can be seen from Figure 4.1.2.
Figure 4.1.2: The HP 4275A LCR meter connections to the die cast box.
High-Probe Low-Probe
N-Type
P-Type
N+
HP4275A LCR meter
HP4825 Multi-meter
DC bias Monitor
PC LABVIEW controlled
GPIB Interface
HP 4275A LCR meter
Die-Cast box
Coaxial cables
T-connector
- 28 -
Chapter 4 Setup of Equipments and Software Coding
As shown in Figure 4.1.2, the LCR meter has four terminals, HC, HP, LC and LP. The
two H terminals are connected to a T-connector on the die cast box via coaxial cables.
This is the same case for the two L terminals. Photograph of the setup of equipments
used in this thesis is shown in Appendix I.
Capacitance of the P-N junction must be accurately measured in order to obtain accurate
doping profile. Therefore it is essential to make sure that measurement of the
capacitance is accurate. There are many procedures and precautions to take note when
using the LCR meter. Precautions to take note when making measurements on
capacitance of P-N junction are as follows:
1. The LCR meter requires a warm up time of thirty minutes.
2. The device under test is to be placed in a die-cast box, the DUT is keep
clear from light and electromagnetic interferences which might influence
measurement of the capacitance.
3. ‘Short’ and ‘open’ circuit zeroing for the LCR meter to minimize stray
capacitance.
4. Setting of measurement frequency at 1 MHz and the A.C voltage
superimposing on the D.C voltage at 50mV.
5. The cables used for connecting the LCR meter to the die-cast box are
coaxial cable to reduce stray capacitance and external noise.
6. The selection of cable length on the LCR meter should correspond to the
physical cable length used. Cable length of less than one meter is
preferred as addition cable lengths add on the stray capacitance.
7. Probe pressure acting on the DUT must be optimum. Sufficient pressure
is needed to have a good contact for consistence capacitance
measurement. On the other hand, probe pressure must not be too great to
cause ‘shorting’ of the probes.
8. Once measurement procedure is initiated by the LABVIEW program, all
equipments including cables should be left undisturbed. This will ensure
a consistence stray capacitance throughout the measurement of the
device.
- 29 -
Chapter 4 Setup of Equipments and Software Coding
9. Setting resolution “On” enables the LCR meter to take ten measurements
automatically and display the average result.
These are the precautions taken during measurement of capacitance of the device under
test in this thesis. Having followed these precautions, measurement of the capacitances
is found to be accurate and repeatable. The measured capacitance is repeatable up to
1pF. This accuracy for the capacitance does not hold for bias voltage greater than
positive 0.5 volts.
4.2 Setting up the HP4825 Multi-meter
Referring to Figure 4.1.1, the HP4825 multi-meter is connected to the D.C Bias monitor
of the LCR meter. The applied voltage that the LCR meter produces is not a true voltage
across the device. Hence the multi-meter monitors the voltage across the junction and
extracts the true voltage across the junction. Like the LCR meter, the multi-meter is
controlled by the LABVIEW program. At every voltage step, the multi-meter measures
and outputs the measured voltage as controlled by the LABVIEW program.
The voltage measured using the multi-meter is found to be repeatable up to 0.03 volts.
4.3 Description of the LABVIEW Program
As mentioned previously, equipments used in this thesis are controlled by program
written in LABVIEW. The LCR meter and multi-meter are connected to the personal
computer through GPIB interface. The purpose of the program in LABVIEW is to
control the functions of the LCR meter and the multi-meter. The operating sequence of
the program is best explained with the help of a flowchart.
- 30 -
Chapter 4 Setup of Equipments and Software Coding
Figure 4.3.1: Flow chart showing operation of the LABVIEW program
Graphical User Interface
Measure C and V
Yes
No
Take average V and C for 5 samples
Input voltage range and compute number
of steps, X
5 reading for every data
point?
Store C and V average into file.dat
Completed X No. of
steps?
Yes
No
Start
Plot C-V curve
Stop
- 31 -
Chapter 4 Setup of Equipments and Software Coding
The program first starts with a Graphical User Interface (GUI) with several controls as
shown in Figure 4.3.2. On the top left side of the GUI, it has a start and stop text box.
Entering -5 for the start and 5 for the stop will set the LCR meter to supply a bias
voltage from -5 to 5 volts. The size of the voltage step for measurement can also be
entered as shown in the figure. By allowing a larger step size, measurement time can be
reduced. This larger step size can be used to determine whether the device under test is a
N-P-N or a P-N-P transistor with a much smaller measurement time. The method of
determining whether the device is P-side or N-side will be explained in chapter 5.
The program will initialise various settings on the LCR meter. Settings like the
measurement frequency and the multiplier for A.C voltage for the experiment to be run
can be controller using the program. From voltage range specified by the user, the
program will calculate the number of steps required to run the measurement. When the
program is running, the current step number will be indicated, this allow user to estimate
how long more does the program has to run.
Following a stabilizing time for the device and equipment, the capacitance and voltage
across the junction are measured by the LCR meter and multi-meter respectively. A loop
is created allowing each data point to be measured five times and then average so as to
reduce measurement noise. Each of the five capacitances and the five voltages are
displayed on the right hand side of the GUI. The program then calculates the average of
these values and stores them into a file for processing. With such precautions,
measurements taken from the equipments setup are accurate and repeatable up to 1 pF
for the LCR meter and 0.03 volts for the multi-meter.
The program will then collect all data points for the voltage range specified by the user.
As shown in the flowchart, the saving and averaging of the data points is repeated every
voltage step. As such, at the end of the measurement, the program can output the result
into a file for processing. Although LABVIEW is capable of processing the data,
Microsoft Excel is preferred and used in this thesis for processing of data. After
collecting all data, the program will than plot the C-V curve using the data points
obtained. This provides a clear view of the measured data points before processing them
- 32 -
Chapter 4 Setup of Equipments and Software Coding
in Excel. The program has a graphical user interface as shown in the Figure 4.3.2 below.
(Please refer to APPENDIX II for the source code for the program.)
Figure 4.3.2: Graphical user interface of the program written in LABVIEW
4.4 Device Simulation software ATLAS
A device simulation software ATLAS was been chosen for device simulation in this
thesis due to its capabilities and availability. As the fabrication process of the device
used in this thesis is unknown, the device structure can be defined by making
assumptions to the device structure.
ATLAS is a versatile, modular and extensible solution for one, two and three
dimensional device simulation. It has comprehensive capabilities but for the purpose of
this thesis, only those of interest would be discussed. The functions of ATLAS in this
- 33 -
Chapter 4 Setup of Equipments and Software Coding
thesis are to define the device structure and to perform the required device simulation on
the device. These functions of ATLAS will be discussed next [17].
4.4.1 Numerical Device Simulation in ATLAS
As explained earlier, the fabrication steps of the device under test is unknown.
Therefore, it is not required to go through the fabrication steps in ATHENA. ATHENA
is a simulator that provides general capabilities for numerical, physically-based, two
dimensional simulation of semiconductor processing [17]. The device under test in this
thesis is a P-N junction. Hence, in this thesis, a P-N junction will need to be defined in
ATLAS. Only after the device is defined, then can numerical simulation be run so as to
extract the desired parameters [17].
Firstly, the mesh is created by specifying the regions and materials. It is important to
select an optimum mesh as this would affect computation time and accuracy. For
instance, setting a gird that is too fine will require too much computation time. And in
some cases, abnormal termination will result when performing numerical simulation on
the device. On the other hand, if a grid is set too coarse, precision of the results will be
affected when performing numerical simulation.
Next, electrodes need to be specified. These electrodes will be used as reference when
conducting numerical simulations. Finally, doping distribution to the structure can be
specified. Doping distribution of the P-N junction can be specified by specifying a
specific distribution type for the P-side and the N-side. Common doping distribution for
semiconductor device has a Gaussian distribution. The device used in this thesis is a P-
N junction has a uniform doped P-type anode and an N+ cathode. The N+ cathode has a
Gaussian doping which corresponds to ion implantation process in modern
semiconductors fabrication process as explained in chapter 2.4.
Having defined the device, the next step is to perform a numerical simulation on the
device to obtain C-V response to perform the inverse modelling process. The inverse
modelling process is an important part of this thesis and would require a chapter by
- 34 -
Chapter 4 Setup of Equipments and Software Coding
itself. The inverse modelling process has been explained in Chapter 3, and the results
from inverse modelling will be discussed in Chapter 6. There are a number of numerical
solution techniques provided by ATLAS for calculating solution to semiconductor
devices. It is important to choose the correct numerical solution technique so as to
obtain correct solutions. The details of the solution techniques can be found in the
ATLAS user manual [17].
Small-signal A.C solutions must be specified in order to obtain the C-V plot of the
device. The syntax required for small-signal A.C solutions is simple. Adding an A.C
flag and a small signal A.C frequency to the existing D.C ramp is sufficient. Where D.C
ramp is the range of voltage the simulator is set to run for D.C solution [17].
The results from the numerical simulation will be displayed using TONYPLOT.
TONYPLOT is a graphical post processing tool for use with all SILVACO simulators.
The results are displayed using TONYPLOT and then export to Microsoft Excel for
processing. (Please refer to APPENDIX III for the source code written in ATLAS)
Here, the basis steps of defining the device and numerical simulation of the device has
been described. As mentioned earlier, the inverse modelling process done in ATLAS
has been discussed in Chapter 3.
- 35 -
Chapter 5 Discussion of Measurement Results
Chapter 5
Discussion of Measurement Results
This chapter presents the results obtained from the experiment. The C-V measured from
the experiment will be discussed first followed by doping profile extraction using the
conventional C-V technique.
5.1 C-V Measurement from LABVIEW
The P-N junction in which doping profile will be evaluated in this thesis is obtained
from a BJT transistor. The specimen is placed in the die cast box and measurements are
made as described in chapter 3. Figure 5.1.1 shows the C-V response of the result
measured from the LABVIEW program.
Measured Capacitance Versus Voltage
0.E+00
5.E+02
1.E+03
2.E+03
2.E+03
3.E+03
-6 -5 -4 -3 -2 -1 0 1
Measured Bias voltage(VB)
Mea
sure
d C
apac
itanc
e(pF
)
3x103
2.5x103
2x103
1x103
5x102
0x100
Figure 5.1.1: Measured capacitance versus voltage of the P-N junction under test
- 36 -
Chapter 5 Discussion of Measurement Results
Figure 5.1.1 shows that a higher reverse bias produces a lower capacitance due to a
larger depletion width. For higher reverse bias, more electrons are attracted to the N-
side, holes attracted to the P-side. This results in increase in the positive donor and
negative acceptor ions at the depletion region, which eventually increase the depletion
width. As the bias voltage increases (smaller reverse bias), the capacitance increases as
well. This C-V response matches well with the typical C-V response of P-N junction in
reverse bias.
At VB=0.4V, it can be seen that the capacitance starts to decrease, this is this is where
the diode starts to switch on. In order to achieve accurate doping extraction,
measurements of capacitance and voltage on the device needs to be accurate. This is
ensured with the precautions mentions in section 4.1 and 4.2.
From the C-V measurement, it can be determined that the transistor has a P-type base,
N-type emitter and base. From the knowledge of BJT fabrication process, it is known
that the emitter is last implanted and is always the most highly doped. Therefore it can
be determined that the P-N junction which doping profile has to be determined is a P-N+
junction. This can be seen from Figure 5.1.2.
Figure 5.1.2: Structure of a typical BJT transistor
High-Probe
Low-Probe
N-Type
P-Type
N+
- 37 -
Chapter 5 Discussion of Measurement Results
Figure 5.1.3: Photograph of the device under test
Figure 5.1.3 shows the wafer under magnification using an electron microscope. The
emitter and the base are shown in the figure. The collector is under the emitter and base,
that is why the collector cannot be seen on the picture. For presentation purpose, a layer
of carbon is applied on the surface to enhance the contrast of the picture. This layer of
carbon damages the wafer and will prevent the C-V technique from being non-
destructive as claimed before. However, this is not necessary for the area of the device
to be determined where picture of such quality is not necessary.
As mentioned in Chapter 4, the area of the device has to be precise in order to extract
accurate doping profile. The area of the device under test is determined accurately by
enlarging the device under an electron microscope and taking a photo of it. The area of
Emitter
Base
- 38 -
Chapter 5 Discussion of Measurement Results
the device is simply the area of the emitter that is in contact with the base. This is
assumed to be the middle between the emitter and the base Figure 5.1.3 above. The area
of the device is found out to be 3.94 mm2.
The area obtained here is reasonably accurate. Despite magnifying the device and
carefully determining the area, the effective area still cannot be determined accurately.
This is due to the lateral space-charge region spreading with a change in bias voltage.
This change in effective area causes the effective doping density to vary as well. As
such, the area of device cannot be accurately determined. This shows the limitation of
the conventional C-V technique.
In this section, the P-N junction has been identified as a P-N+ junction from the C-V
measurement. Area of the junction has been calculated as well. Before discussing how
doping profile can be extracted from the C-V measurement, the C-V response of the
device under different frequency and A.C voltage shall be discussed.
- 39 -
Chapter 5 Discussion of Measurement Results
C-V plot at different frequencies
0.E+00
2.E+03
4.E+03
6.E+03
8.E+03
1.E+04
1.E+04
-6 -5 -4 -3 -2 -1 0 1
V(volts)
Cap
acita
nce(
pF)
Frequency at 10kFrequency at 100kFrequency at 1M
1.5x104
1x104
8x103
6x103
4x103
2x103
0x100
Figure 5.1.4: C-V response under different frequencies
Figure 5.1.4 shows the P-N junction C-V response under different frequencies. When
the frequency is low (10 kHz and 100 kHz), the capacitance for reverse bias does not
have significant differences. As compared to the C-V response at 1MHz, the capacitance
for 1 MHz is a little lower. This because deep-level impurities in the space charge
region will cause the capacitance to be frequency dependent because of their finite
charging and discharging time [10, 18].
If high level impurities are present, high-frequency capacitance will be less than the
low-frequency capacitance up to 30 to 50%. Here the difference is not too great
meaning that deep level impurities are not present.
As the P-N junction reaches forward bias, the diffusion capacitance, Cd dominates. As
mentioned in chapter 2.1.4, Cd is sensitive to the measurement frequency. This is the
- 40 -
Chapter 5 Discussion of Measurement Results
reason why the C-V response between the high and low frequency differ greatly as the
junction enters forward bias. Diffusion capacitance is dependent on movement of
minority carriers. So for measurement frequency at 1 MHz, the change of applied
voltage is too fast for minority carriers to react. This causes the diffusion capacitance of
high frequency measurement to be significantly lower than that of low frequency
measurement when the P-N junction is in forward bias.
C-V Plot Under Different A.C voltage
0.00E+00
5.00E+02
1.00E+03
1.50E+03
2.00E+03
2.50E+03
-6 -5 -4 -3 -2 -1 0 1VB (volts)
Cap
acita
nce
(pF)
50mv0.5v5mv
2.5x103
2x103
1.5x103
1x103
5x102
0x100
Figure 5.1.5: C-V plot of the P-N junction under different A.C voltage
Capacitance of P-N junction is also dependent on the A.C voltage that is superimposed
on the D.C voltage. As shown in Figure 5.1.4, the measured capacitance decreases if the
A.C voltage increases. This is because for a higher A.C voltage, more holes and
electrons are attracted to the contacts and the average depletion width is increased. This
increase in depletion width reduces the average capacitance measured.
- 41 -
Chapter 5 Discussion of Measurement Results
5.2 Doping Profile Extraction using conventional C-V technique.
The extraction process of doping profile using the convention C-V approach will be
discussed in this section. From the experimental results, Equation 2.4 is used to obtain
the depletion width and equation 2.6 is then used to obtain the doping profile of the
junction. Extraction of the data points for the doping profile is done in spreadsheet in
Microsoft Excel. Equation 2.6 is shown here for easy reference.
dVCdAqKs
WN
o
A )/1(2)( 2
2ε−= ---------Equation 2.6
By applying the two equations to all data points retrieved from the experiment, the
doping profile versus depletion width is plotted as shown in Figure 5.2.1. It is important
to make sure the units used for all the parameters within the equation are consistent
throughout as described in chapter 2.2.2 or else calculation error will result in the
extracted doping profile.
- 42 -
Chapter 5 Discussion of Measurement Results
Doping Profile Extracted Using Conventional Technique
0.0E+00
5.0E+15
1.0E+16
1.5E+16
2.0E+16
2.5E+16
3.0E+16
3.5E+16
4.0E+16
0 0.00001 0.00002 0.00003 0.00004 0.00005 0.00006
Depletion Width(m)
Dop
ing
Con
cent
ratio
n N
A (c
m3 )
4x1016
3.5x1016
3.0x1016
2.5x1016
2x1016
1.5x1016
1x1016
5x1015
0x100
Figure 5.2.1: Doping profile extracted using convention C-V technique
Figure 5.2.1 shows the extracted doping profile using the conventional C-V technique. It
can be seen that the extracted profile has a peak doping concentration of 3.5X1016 cm3 at
depletion width W approximately equals to 0.000036m. At the point where the depletion
width is the lowest, VB is the highest. As explained in chapter 2, a larger reverse bias
acting on a P-N junction causes electrons and holes to be attracted to the contact. This
leaves behind more donor and acceptor ions as compared to a smaller reverse bias or P-
N junction in equilibrium. Similarly, it can be seen that the depletion width is largest for
the lowest VB.
Referring to Figure 5.2.1, the doping concentration varies as the depletion width
increases. For an increasing depletion width, the doping concentration increases until W
is approximately equals to 0.00038m and then starts to decrease as W approaches
0.00004m. As indicated in the figure, for depletion width = 0m, this is where the
At W = 0m, this is where the junction/surface is.
? Doping profile near surface cannot be determined.
- 43 -
Chapter 5 Discussion of Measurement Results
junction or surface is. The accuracy of the doping profile extracted will be verified in
Chapter 6, where the results of the inverse modelling process will be discussed.
As discussed in chapter 2, the doping profile extracted using this method is the profile of
the less highly doped side. This is possible because of the assumption that the N+-side is
100 times more heavily doped than the P-side. For this reason, the scr spreading into the
P-side can be neglected. And this happens to be a good assumption as most
semiconductor devices have this characteristic. Hence, effectively the depletion width is
spreading to the less highly doped side (for this case the P-side).
Figure 5.2.1 clearly shows the limitation of the conventional C-V technique, where only
the doping profile of the less highly doped side of the junction is extracted. Despite the
limitations, this extracted doping profile is still important. It is used in Chapter 6 for the
inverse modelling process as it provides a good estimate for the substrate doping of the
P-N junction.
Doping profile can still be extracted for VB up to 0.3 volts. This is because the
conductance is considerably low up to 0.3 volts. Referring to Figure 5.1.1, the P-N
junction turns ‘On’ at VB= 0.4 volts. This switching ‘On’ of the P-N junction results in
increase in the conductance. The second limitation of the conventional C-V technique is
when Vr≈0.3 volts or larger, the capacitance measured cannot be used to doping profile
of the device. This because the conductance across the junction is too high and causes
the capacitance measured to be inaccurate. Likewise, the conductance of the P-N
junction is considered reasonably low enough for doping profile to be accurately
extracted up to 0.3Volts. This prevents doping profile near surface to be determined.
Physics of semiconductor surface is important because that is the region where a modern
semiconductor device such as MOSFET’s CCD operates.
The conventional C-V technique has been demonstrated and doping profile with the two
main limitations was extracted. These limitations will be overcome using the inverse
modelling approach introduced in Chapter 4 which will be the next topic of discussion.
- 44 -
Chapter 6 Results from the Inverse Modelling process
Chapter 6
Results from the Inverse Modelling process
From section 5.2, the doping profile of the P-type substrate can be obtained. This result
is very useful and can be used as a link to the inverse modelling of the doping profile.
This is because this result provides a good guess for the initial substrate doping
concentration. This saves computation time and in some cases reduces a parameter to be
adjusted when performing the adjustment. In SILVACO, a device with uniform
substrate concentration of 6x1016cm3 P-type atoms is doped with two N-type Gaussian
profiles. The device is then made to go through a simulation to obtain the C-V profile.
Measured and Simulated C-V plot with best Fit
0.0E+00
2.0E-04
4.0E-04
6.0E-04
8.0E-04
1.0E-03
1.2E-03
1.4E-03
1.6E-03
-5 -4 -3 -2 -1 0 1Bias Voltage(volts)
Cap
acita
nce(
F/m
2)
Measured C-V Plot Simulated C-V Plot
1.6x10-3
1.4x10-3
1.2x10-3
1.0x10-3
8x10-4
2x10-4
4x10-4
6x10-4
0x10-0
Figure 6.1: Measured and Simulated C-V Curve Superimposed
The capacitance obtained from the simulation is in capacitance per unit width. As
compared to the capacitance obtained from the measurement is in capacitance only. For
matching purpose, both capacitance in simulation and measurement are converted to
capacitance per unit area. The measured capacitance is divided by the area of the device,
Capacitance does not fit very well.
- 45 -
Chapter 6 Results from the Inverse Modelling process
which is 3.94mm2. The simulated capacitance is divided by one micro meter. This is
because the length of device in ATLAS, SILVACO is set at one micro metre by default.
This computation of the capacitance per unit area is calculated in Microsoft Excel.
Following that, the two C-V curves are compared to check if they match in Microsoft
Excel. If the two curves do not fit well, the parameters for the doping profile are
changed and the simulation is allowed to rerun. After several iterations, the result of the
best matched C-V curve is shown in Figure 6.1. The best fit of the two curves is
determined by observing and choosing the curve that best fits. This is done manually
like the iterations process which is time consuming and in some cases may be inaccurate.
A least square solver could have been implemented to solve the problem.
From the results, it can be observed that the two C-V curves matched very well up to
about 1.0 volts. However, as the bias voltage increases greater than 1.0volts, the two C-
V curves are no longer well matched. This is due to the increase in conductance of the
junction for forward bias which affects the accuracy of the measured capacitance. Hence
the two C-V curves are still considered well matched.
Measured Conducatance versus Voltage
0.E+001.E-032.E-033.E-034.E-035.E-036.E-037.E-038.E-039.E-031.E-02
-5 -4 -3 -2 -1 0 1
VB(volts)
Con
duct
ance
G(S
iem
ens)
1x10-2
4x10-3
5x10-3
6x10-3
7x10-3
8x10-3
9x10-3
0x10-0
1x10-3
2x10-3
3x10-3
Figure 6.2: Measured conductance versus voltage curve
- 46 -
Chapter 6 Results from the Inverse Modelling process
As shown in Figure 6.2, the conductance versus voltage plot, the measured conductance
increases as the bias voltage increases. It is important to take note that as the bias
voltage is approaches 0.3 volt, the conductance starts to increase at a faster rate
compared to high reverse bias. And when the bias voltage becomes positive (junction in
forward bias), the conductance starts to increase exponentially. This explains why the
measured capacitance does not match well with the simulated capacitance for bias
greater than 1.0 volts.
As explained earlier, the P-N junction that produces a C-V curve that best fit the
measured C-V curve has doping profile of the actual device. Hence, Figure 6.3 shows
the extracted doping profile of the P-N junction.
Figure 6.3: Extracted doping profile via the inverse modelling approach
Nx(cm-3)
x (um)
Doping profile determined by the conventional method
- 47 -
Chapter 6 Results from the Inverse Modelling process
Figure 6.3 shows the extracted doping profile for the P-N junction after much iteration
using the inverse modelling technique. The final doping profile consists of a P-type
anode with net doping of 4X1016cm3. As for the N-type cathode, it has two Gaussian
peaks implanted. The peak on the right is slightly higher than the implanted profile of
8X1020cm3 due to the addition of the peak on the left.
The doping profile extracted from the conventional C-V method is circled. The doping
concentration decreases as it approaches the junction. It is same as the extracted doping
profile extracted from the conventional C-V technique. It is apparent that the extracted
doping profile using the inverse modelling approach could overcome the limitations of
the conventional C-V technique. The doping profile near junction could be determined.
The doping profile for the less highly doped side, the P-side under test has been
successfully extracted. However, there is still a problem with the extracted profile using
the inverse modelling approach. The doping profile of the more highly doped side (for
this case N+-side) cannot be determined. However,
- 48 -
Chapter 7 Summary and Conclusions
Chapter 7
Summary and Conclusions
In this thesis, the conventional C-V technique had been demonstrated and doping profile
of the device under test was determined. Accurate measurements of capacitances,
voltages and area of the P-N junction were done. Despite that, the doping profile
determined using this method is an approximation with several limitations.
Subsequently, an inverse modelling approach was applied with the use of simulation in
ATLAS. The measurement results of C-V measurement were compared with the
simulated C-V results. If the two curves are does not give a good match, the doping
profile parameters of the P-N junction in simulator are adjusted. The simulation will
rerun and the two C-V curves are matched again. This process is repeated until the two
C-V curves best fits. The final doping profile in simulator which produces C-V curve
that best fit the measured C-V curve is deemed to have the doping profile of the actual
device.
So far, the conventional technique of doping profile extraction has been demonstrated
together with the inverse modelling approach of doping profile extraction. Doping
profile of the less heavily doped side of the P-N junction was accurately determined
with the extension and it tallies with the expected result. This approach of doping profile
extraction has overcome one major limitation of the conventional method; where the
doping profile near the junction cannot be determined.
However, there are several problems with this technique which have to be addressed
before this method can be implemented commercially. For instance, the current method
proved to be inefficient as a least squared solver could have been used to allow this
process to be solved automatically. On top of that, the doping profile of the more
heavily doped side still cannot be obtained. Suggestions for improvement for this thesis
will be made in the next section.
Recommendation for future work and reprise
- 49 -
Recommendations for Future Work and Reprise
Some possible future works include:
• The inverse modelling algorithm could have been programmed entirely in the
device simulator. This eliminates the inefficient trial and error approach and
could fully utilize the advantage of the computational power present in modern
computers. Specifically, the Levenberg-Marquardt nonlinear least-squares solver
could be used in the inverse modelling algorithm. This would allow a threshold
to be assigned to the program which will allow a best fit with all possibilities
taken into consideration.
• The inverse modelling approach discussed in this thesis demonstrated the ability
to evaluate doping profile of P-N junction accurately. Since P-N junctions are
the most fundamental of all semiconductor devices, this approach could be
extended to other devices like MOSFET’s.
• The inverse modelling approach introduced is useful for problem and can be
used for teaching purposes.
Bibliography
- 50 -
Bibliography
[1] C. Y.-T. Chiang, C. T. C. Hsu, and Y. T. Yeow, "Measurement of MOSFET
substrate Dopant Profile via Inversion Layer-to-Substrate Capacitance," in ITEE: University Of Queensland, 1998.
[2] W. C. Johnson, "The Influence of Debye Length on the C-V Measurement of
Doping Profiles," 1971. [3] M. Ziska, "Sperading Resistance Profiling," in Faculty of Electrical Engineering
and Information Technology: Slovak University of Technology in Bratislava, 2001.
[4] E. Pop, "CMOS Inverse Doping Profile Extraction and Substrate Current
Modeling," in Department of Electrical Engineering and Computer Science: Miassachusetts Institute of Technology, 1999.
[5] J. W. Crawford Dunlap, "An Intorduction to Semiconductors." [6] K. Hess, "Advance Theory of Semiconductor Devices," 2000. [7] S. Dimitrijev, "Understanding semiconductor devices," in Oxford series in
electrical and computer engineering. New York: Oxford University Press, 2000, pp. xviii, 574.
[8] B. G. Streetman and S. Banerjee, Solid state electronic devices, 5th ed.
Englewood Cliffs, NJ: Prentice Hall, 2000. [9] J. J. Sparkes, "Semiconductor Devices," 1994. [10] D. K. Schroder, Semiconductor material and device characterization, 2nd ed.
New York: Wiley, 1998. [11] W. R. R. T. J. Shaffner, "Semiconductor Measurements & Instrumentation,"
1998. [12] W. Crans, "Software tools for process, device and circuit modeling," 1989. [13] H. HAYASHI, "Inverse modeling and its Application to MOSFET Channel
Profile Extraction," 1999. [14] W. Crans, "MASCOD (Modelling and Assessment of SemiConducting
Devices)," http://www.dimes.tudelft.nl/2000/215_mascod.htm (Accessed on 10th May 2003.
Bibliography
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[15] C. Y.-T. Chiang and Y. T. Yeow, "Inverse Modelling of Two-Dimensional MOSFET Dopant Profile via Capacitance of the Source/Drain Gated Diode," 2000.
[16] B.Sapoval and C.Hermann, "Physics of Semiconductors," 1993. [17] SILVACO, "http://www.silvaco.com/products/vwf/atlas/atlas/atlas_br.html,"
Date retrieved: 11th May 2003. [18] C. F. Robinson, "Microprobe analysis," 1973.
APPENDIX I
- 52 -
APPENDIX I – Setup of Equipment Used
HP7275A LCR meter
Microscope HP4825 multi-meter
Die Cast box
APPENDIX II
- 53 -
APPENDIX II - Source code for program in LABVIEW
APPENDIX II
- 54 -
APPENDIX II
- 55 -
APPENDIX II
- 56 -
APPENDIX III
- 57 -
APPENDIX III - Source code for program in ATLAS go atlas mesh space.mult=1.0 # x.mesh loc=0.00 spac=0.5 x.mesh loc=3.00 spac=0.2 x.mesh loc=5.00 spac=0.25 x.mesh loc=7.00 spac=0.25 x.mesh loc=9.00 spac=0.2 x.mesh loc=12.00 spac=0.5 # y.mesh loc=0.00 spac=0.1 y.mesh loc=1.00 spac=0.02 y.mesh loc=2.00 spac=0.1 region num=1 silicon electr name=anode top #x.min=0 length=12 electr name=cathode bottom #.... P-epi doping doping p.type conc=4.0e16 uniform #.... n+ doping doping gaussian conc=8.0e20 characteristic=0.25 n.type x.left=0.0 x.right=12.0 peak=1.8 doping gaussian conc=8.0e20 characteristic=0.12 n.type x.left=0.0 x.right=12.0 peak=1.5 save outf=diodeex01_0.str tonyplot diodeex01_0.str model conmob fldmob srh auger bgn contact name=anode workf=4.97 solve init method newton log outfile=diodeex01.log solve vanode=-5.0 vstep=0.1 vfinal=0.8 name=anode ac freq=1e6 tonyplot diodeex01.log -set diodeex01_log.set quit
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