prom,pld problems

DSD and HDL Simulation, Assignment Questions

Problem Give the implementation of full-adder using [i] PROM [ii] PAL Solution: Consider the truth table of full-adder

Consider expression for outputs S and Co

𝑆 = ∑1, 2, 4, 7 and 𝐶 = ∑3, 5, 6, 7

[i] Note that PROM has a fixed AND plane (usually implemented by using a decoder of suitable size) and a programmable OR plane. To implement 8 different product terms, a 3-to-8 decoder may be used. The full-adder implementation using PROM can be shown in different ways:

OR

OR

Here, dots (.) indicate connections to AND gate inputs and cross mark (X) indicates fusible (programmable) links.

[ii] PAL has a programmable AND array and a fixed OR array. The full-adder implementation using PAL is shown below:

Here, cross mark (X) indicates fusible (programmable) links and dot indicates fixed connections.

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Problem Give the implementation of BCD-to-7 segment decoder using PLA. Assume common cathode display. Solution:

7-Segment display format

7-Segment Display Elements for all Numbers Consider the truth table of BCD-to-7 segment decoder

Consider the expression for different outputs a, b, c, d, e, f, g 𝑎 = ∑0, 2, 3, 5, 6, 7, 8,9 𝑏 = ∑0, 1, 2, 3, 4, 7, 8, 9 𝑐 = ∑0, 1, 3, 4, 5, 6, 7, 8, 9

𝑑 = ∑0, 2, 3, 5, 6, 8 𝑒 = ∑0, 2, 6, 8

𝑓 = ∑0, 4, 5, 6, 8, 9

𝑔 = ∑2, 3, 4, 5, 6, 8, 9 The implementation of BCD-to-7 segment decoder using PLA is shown below:

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Dr. D. V. Kamath Professor, Dept. of E&C Engg., MIT