readout for the hft at star. lg - star upgrades workshop dec. 2005 2 a stand-alone heavy flavor...
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Readout for the HFT at STAR
LG - STAR Upgrades Workshop Dec. 2005
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A Stand-alone Heavy Flavor Tracker for STAR
• Z. Xu• Brookhaven National Laboratory, Upton, New York 11973• Y. Chen, S. Kleinfelder, A. Koohi, S. Li • University of California, Irvine, California• H. Huang, A. Tai• University of California, Los Angeles, California 90095• V. Kushpil, M. Sumbera• Nuclear Physics Institute AS CR, 250 68 Rez/Prague, Czech Republic• C. Colledani, W. Dulinski, A. Himmi, C. Hu, A. Shabetai, M. Szelezniak, I.
Valin, M. Winter• Institut de Recherches Subatomique, Strasbourg, France• M. Miller, B. Surrow, G. Van Nieuwenhuizen• Massachusetts Institute of Technology, Cambridge, MA 02139• L. Greiner, H.S. Matis, M. Oldenburg, H.G. Ritter, F. Retiere, A. Rose,
K. Schweda, E. Sichtermann, J.H. Thomas, H. Wieman, N. Xu, and more STARs!
• Lawrence Berkeley National Laboratory, Berkeley, California 94720• I. Kotov• Ohio State University, Columbus, Ohio 43210
LG - STAR Upgrades Workshop Dec. 2005
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STAR HFT • Two layers
– 1.5 cm radius– 4.5 cm radius
• 24 ladders– 2 cm X 20 cm
each– ~ 100 Mega Pixels
Purpose:Greatly improve D meson capability in STAR
LG - STAR Upgrades Workshop Dec. 2005
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HFT Ladder
• 10 MimoSTAR detectors / ladder (green)• I => V conversion and driver electronics (blue)• All ladders are the same
MIMOSTAR
HFT Ladder
I => V conversionand drivers
20 x 50 MHz Analog signalsclock, control, JTAG, power,ground.
10 MIMOSTAR2 Detectors
cableto motherboard
LG - STAR Upgrades Workshop Dec. 2005
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Mimosa5 detectors in a wafer
640 Rows
640Columns
•Serial raster readout
•640 pixels in a row
•320 column / sector
•2 sectors / detector
•4 ms readout time (50 MHz pixel read clock)
MimoSTAR Detector Pixel Structure
LG - STAR Upgrades Workshop Dec. 2005
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•20 I => V converters / drivers per ladder
•Additional clock, control and JTAG connections. Power and ground
•Analog signals and clock/control is transferred to the motherboard via fine twisted pair cable.
I => V Conversion and driver electronics
MIMOSTAR
HFT Ladder
I => V conversionand drivers
20 x 50 MHz Analog signalsclock, control, JTAG, power,ground.
10 MIMOSTAR2 Detectors
cableto motherboard
LG - STAR Upgrades Workshop Dec. 2005
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HFT Readout Functional Goals
• Digitize every 20 ns.• Triggered detector system fitting into
existing STAR infrastructure.• Deliver full frame events to STAR DAQ for
event building at approximately the same rate as the TPC.
• Reduce the total data rate of the detector to a manageable level (<< TPC rate)
• Reliable, robust, cheap, etc.
LG - STAR Upgrades Workshop Dec. 2005
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Functional Block DiagramHFT Motherboard
Daughter Card (x5)
ADCCDS,
Ped. Sub.(FPGA)
RAM
Hit finddata red.(FPGA)
SIU
analog data
Buffer
clock, control, JTAG, power,ground.
ToLadder
Hit dataTo RORC
Synch /Control(FPGA)
To Synch / Triggerboard
The readout system is a large parallel system. The block diagram shown above is for one ladder of a 24 ladder system.
LG - STAR Upgrades Workshop Dec. 2005
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ADC and CDS Block Diagram
10 bitADC
CDSFPGA
SDRAM
ClusterFinder
FromDetector
•Synchronous Correlated Double Sampling and hot pixel removal.
•8 bit data after CDS.
•Perform read – subtract – write on each clock tick.
LG - STAR Upgrades Workshop Dec. 2005
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Cluster Finding FPGA
Data FIFO, 8-bit, 317 deep
8-bit post-CDSdata
18204,800counter
Data saved per high threshold crossing
columnn
columnn-1
columnn+1
row nrow n-1 row n+1
Cluster Finding for HFT
50 MHz datastream.2 streams / detector
LG 11/28/2005
Data FIFO, 8-bit, 317 deep
8-bit, 3 deep Shift Register
8-bit, 3 deep Shift Register
8-bit, 3 deep Shift Register
highthresh
WriteEnable
highthresh.
Address saved per high threshold crossing
pixel address
pixel address
Cluster Word (90 bits)
LG - STAR Upgrades Workshop Dec. 2005
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8-bit post-CDSdata
pixel address
18204,800counter
Cluster Finding for HFT Saving Address Only
50 MHz datastream.2 streams / detector
Hi / LowThreshold
2 bits
Cluster sensor operateson these 9 pixels
Load
ToClusterFIFO
LG - STAR Upgrades Workshop Dec. 2005
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Cluster FIFO
Eve
nt F
IFO
Eve
nt F
IFO
Eve
nt F
IFO
Eve
nt F
IFO
Eve
nt F
IFO
Cluster data from Cluster Finder
trigger handler
delay/gate Enable for 1 frame
trigger/DAQ
1 sectordata stream
1 2 3 4 5
SIU
DAQ
•Trigger enables FIFOs sequentially for 1 frame ( 204,800 clocks) with an offset to the enable that aligns the event start time with the location of the first pixel in the event.•Each event FIFO is a separate trigger event stream and can be enabled independently. This allows events to be triggered at ~1 ms intervals with our 4 ms latency.•Each sector event FIFO is emptied by the SIU at the end of the frame.
LG - STAR Upgrades Workshop Dec. 2005
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Implementation Diagram
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Some Relevant Numbers
• bits/address = 18
• Number of inner ladders = 6
• Number of outer ladders = 18
• Sectors (half chips) per ladder = 20
• ave hits/half chip, inner, (L = 1027) = 200
• ave hits/half chip, outer, (L = 1027) = 40
• 1 KHz event rate.
LG - STAR Upgrades Workshop Dec. 2005
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Data Rates
• Average event size = 90 KB• Event size = 90 MB/sec at 1KHz• 24 fibers• 12 RORC (4 readout PCs)
MIMOSTARSensors
123 GB/s
ADCsADCs
ADCs
AnalogSignals
CDS
98 GB/s
DAQ90 MB/s
HitFinder
+ address(450 Mb/secfor ADCs too)
LG - STAR Upgrades Workshop Dec. 2005
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Features of HFT Readout Scheme• The daughter board hardware will provide the full data rate and functionality
required for a complete first generation 4 ms HFT solution.• Much of the required VHDL firm ware is running, tested and understood• The cluster identifier runs at the same speed as digitization providing
immediate data compression. Only cluster center addresses are passed on for data storage.
• Data digitization and compression takes the same 4 ms for all events independent of data.
• The cluster identifier and data compression fits well in the FPGA environment. It requires few resources and can be implemented with simple straight forward VHDL coding.
• The design is triggered and fits the standard DAQ design.• All the hits for an event are stored directly for that event. There are no
complications with frame boundaries or hits for an event located in different frames. This is important because file handling software used in STAR data analysis does not have to be altered to accommodate the HFT.
• The latency is 4 ms, but the dead time is 1 ms matching the new TPC system.
• The HFT data size for an event is 90 kBytes, significantly less than the 2 Mbytes for TPC central collision event.
LG - STAR Upgrades Workshop Dec. 2005
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Data FormatEvent/Header
ladder address 0
half chip address 0
pixel address 157,921
pixel address 159,203
. . . . . .
pixel address 142,888
pixel address 148,321
half chip address 1
pixel address 155,423
pixel address 155,231
. . . . .
ladder address 1
half chip address 0
18 bit wide words
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