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DM632B
Version : PRE.001 Issue Date : 2008/07/31 File Name : SP-DM632B-PRE.001.doc Total Pages : 31
16-CHANNEL CONSTANT CURRENT LED DRIVER
WITH 16-bit PROGRAMMABLE PWM OUTPUTS
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 1
DM632B
DM632B 16-CHANNEL CONSTANT CURRENT LED DRIVER
WITH 16-bit PROGRAMMABLE PWM OUTPUTS
General Description DM632B is a 16-channel constant current sink LED driver. Each channel has independent
16-bits (65536 steps) grayscale PWM control current outputs. It incorporates shift registers, data
latches, constant current circuitry with current value set by an external resistor, and built-in LED
open detection circuit to detect error status. It combines the selections with rising / falling edge
serial out, auto-reload/one-shot PWM output, internal/external grayscale clock source. It is
specifically designed for LED display or lighting applications.
Features Constant-current outputs: 5mA to 60mA adjustable by one external resistor
16-bit linear PWM control current outputs for each channel
Maximum output voltage: 17V
Maximum clock frequency: 25MHz
Auto-Reload / One-Shot Mode selection.
Serial out clock edge selection – Rising / Falling edge selection
Internal / External PWM clock mode selection
Built-in real-time open detection
Package and pin assignment compatible to conventional LED drivers
(DM134/5/6, DM13C)
Power supply voltage: 3.3V to 5V
Schmitt Trigger input
Output channel delay
Applications Indoor/Outdoor LED Video Display
LED Variable Message Signs (VMS) System
LED Decorative Lighting
Package Types DIP24B, SOP24B, SSOP24, TSSOP24E (with exposed pad)
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 2
DM632B
Block Diagram
DAI
DCK
LAT
DAO
GCK
REXT
OUT 0 OUT 15
16-bitCounter
16
16
16
16
16
16
InternalOscillator
VCCGND
16-bit Shift Register(1)
16-bit Shift Register(15)
16-bit Latch Register(0)
16-bit Latch Register(1)
16-bit Latch Register(15)
16-bit Shift Register(0)
16-bit PWM Generator(0)
16-bit PWM Generator(1)
16-bit PWM Generator(15)
OUT 1
LED Open Detector(0)
LED Open Detector(1)
LED Open Detector(15)
Constant Current Driver(0)
Constant Current Driver(1)
Constant Current Driver(15)
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 3
DM632B
Pin Connection
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
OUT0OUT1OUT2OUT3
VCCREXTDAOGCK
GND
DCKLAT
OUT 15OUT 14OUT 13OUT 12
DAI
SOP24
TSSOP24E
( top view )
9
10
11
12
16
15
14
13
OUT4OUT5OUT6OUT7
OUT 11OUT 10OUT 9OUT 8
SOP24B
DIP24B
Pin Description PIN No. PIN
NAMEFUNCTION
SOP24B/SSOP24/TSSOP24E: 1 TSSOP24E: exposed pad
GND Ground terminal.
SOP24B/SSOP24/TSSOP24E: 2 DAI Serial data input terminal.
SOP24B/SSOP24/TSSOP24E: 3 DCK Synchronous clock input terminal for serial data transfer. Data is sampled at the rising edge of DCK.
SOP24B/SSOP24/TSSOP24E: 4 LAT
Input terminal of data strobe: ‘H’ means data on shift register goes through latch
(level trigger), all outputs off and counter resetimmediately
‘L’ means data is latched.
SOP24B/SSOP24/TSSOP24E: 5~20 OUT0~15 Sink constant-current outputs (open-drain).
SOP24B/SSOP24/TSSOP24E: 21 GCK Gray Scale Clock (GCK) : Input terminal for PWM operation.
SOP24B/SSOP24/TSSOP24E: 22 DAO Serial data output terminal. Data shift out at the rising edge of DCK in REM∗1 (default), or data shift out at the falling edge of DCK in FEM∗2.
SOP24B/SSOP24/TSSOP24E: 23 REXT External resistors connected between REXT and GND for output current value setting.
SOP24B/SSOP24/TSSOP24E: 24 VCC Supply voltage terminal.
∗1 Rising Edge Mode ∗2 Falling Edge Mode
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 4
DM632B
Equivalent Circuit of Inputs and Outputs 1. DCK, DAI, LAT , GCK terminals
2. DAO terminals
PCB Layout Consideration To connect an external resistor to REXT pin and ground can determine the maximum output
current. If there is any disturbance occurred to REXT pin, the constant current output may be unstable or has noise happened. Since REXT (pin23), DAO (pin22), and GCK (pin21) are next to each other, the most possible interference is caused by DAO or GCK signal. Accordingly, it is recommended that adding some shielding area within the above pins in PCB layout, or laying the signal line of above pins on different PCB layer will prevent the noise problems effectively.
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 5
DM632B
Maximum Ratings (Ta=25°C, Tj(max) = 150°C) CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VCC -0.3 ~ 7.0 V Input Voltage VIN -0.3 ~ VCC+0.3 V Output Current IOUT 70 mA Output Voltage VOUT -0.3 ~ 17 V Input Clock Frequency FDCK 25 MHz GND Terminal Current IGND 1120 mA
4.17 ( TSSOP24E exposed pad) 2.19 ( SOP24B) 1.87 (DIP24B)
Power Dissipation (4 layer PCB, at Ta=25℃)
PD
1.79 ( SSOP24 )
W
30 ( TSSOP24E exposed pad) 57 (SOP24B) 67 (DIP24B)
Thermal Resistance (4 layer PCB, at Ta=25℃)
Rth(j-a)
70 (SSOP24 )
°C/W
Operating Temperature Top -40 ~ 85 °C Storage Temperature Tstg -55 ~ 150 °C
Recommended Operating Condition
CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNITSupply Voltage VCC ⎯ 3.3 5.0 5.5 V
Output Voltage VOUT Driver On*1 1.0 ⎯ 0.5VCC
Output Voltage VOUT Driver Off*2 ⎯ ⎯ 17 V
IO OUTn 5 ⎯ 60 IOH VOH = VCC – 0.4 V ⎯ ⎯ +1.5 Output Current IOL VOL = 0.2 V ⎯ ⎯ -1.5
mA
VIH 0.8VCC ⎯ VCC Input Voltage
VIL VCC = 3.3 V ~ 5.5V
0.0 ⎯ 0.2VCCV
Input Clock Frequency FDCK Single Chip Operation ⎯ ⎯ 25
Input PWM Frequency FGCK 3.3V~5.5V ⎯ ⎯ 25 MHz
LAT Pulse Width tw LAT 15 ⎯ ⎯ DCK Pulse Width tw DCK 15 ⎯ ⎯ Set-up Time for DAI tsetup(D) 10 ⎯ ⎯ Hold Time for DAI thold(D) 10 ⎯ ⎯ Set-up Time for LAT tsetup(L) 10 ⎯ ⎯ Hold Time for LAT thold(L)
VCC = 5.0V
360*3 ⎯ ⎯
ns
*1 Notice that the power dissipation is limited to its package and ambient temperature. *2 The driver output voltage including any overshoot stress has to be compliant with the maximum voltage (17V). *3 Due to open detection operation and output channel delay consideration.
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點晶科技股份有限公司 SILICON TOUCH TECHNOLOGY INC. 新竹市科學園區展業一路 9號 7樓之 1
9-7F-1, Prosperity RoadⅠ, Hsin-Chu, Taiwan, R.O.C. Tel:886-3-5645656 Fax:886-3-5645626
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 6
DM632B
Electrical Characteristics (VCC = 5.0 V, Ta = 25°C unless otherwise noted) CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT
Output Leakage Current IOL VOH = 17 V ⎯ ⎯ ±1.0 uA
VOL IOL = 1.25 mA ⎯ ⎯ 0.4 Output Voltage (S-OUT)
VOH IOH= 1.4 mA VCC-0.2 ⎯ ⎯ V
Output Current Skew
(Channel-to-Channel)*1 IOL1 ⎯ ⎯ ±3 %
Output Current Skew
(Chip-to-Chip)*2 IOL2
VOUT = 1.0 V Rrext = 2.2 KΩ
TBD TBD TBD mA
Output Voltage Regulation % / VOUT Rrext = 2.2 KΩ
VOUT = 1 V ~ 3 V ⎯ ±0.1 ±0.5
Supply Voltage Regulation % / VCC Rrext = 2.2 KΩ ⎯ ±1 ±4
% / V
LED Open Detection Threshold V(od) all outputs turn on ⎯ 0.2 ⎯ V
IDD(off)
power on all pins are open
unless VCC and GND (internal GCK mode
⎯ 5.5 ⎯
IDD(off)
power on all pins are open
unless VCC and GND (external GCK mode)
⎯ 5.0 ⎯
IDD(on) input signal is static
Rrext = 12.4 KΩ all outputs turn off
⎯ 6.0 ⎯
IDD(on) input signal is static
Rrext = 2.2 KΩ all outputs turn off
⎯ 8.5 ⎯
Supply Current*3
IDD(on) input signal is static
Rrext = 570 Ω all outputs turn off
⎯ 17.5 ⎯
mA
*1 Channel-to-channel skew is defined as the ratio between (any Iout – average Iout) and average Iout, where average
Iout = (Imax + Imin) / 2. *2 Chip-to-Chip skew is defined as the range into which any output current of any IC falls. *3 IO excluded.
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 7
DM632B
Electrical Characteristics (VCC = 3.3 V, Ta = 25°C unless otherwise noted) CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT
Output Leakage Current IOL VOH = 17 V -1.0 ⎯ +1.0 uA
VOL IOL = 1.25 mA ⎯ ⎯ 0.4 Output Voltage (S-OUT)
VOH IOH= 1.4 mA VCC-0.2 ⎯ ⎯ V
Output Current Skew
(Channel-to-Channel)*1 IOL1 ⎯ ⎯ ±3 %
Output Current Skew
(Chip-to-Chip)*2 IOL2
VOUT = 1.0 V Rrext = 2.2 KΩ
TBD TBD TBD mA
Output Voltage Regulation % / VOUT Rrext = 2.2 KΩ
VOUT = 1 V ~ 3 V ⎯ ±0.1 ±0.5
Supply Voltage Regulation % / VCC Rrext = 2.2 KΩ ⎯ ±1 ±4
% / V
LED Open Detection Threshold V(od) all outputs turn on ⎯ 0.2 ⎯ V
IDD(off)
power on all pins are open
unless VCC and GND (internal GCK mode)
⎯ 4.5 ⎯
IDD(off)
power on all pins are open
unless VCC and GND (external GCK mode)
⎯ 4.2 ⎯
IDD(on) input signal is static
Rrext = 12.4 KΩ all outputs turn off
⎯ 5.5 ⎯
IDD(on) input signal is static
Rrext = 2.2 KΩ all outputs turn off
⎯ 7.0 ⎯
Supply Current*3
IDD(on) input signal is static
Rrext = 570 Ω all outputs turn off
⎯ 15.0 ⎯
mA
*1 Channel-to-channel skew is defined as the ratio between (any Iout – average Iout) and average Iout, where average
Iout = (Imax + Imin) / 2. *2 Chip-to-Chip skew is defined as the range into which any output current of any IC falls. *3 IO excluded.
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 8
DM632B
Switching Characteristics (VCC = 5.0V, Ta = 25°C unless otherwise noted) CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT
GCK-to-OUT ⎯ 45.7 ⎯
DCK(rising edge)-to-DAO ⎯ 36 ⎯ Propagation Delay
(‘L’ to ‘H’) DCK(falling edge)-to-DAO
tpLH
⎯ 16 ⎯
GCK-to-OUT ⎯ 23.8 ⎯
DCK(rising edge)-to-DAO ⎯ 28 ⎯ Propagation Delay
(‘H’ to ‘L’) DCK(falling edge)-to-DAO
tpHL
⎯ 14 ⎯
Output Current Rise Time tor ⎯ 18 ⎯
Output Current Fall Time tof ⎯ 7.0 ⎯
Output Delay Time Unit Td
VIH = VCC
VIL = GND
Rrext = 2.2 KΩ
VL = 5.0 V
CL = 13 pF
⎯ 20 ⎯
ns
Switching Characteristics (VCC = 3.3V, Ta = 25°C unless otherwise noted) CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT
GCK-to-OUT ⎯ 48.8 ⎯
DCK(rising edge)-to-DAO ⎯ 23 ⎯ 0Propagation Delay
(‘L’ to ‘H’) DCK(falling edge)-to-DAO
tpLH
⎯ 23 ⎯
GCK-to-OUT ⎯ 29.6 ⎯
DCK(rising edge)-to-DAO ⎯ 21 ⎯ Propagation Delay
(‘H’ to ‘L’) DCK(falling edge)-to-DAO
tpHL
⎯ 20 ⎯
Output Current Rise Time tor ⎯ 20 ⎯
Output Current Fall Time tof ⎯ 8.3 ⎯
Output Delay Time Unit Td
VIH = VCC
VIL = GND
Rrext = 2.2 KΩ
VL = 3.3 V
CL = 13 pF
⎯ 30 ⎯
ns
OUTn
DAO
REXT
VCC
CL
VL
Switching Characteristics Test Circuit
A
Rrext
DAI
LAT
DCK
GCKCLCLCLCL
GND
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 9
DM632B
Constant-Current Output Constant-current value (Iout*1) of each output channel is set by an external resistor connected
between the REXT pin and GND. The current scale ranging can be adjusted from 5mA to 60mA by varying the resistor value. The reference voltage of REXT terminal (Vrext) is approximately 1.23V. The output current value is calculated by the following equation:
Iout(mA) 5 10 20 30 40 50 60
M 37.11 36.29 37.55 39.03 40.36 40.4 41.28
Output current as a function of Rext value
0
10
20
30
40
50
60
70
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Rext
Iout
(mA)
Output Current as a function of Output Voltage
0
10
20
30
40
50
60
70
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Vout(V)
Iout
(A)
In order to obtain a good performance of constant-current output, a suitable output voltage is necessary. Users can get related information about the minimum output voltage above.
*1 Iout is typical current value setting under 100% PWM duty cycle .
Iout (mA) ~Vrext (V)
Rrext (KΩ)× M
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 10
DM632B
Serial Data Interface The serial-in data (DAI) data will be clocked into 16 × 16 bit shift registers synchronized on
the rising edge of the clock (DCK). The data will be transferred into the 16 × 16 bit latch registers
when the strobe signal ( LAT ) is kept at high level (level trigger); Otherwise, the data will be held. The latch pulse should be sent after the falling edge of the last clock within one frame data. The serial-out data (DAO) will be shifted out on synchronization of the clock (DCK). Input Data clock-in sequence
The sequence of the grayscale PWM luminous data of a driver showed as following diagram. The input data sequence of input data is from the MSB of OUT15 (D15 [15:0]) to the LSB of OUT0 (D0 [15:0]) by time passing.
Serial-out Data clock-out sequence The data serial out from DAO include latched grayscale data and the LSB of each output data covered by detection message (ERR) after LAT pulse be active. The serial out sequence of the data is from the MSB of OUT15 (D15 [15:0]) to the LSB of OUT0 (D0 [15:0]) by time passing.
D15 [15] D15[13] D15[10] D15 [9] D15[8]D15[12] D15[11] D15[7] D15 [6] D15[5] D15 [2] D15[1] ERR [15]D15[4] D15[3]
LSB
OUT 15
MSB
shift out first
LSB
OUT 14
MSB
LSB
OUT 0
MSB
D14[15] D14[14] D14 [13] D14 [10] D14[9] D14[8]D14 [12] D14[11] D14 [7] D14[6] D14[5] D14[2] D14[1] ERR[14]D14[4] D14 [3]
D0 [15] D0 [14] D0[13] D0[10] D0[9] D0 [8]D0[12] D0 [11] D0[7] D0 [6] D0 [5] D0 [2] D0 [1] ERR[0]D0[4] D0[3]
D15 [14]
* ERR[15], ERR[14], … EER[0] are Error Message of LED Open Detection. `1'is normal, and `0'is abnormal.
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 11
DM632B
Rising/Falling Edge Mode selection The luminous data serial out from DAO by data clock (DCK) as following waveform. In rising edge mode (REM), the data serial out by the rising edge of DCK.
D[255]DAO
DCK
LAT
255
E [2 ]
1 2
D[254] D[253 ] 55
256
ERR[0]
256
Rising Edge Mode (REM) DAO serial out by DCK rising edge.
In falling edge mode (FEM), the data serial out by the falling edge of DCK.
DAO
DCK
LAT
2551 2 256256
Falling Edge Mode (FEM) : DAO serial out by DCK falling edge.
D[255] E [2 ]D[254] 55ERR[0]
*D[255], D[254],…D[0], E[255] are clock-in data in Shift data register of driver
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 12
DM632B
The default mode is the Rising-Edge Mode (REM*1) after power-on. Users could do mode select between REM and FEM*2 by following timing sequence. The option 1 shows two rising edge of latch pulses ( LAT ) when the data-input clock (DCK) kept at high level then sending one rising edge of DCK pulses when LAT kept at high level. Then we can receive serial-out data from the data-output signal (DAO) at falling edge of DCK after the falling edge of LAT . The option 2 shows three rising edge of LAT when DCK kept at high level then sending two rising edge of DCK, while LAT kept high level at the same time. After the falling edge of LAT , we receive serial-out data from DAO at rising edge of DCK (REM). Notice that when internal RESET at low level, all the shift registers in DM632B will be cleared (Kept at Low level).
DCK
LAT
Option 2 : Timing Combination to set up Rising-Edge Mode (REM)
RESET (internal)
t
1 2 3
1 2
GCK
DCK
LAT
Option 1 : Timing Combination to set up Falling-Edge Mode (FEM)
RESET (internal)
t
1 2
1
GCK XX X X
Auto-Reload/One-Shot Mode selection The Auto-Reload mode (ARM) in DM632B means outputs can repeat the grayscale PWM cycle over and over. It can decrease the data amount greatly compare to non-PWM function driver operated in grayscale PWM application.
LAT
GCK
OUT0
( internal or external ) 65536 GCK
Counter reset
(current)
on
off
high
low
1
0
Auto-Reload Mode (ARM).
Frame Data B
65536 GCK
Frame Data B
The One-Shot Mode in DM632B means each output shows one grayscale PWM cycle following one latch pulse. The grayscale PWM cycle starts with the falling edge of LAT signal. The first GCK pulse after LAT increases the grayscale counter by one and switches on all outputs with grayscale value. It makes driver synchronous control easily.
*1 REM switch to FEM timing diagram please refer to page 16. *2 FEM switch to REM timing diagram please refer to page 17.
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 13
DM632B
on
off
high
low
65536 GCK
1
0
Frame Data B
One-Shot Mode (OSM)
LAT
GCK
OUT0
( internal or external )
(current)
Counter reset
The default mode is the Auto-Reload Mode (ARM*1) after power-on. Users could do mode
select between ARM and One-Shot Mode (OSM*2 ) by following timing sequence. The gray scale clock signal (GCK) should keep at low during this mode selection process. The option 1 shows four rising edges of latch pulse ( LAT ) when the data-input clock (DCK) kept at high level then three rising edges of DCK when LAT kept at high level. Then DM632B starts OSM after the falling edge of LAT . The option 2 shows five rising edges of LAT when DCK kept at high level then sending four rising edges of DCK signal, while LAT signal kept high level . After falling edge of LAT , DM632B switch to ARM . Notice that when internal RESET at low level, all the shift registers in DM632B will be cleared (Kept at Low level) .
DCK
LAT
RESET (internal)
Option 1 : Timing Combination to set up One-Shot Mode (OSM)
t
1 2 3
1 2 3
4
GCK
DCK
LAT
RESET (internal)
Option 2 : Timing Combination to set up Auto-Reload Mode (ARM)
t
1 2 3
1 2 3
4
GCK
5
4
X X X X
*1 ARM switch to OSM timing diagram please refer to page 18. *2 OSM switch to ARM timing diagram please refer to page 19.
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 14
DM632B
Internal/External Clock Mode selection Grayscale luminous of each channel comes from comparisons of grayscale PWM luminous data and grayscale counter value. In internal-clock mode, DM632B provides build-in oscillator for counter operation. In external-clock mode, the clock source of counter is from control system through GCK pin. The default mode is the Internal-Clock Mode(ICM*1) after power-on. Users could do mode select between ICM and External-Clock Mode (ECM∗2 ) by following timing sequence. The option 1 shows four rising edges of latch pulses ( LAT ) when the data clock (DCK) kept at high level and the grayscale clock (GCK) kept at low then sending three rising edges of DCK when LAT and GCK both kept at high level. Then we can input external gray scale clock from GCK pin to operate grayscale PWM function after the falling edge of LAT . The option 2 shows five rising edges of LAT when DCK kept at high level and GCK at low level then sending four rising edges of DCK , while LAT and GCK kept at high level . After the falling edge of LAT , grayscale PWM function operates by internal gray scale clock generator. Notice that when internal RESET at low level, all the shift registers in DM632B will be cleared (Kept at Low level).
DCK
LAT
RESET (internal)
Option 1 : Timing Combination to set up External-Clock Mode (ECM)
t
1 2 3
1 2 3
4
GCK
DCK
LAT
RESET (internal)
Option 2 : Timing Combination to set up Internal-Clock Mode (ICM)
t
1 2 3
1 2 3
4
GCK
5
4
XXXX
LED Open Detection
DM632B provides a real time monitor of LED open detection function without extra components or circuit design. It will be identified as a LED open failure when the output is turned on but the output voltage is below 0.2V. The test result of each channel will write to its correspondent shift register which is in LSB position (ERR[15], ERR[14], …., ERR[0]) while strobe signal is active. User can refer to timing diagram on page11. Detecting report could be retrieved from serial-out (DAO) data. If the system reads ‘1’ back, that indicates LED is in normal status. But if ‘0’ was retrieved then LED open failure has occurred. In order to make sure LED open detection function is in well operating condition, thold(L)*3 should larger then 360n sec(typ) due to the build-in delay between outputs. And it is recommended that all the luminance data wrote to ‘1’ during detection.
*1 ICM switch to ECM timing diagram please refer to page 20. ∗ 2 ECM switch to ICM timing diagram please refer to page 21 * 3 Hold time between LAT and DCK, please refer to page 15.
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16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 15
DM632B
Timing Diagram 1. DCK-DAI, DAO
DCK
DAI
DAO50%
50% 50%
50% 50% 50%
twDCK twDCK
tsetup(D) thold(D)
tpLH tpHL
50%
50%
2. DCK-LAT
DCK
LAT
50%
50% 50%
tsetup(L)
twLAT
50%
t hold(L)
3. GCK-OUT0
GCK
OUT050%
50% 50%
tpLH tpHL
50%
ON
OFF
4. Output Delay Time Unit (N=0, 4, 8, 12)
OUTN
OUTN+150%
50%
td
OUTN+250%
td
OUTN+350%
td
ON
OFF
ON
OFF
ON
OFF
ON
OFF
-
點晶科技股份有限公司 SILICON TOUCH TECHNOLOGY INC. 新竹市科學園區展業一路 9號 7樓之 1
9-7F-1, Prosperity RoadⅠ, Hsin-Chu, Taiwan, R.O.C. Tel:886-3-5645656 Fax:886-3-5645626
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 16
DM632B
Timing Diagram (Rising-Edge Mode switch to Falling-Edge Mode)
Don
'ca
ret
*2ER
R[0
] is
the
erro
r mes
sage
of
LED
ope
n de
tect
ion.
*3LA
T is
leve
l trig
ger,
not e
dge
trigg
er.
J[1
]
255
256
DAI
DAO
*1
DC
K
LAT
*3
12
256
GC
K
OU
Tn*4
(cur
rent
)
J[0
]L[
255]
L[25
4]
J[2
55]
Fram
eD
ata
JFr
ame
Dat
aI
high
low
high
low 1 01 0
L[2
55]
254
J[2
]
I[1]
Cou
nter
re
set
*4Io
ut tu
rn o
ff w
hen
LAT
is h
igh
leve
l ,an
d tu
rn o
n at
the
first
GC
K ris
ing
edge
whe
n LA
T is
low
leve
l.
65
536
GC
K
J[2
54]
12
34
L[2
54]
L[2
53L
[252
]]
M[2
55]
M[2
54]
M[2
53]
M[2
52]
*1R
EM, A
RM
, IG
M is
con
figer
ed b
y de
faul
t. Th
ey c
an s
witc
h to
FEM
, OSM
, EG
M a
ccor
ding
ly.
All r
egis
ters
in D
M63
2B w
ith b
e re
set w
hen
any
switc
h pr
ocee
s oc
cur.
Fram
eD
ata
L
(inte
rnal
)
GC
K
(ext
erna
l)
1 0 on off
high
low
Don
'ca
ret
L[0
]D
on'
care
t
ER
R[0
]*2
Mod
e sw
itch
perio
dG
rays
cale
dat
a cl
ock-
in p
erio
dG
rays
cale
dat
a cl
ock-
in p
erio
d
*5 J
[255
],J[2
],J[1
],J[0
],I[1
],I[1
],L[2
55].L
[254
],… L
[0],M
[255
],M[2
54],…
are
ser
ial d
ata
for D
M63
2B.
Fram
eD
ata
L
*5
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 17
DM632B
Timing Diagram (Falling-Edge Mode switch to Rising-Edge Mode) D
on'
care
tD
on'
care
t
*2ER
R[0
] is
the
erro
r mes
sage
of
LED
ope
n de
tect
ion.
*3LA
T is
leve
l trig
ger,
not e
dge
trigg
er.
M[1
]
255
256
DAI
DAO
*1
DC
K
LAT
*3
12
256
GC
K
OU
Tn*4
(cur
rent
)
M[0
]O
[255
]O
[254
]O
[0]
M[2
55]
M[2
54]
Fram
e D
ata
MFr
ame
Dat
aL
on off
high
low
high
low 1 01 0
O[2
55]
254
M[2
]
L[1
]
Cou
nter
re
set
*4Io
ut tu
rn o
ff w
hen
LAT
is h
igh
leve
l ,an
d tu
rn o
n at
the
first
GC
K ris
ing
edge
whe
n LA
T is
low
leve
l.
65
536
GC
K
N[2
53]
12
34
O[2
54]
O[2
53O
[252
]]
P[2
55]
P[2
54]
P[2
53]
P[2
52]
*1R
EM, A
RM
, IG
M is
con
figer
ed b
y de
faul
t. Th
ey c
an s
witc
h to
FEM
, OSM
, EG
M a
ccor
ding
ly.
All r
egis
ters
in D
M63
2B w
ith b
e re
set w
hen
any
switc
h pr
ocee
s oc
cur.
Fram
eD
ata
O
(inte
rnal
)
GC
K(e
xter
nal)
1 0 high
low
ER
R[0
]*2
Don
'ca
ret
Mod
e sw
itch
perio
dG
rays
cale
dat
a cl
ock-
in p
erio
dG
rays
cale
dat
a cl
ock-
in p
erio
d
*5 M
[255
],M[2
54],…
M[0
],L[2
],L[1
],O[2
55].O
[254
],… O
[0],P
[255
],P[2
54],…
are
ser
ial d
ata
for D
M63
2B.
L[2
]*5
Fram
eD
ata
O
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 18 未經授權而逕予重製、複製、使用或公開本文件,行為人得被追究侵權之相關民刑事責任
Unauthorized reproduction, duplication, use or disclosure of this document will be deemed as infringement.
DM632B
Timing Diagram (Auto-Reload Mode switch to One-Shot Mode) D
on'
care
D[0
]
on off
high
low
high
low 1 01 0
D[2
55]
DAI
DA
O*1
DC
K
LAT*
3
OU
Tn*4
12
256
F[2
55]
F[2
54]
F[0
]
F[25
]5D
[2]
53D
[2]
52
65
536
GC
K [
255]
G[2
54]
G[2
53]
G
[2]
54F
[2]
53F
[252
F]
*2ER
R[0
] is
the
erro
r mes
sage
of
LED
ope
n de
tect
ion.
*3LA
T is
leve
l trig
ger,
not e
dge
trigg
er.
*4Io
ut tu
rn o
ff w
hen
LAT
is h
igh
leve
l ,an
d tu
rn o
n at
the
first
GC
K ris
ing
edge
whe
n LA
T is
low
leve
l.
*1R
EM, A
RM
, IG
M is
con
figer
ed b
y de
faul
t. Th
ey c
an s
witc
h to
FEM
, OSM
, EG
M a
ccor
ding
ly.
All r
egis
ters
in D
M63
2B w
ith b
e re
set w
hen
any
switc
h pr
ocee
s oc
cur.
D[2
]54
256
GC
K(e
xter
nal)
1 0
Fram
e D
ata
F
For e
xam
ple,
if th
e re
fresh
rate
in d
ispl
ay s
yste
m is
hig
her t
han
60H
z, th
e in
put G
CK
frequ
ency
mus
t be
high
er th
an 4
MH
z.
=R
efre
sh R
ate
(Hz)
Inpu
t GC
K Fr
eque
ncy
(Hz)
Tota
l PW
M re
solu
tion
(216
)
6553
6 G
CK
Cou
nter
re
set
(cur
rent
)
high
low
Cou
nter
re
set
Fram
e D
ata
CFr
ame
Dat
a D
GC
K(in
tern
al)
t
12
3
Don
' c
are
t
*5D
[255
],D[2
54],…
D[0
],F[2
55],F
[254
],...F
[0],G
[255
],G[2
54],…
are
ser
ial d
ata
for D
M63
2B.
Mod
e sw
itch
perio
dG
rays
cale
dat
a cl
ock-
in p
erio
dG
rays
cale
dat
a cl
ock-
in p
erio
d
Don
' c
are
t
Fram
e D
ata
D
*5
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 19
DM632B
Timing Diagram (One-Shot Mode switch to Auto-Reload Mode)
*2ER
R[0
] is
the
erro
r mes
sage
of
LED
ope
n de
tect
ion.
*3LA
T is
leve
l trig
ger,
not e
dge
trigg
er.
ER
R[0
]*2
G[1
]
255
256
DAI
DAO
*1
DC
K
LAT
*3
t
12
256
GCK
OU
Tn*4
(cur
rent
)
G[0
]I[
255]
I[25
4]I[
0]
G[2
55]
Fram
eD
ata
GFr
ame
Dat
aF
on off
high
low
high
low 1 01 0
I[25
5]F
[1]
*4Io
ut tu
rn o
ff w
hen
LAT
is h
igh
leve
l ,an
d tu
rn o
n at
the
first
GC
K ris
ing
edge
whe
n LA
T is
low
leve
l.
65
536
GC
K
G[2
52]
12
I[25
4]
J[25
5]J[
254]
*1R
EM, A
RM
, IG
M is
con
figer
ed b
y de
faul
t. Th
ey c
an s
witc
h to
FEM
, OSM
, EG
M a
ccor
ding
ly.
All r
egis
ters
in D
M63
2B w
ith b
e re
set w
hen
any
switc
h pr
ocee
s oc
cur.
G[2
53]
[254
]G
(iner
nal)
G[2
53]
65
536
GC
K
GC
K(e
xter
nal)
1 0
Fram
e D
ata
I
high
low
Don
'ca
reD
on'
care
tD
on'
care
t
Mod
e sw
itch
perio
dG
rays
cale
dat
a cl
ock-
in p
erio
dG
rays
cale
dat
a cl
ock-
in p
erio
d
*5 F
[1],G
[255
],G[1
],G[0
],I[2
55],I
[254
],...I
[0],J
[255
],J[2
54],…
are
ser
ial d
ata
for D
M63
2B.
Fram
e D
ata
I
*5
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 20
DM632B
Timing Diagram (Internal-Clock Mode switch to External-Clock Mode)
*2ER
R[0
] is
the
erro
r mes
sage
of
LED
ope
n de
tect
ion.
*3LA
T is
leve
l trig
ger,
not e
dge
trigg
er.
P[1
]
255
256
DAI
DAO
*1
DC
K
LAT
*3
12
256
GC
K
OU
Tn*4
(cur
rent
)
P[0
]Q
[255
]Q
[254
]Q
[0]
Fram
e D
ata
PFr
ame
Dat
aO
high
low
high
low 1 01 0
Q[2
55]
254
P[2
]
1 0
*4Io
ut tu
rn o
ff w
hen
LAT
is h
igh
leve
l ,an
d tu
rn o
n at
the
first
GC
K ris
ing
edge
whe
n LA
T is
low
leve
l.
65
536
GCK
P[2
52]
12
Q[2
54]
R[2
55]
R[2
54]
*1R
EM, A
RM
, IG
M is
con
figer
ed b
y de
faul
t. Th
ey c
an s
witc
h to
FEM
, OSM
, EG
M a
ccor
ding
ly.
All r
egis
ters
in D
M63
2B w
ith b
e re
set w
hen
any
switc
h pr
ocee
s oc
cur.
Fram
eD
ataQ
P[2
53]
(ext
erna
l)
GCK
(inte
rnal
)
high
low
high
low
Cou
nter
re
set
P[2
55]
O[1
]P
[254
]
Don
'ca
ret
ER
R[0
]*2
Don
'ca
ret
Don
'ca
ret
Mod
e sw
itch
perio
dG
rays
cale
dat
a cl
ock-
in p
erio
dG
rays
cale
dat
a cl
ock-
in p
erio
d
*5 P
[255
],P[2
54],…
P[0
],O[1
],Q[2
55].Q
[254
],… Q
[0],R
[255
],R[2
54],…
are
ser
ial d
ata
for D
M63
2B.
*5
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 21
DM632B
Timing Diagram (External-Clock Mode switch to Internal-Clock Mode)
*2ER
R[0
] is
the
erro
r mes
sage
of
LED
ope
n de
tect
ion.
*3LA
T is
leve
l trig
ger,
not e
dge
trigg
er.
R[1
]
255
256
DAI
DAO
*1
DC
K
LAT
*3
12
256
GC
K
OU
Tn*4
(cur
rent
)
R[0
]S
[255
]S
[254
]S
[0]
Fram
e D
ata
RFr
ame
Dat
aQ
high
low
high
low 1 01 0
S[2
55]
254
R[2
]
Cou
nter
re
set
*4Io
ut tu
rn o
ff w
hen
LAT
is h
igh
leve
l ,an
d tu
rn o
n at
the
first
GC
K ris
ing
edge
whe
n LA
T is
low
leve
l.
65
536
GC
K
R[2
52]
12
S[2
54]
T[2
55]
T[2
54]
*1R
EM, A
RM
, IG
M is
con
figer
ed b
y de
faul
t. Th
ey c
an s
witc
h to
FEM
, OSM
, EG
M a
ccor
ding
ly.
All r
egis
ters
in D
M63
2B w
ith b
e re
set w
hen
any
switc
h pr
ocee
s oc
cur.
Fram
e D
ata
S
R[2
53]
[254
]R
(ext
erna
l)
R[2
53]
on off
GC
K(in
tern
al)
1 0 high
low
R[2
55]
Q[1
]E
RR
[0]*2
Don
'ca
ret
Don
'ca
ret
Don
'ca
ret
Mod
e sw
itch
perio
dG
rays
cale
dat
a cl
ock-
in p
erio
dG
rays
cale
dat
a cl
ock-
in p
erio
d
*5 R
[255
],R[2
54],…
R[0
],S[2
55].S
[254
],… S
[0],T
[255
],T[2
54],…
are
ser
ial d
ata
for D
M63
2B.
*5
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 22
DM632B
Output Modulation Technique
DM632B provides a new LED drive technique of output modulation. It mixes traditional Pulse Width Modulation (PWM) represented by LSB 12 bit with Sequential Split Modulation (SSM) represented by MSB 4 bit. The main benefits of SSM are to drive LED with an equivalent higher refresh rate (up to 380Hzn in DM632B when FGCK = 25MHz) and change bit to next bit smoothly. The relationships between PWM and SSM in time domain can be refer to the diagram (not to scale) below:
0000 XXXX,XXXXXXXX
0001 XXXX,XXXXXXXX
0110 XXXX,XXXXXXXX
0111 XXXX,XXXXXXXX
1000 XXXX,XXXXXXXX
1001 XXXX,XXXXXXXX
1110 XXXX,XXXXXXXX
1111 XXXX,XXXXXXXX
Bit[11:0] (PWM)Bit[15:0]
on
off
on
off
on
off
on
off
on
off
on
off
on
off
on
off
t
65536 clocks
Bit[11:8] (PWM)
Bit[11:8] (PWM)
Bit[11:0] (PWM)
Bit[11:0] (PWM)
Bit[11:0] (PWM)
Bit[11:0] (PWM)
Bit[11:0] (PWM)
A complete modulation cycleMSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB
Bit[7:0] (PWM)
Bit[7:0] (PWM)
Bit[7:0] (PWM)
Bit[7:0] (PWM)
Bit [7:0] (PWM)
Bit[7:0] (PWM)
Bit[7:0] (PWM)
Ultra High Resolution Current Outputs
DM632B could provide 16-bit linear PWM control current outputs for each channel. There are two advantages for system design. One is DM632B has sufficient bit resolution (65536 steps), not only LED color information but additional data such as global brightness, dot correction, and gamma correction can be represented by the proper algorithms. The other is to reduce a lot of clock and data rate compared to conventional ON-OFF type LED drivers.
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 23
DM632B
Global Brightness Control DM632B has no built-in global brightness control feature. In order to obtain a lower resolution
of global brightness control effect, two methods could be utilized. Here show different ways to adjust the Rrext value or voltage drop across the external resistor. Please see the reference circuit below:
Output to Output Delay
DM632B has build-in output to output delay with a special arrangement. This arrangement help chip avoid noise cause by large current during channels switching. The arrangement details are shown as following table.
Channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Delay units 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 24
DM632B
Power Dissipation
The power dissipation of a semiconductor chip is limited to its package and ambient temperature, in which the device requires the maximum output current calculated for given operating conditions. The maximum allowable power consumption can be calculated by the following equation:
Pd(max)(Watt) =Tj(junction temperature)(max)(°C)– Ta(ambient temperature)(°C)
Rth(junction-to-air thermal resistance)(°C/Watt)
The relationship between power dissipation and operating temperature can be refer to the figure below:
PD - Ta curve
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 20 40 60 80 100 120 140 160
Ambient Temperature Ta ( ℃ )
Pow
er D
issi
pati
on
Pd(
W)
The power consumption of IC can be determined by the following equation and should be less than the maximum allowable power dissipation:
SSOP24
TSSOP24E
Tj(max)=150°C
Rth(TSSOP24E=30°C/Watt
Rth(SOP24B)=57°C/Watt
Rth(DIP24B)=67°C/Watt
Rth(SSOP24)=70°C/Watt
SOP24B
DIP24B
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 25
DM632B
Typical Application
DM632B DM632B
DM632B DM632B
DM632B
DM632B
DM632B
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 26
DM632B
D
24 13
121
E1 E E2
b1
b
e
L A1A
2
ASEATING PLANE
Package Outline Dimension DM632B-DIPB
DIMENSIONS IN INCH DIMENSIONS IN MM
SYMBOLS MIN. MAX. MIN. MAX.
A - 0.210 - 5.334
A1 0.015 - 0.381 -
A2 0.125 0.135 3.175 3.429
b 0.040 1.016
b1 0.018 0.457
D 0.880 0.920 22.352 23.368
E 0.300BSC 7.620BSC
E1 0.245 0.255 6.223 6.477
E2 0.335 0.375- 8.509 9.525
e 0.070 1.778
L 0.115 0.150 2.921 3.810
Θ 0° 15° 0° 15°
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 27
DM632B
D
24 13
121E
b e 0.004
A
E1
C
DETAIL A
A1
A2 A
LL1
SEATING PLANE
GAUGE PLANE
Package Outline Dimension DM632B-SSOP
DIMENSIONS IN INCH DIMENSIONS IN MM
SYMBOLS MIN. MAX. MIN. MAX.
A 0.053 0.069 1.346 1.753
A1 0.004 0.010 0.102 0.254
A2 - 0.059 - 1.499
b 0.008 0.012 0.203 0.305
C 0.007 0.010 0.178 0.254
D 0.337 0.344 8.560 8.738
E 0.228 0.244 5.791 6.198
E1 0.150 0.157 3.810 3.988
e 0.025 BSC. 0.635 BSC
L 0.016 0.050 0.406 1.270
L1 0.041 BSC 1.041 BSC
Θ 0° 8° 0° 8°
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 28
DM632B
Package Outline Dimension DM632B-SOPB
DIMENSIONS IN INCH DIMENSIONS IN MM
SYMBOLS MIN. MAX. MIN. MAX.
A - 0.075 - 1.900
A1 0.002 0.008 0.050 0.200
A2 0.051 0.067 1.300 1.700
b 0.012 0.020 0.300 0.500
c 0.004 0.010 0.100 0.250
D 0.504 0.520 12.800 13.200
E 0.303 0.327 7.700 8.300
e 0.0394 BSC 1.000 BSC
E1 0.228 0.244 5.800 6.200
L 0.010 0.026 0.250 0.650
θ 0° 10° 0° 10°
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 29
DM632B
S
L
L10.
25m
m
GAUGE PLANESEATING PLANE
D1
E2
24 13
121
be
EE1
D
0.05 A1
A2 A
Package Outline Dimension DM632B-TSSOPE (exposed pad)
DIMENSIONS IN INCH DIMENSIONS IN MM
SYMBOLS MIN. MAX. MIN. MAX.
A - 0.047 - 1.20
A1 0.000 0.006 0.00 0.15
A2 0.031 0.041 0.80 1.05
b 0.007 0.012 0.19 0.30
D 0.303 0.311 7.70 7.90
E1 0.169 0.177 4.30 4.50
E 0.252 BSC 6.400 BSC
e 0.026 BSC 0.650 BSC
L1 0.039 REF 1.000 REF.
L 0.018 0.030 0.45 0.75
S 0.008 - 0.20 -
Θ 0° 8° 0° 8°
E2 0.0898 0.1122 2.280 2.850
D1 0.146 1.819 3.700 4.620
-
16-channel 16-bit PWM Constant Current LED Driver Version:PRE.001 Preliminary Page 30
DM632B
The products listed herein are designed for ordinary electronic applications, such as electrical appliances, audio-visual equipment, communications devices and so on. Hence, it is advisable that the devices should not be used in medical instruments, surgical implants, aerospace machinery, nuclear power control systems, disaster/crime-prevention equipment and the like. Misusing those products may directly or indirectly endanger human life, or cause injury and property loss. Silicon Touch Technology, Inc. will not take any responsibilities regarding the misusage of the products mentioned above. Anyone who purchases any products described herein with the above-mentioned intention or with such misused applications should accept full responsibility and indemnify. Silicon Touch Technology, Inc. and its distributors and all their officers and employees shall defend jointly and severally against any and all claims and litigation and all damages, cost and expenses associated with such intention and manipulation.
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