the 21st ieee international symposium on field-programmable custom computing machines april 28-30,...

The 21st IEEE International Symposium on Field-Programmable Custom Computing Machines

April 28-30, 2013, Seattle, WashingtonConference Review

NUS Presentation Title 2006

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NUS Presentation Title 2006

Conference Overview• Venue: Seattle Marriott Waterfront• 8 sessions: 19 long presentation, 18 short presentations

cum poster, 13 posters• General Chair: Ken Eguro, Microsoft Research,

Program Chair: Miriam Leeser, Northeastern University• ~100 participants• 7 corporate sponsors:

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NUS Presentation Title 2006

Technical Program• Day 1: Panel discussion on “Reconfigurable

Computing in the Era of Post-Silicon Scaling”, Pico Computing Workshop

• Day 2: 4 sessions (Data driven computing, hardware, applications and tools). Demo night banquet.

• Day 3: Solarflare University Programme. 4 sessions (Networking, arithmetic and more applications)

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NUS Presentation Title 2006

Interesting Session Papers

• Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices: Eddie Hung, Fatemeh Eslami, and Steven J. E. Wilton• VTR to Xilinx bitstream via XDL

• Open-Source Bitstream Generation: Ritesh Kumar Soni, Neil Steiner, and Matthew French• Embedded bitstream generation using micro-

bitstreams

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NUS Presentation Title 2006

• PC Software-controlled FPGA via PCIe• Comprehensive C++ API• Hardware comprises of FPGA chip and memory buffer• Mode of computation: Streaming• Complex topologies up to PCIe limit: Daisy chaining,

point-to-point• Software-hardware co-simulation• Application: Migrating PC algorithms to FPGA, bitcoin

mining

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NUS Presentation Title 2006

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NUS Presentation Title 2006

• High throughput, low latency 10 GbE, achieved using kernel bypass for the network controller

• Applications: Kill switch for reversal of/erroneous financial market transactions

• Network filtering• Solarflare University Programme: Academic pricing for

hardware and tools, sponsorship for competitions

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NUS Presentation Title 2006

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NUS Presentation Title 2006

Demo Night Banquet• Microsoft: FPGA accelerated

pose-estimation from depth sensor

• MathWorks: MATLAB-HDL cosimulation & compilation

• Vector Logix: Hardware acceleration of matrix operation

• Paper exhibits: Low latency Ethernet FPGA server, use case: remote surgical operation

• FCCM 20: Best papers from the past 20 years

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NUS Presentation Title 2006

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NUS Presentation Title 2006

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NUS Presentation Title 2006

More Details

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