ultra-dynamic voltage scaling using sub-threshold

Ultra-Dynamic Voltage Scaling Using Sub-threshold

Operation and Local Voltage Dithering in 90nm CMOS

Benton Calhoun and Anantha ChandrakasanMassachusetts Institute of Technology

ISSCC 2005

Ultra-DVS Motivation

• Basics of subVT operation0 0.2 0.4 0.6 0.8 1

10−8

10−6

10−4

10−2

100

Nor

mal

ized

I D

Normalized VGS

Sub-threshold operation: Slow,lower power, minimum energy operation becomes possible

Strong Inversion Operation: fast, power-hungry

Unite the regions

DVS

Dynamic Voltage Scaling (DVS)Time Constraint

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Rate (normalized frequency)

Nor

mal

ized

Ene

rgy

Max rate

Sleep

Dynamic Voltage Scaling with infinite levels savesenergy per sample when the workload varies

DVS

Max rate

Sleep

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Rate (normalized frequency)

Nor

mal

ized

Ene

rgy

Quantizing the voltages decreases complexity, but reduces savings if VDD is constant for time constraint

Time Constraint

Quantized DVS

Gutnik and Chandrakasan, An Efficient Controller for Variable Supply-Voltage Low Power Processing, Symposium on VLSI Circuits, 1996

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Rate (normalized frequency)

Nor

mal

ized

Ene

rgy

Dithering within the time constraint givesaverage energy close to the optimum

Dithering

Need to switch VDD in the timescale of the changing workload:

Existing approaches use 100s of µsecs to switch

Voltage DitheringTime Constraint

Gutnik and Chandrakasan, An Efficient Controller for Variable Supply-Voltage Low Power Processing, Symposium on VLSI Circuits, 1996

Quantized rates

Required rates

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

in (V)

out (

V)

Sub-VT OperationPREVIOUS WORK:

Swanson & Meindl, JSSC,1972Sub-VT model & theoretical limits

Vittoz & Fellrath, JSSC,1977 Analog sub-VT circuits

Vittoz, ISSCC Plenary Talk, 1994

Soeleman & Roy, ISLPED, 1999

Wang & Chandrakasan, ISSCC, 2004

90nm sub-VTInverter VTCs

0 0.2 0.4 0.6 0.8 1 1.2

10−15

10−14

10−13

10−12

VDD

(V)

E/o

p (J

)

Sub-VT Minimum Energy Operation

+=

+=

−

−

th

DD

th

DD

nVV

DPgeffeffDD

nVV

DDgDPeffDDeffTotal

eLKCWCV

eVKCLWVCE

2

22LEAKAGEACTIVETOTAL EEE +=

DDDOFFDDTOTAL TVIVCE +⋅= 2

Gate Leakage Energy

90nm simulationfor 32-bit CLA addershowing minimum energy per operation

Total Leakage Energy

Total Energy

Active Energy

0 0.2 0.4 0.6 0.8 1 1.2

10−15

10−14

10−13

10−12

VDD

(V)

E/o

p (J

)

Reason for Min. Energy Point

Leakage Energy increasesPrimarily because of the Larger delay in sub-threshold

0 0.2 0.4 0.6 0.8 1 1.210

−9

10−8

10−7

10−6

10−5

10−4

VDD

(V)

Delay

Leakage Current

Gate Leakage Energy

Total Leakage Energy

Total Energy

Active Energy

• Test chip to show combination of sub-threshold operation with DVS– Sub-threshold Circuit Considerations– Local Voltage Dithering (LVD)– Ultra-Dynamic Voltage Scaling

Demonstrating UDVS

90nm Test Chip Circuit

32-bit Kogge-Stone

adder

SwitchingControl

Ring oscillatorClock

VDD high(VDDH)

VDD low(VDDL)

Local Voltage Dithering (LVD)- Headers select VDD- Local Block Level

Headers

Test Chip Die Photo

90nm6LM

Adder

AccumulatorHeader Size

Acc. 0 Acc. 1 Acc. 2 Acc. 3

32-bit Kogge-Stone Adder Block

Sum calculation

Propagate, Generate creationPath throughadder treehas invertingstages of dot operators

Kogge-Stone Adder Circuits

G0

G0

G1

G1

P1

P1

P0P1

P0P1

G0

G0

G1

G1

P1

P1

G=G0P1+G1

P=P0P1

P=P0+P1

G=G1(P1+G0)

WeakWeak

Sub-VT Sizing Considerations

0 20 40 60 80 100 120

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

time (ns)

Ratioed FF

Non-ratioed FF

WeakWeak

Strong

Strong

N1 N2 N3

N1 N2 N3

N1

N2

N3

N3, non-ratioed

CK

CK

CK

CK

CK

DQ

D Q

Ratioed FF fails to write a 1 atstrong N, weak P corner at 400mV

Preserving State in Sub-VT

0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.220

0.05

0.1

0.15

0.2

0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.220

0.05

0.1

0.15

0.2

N11

N20

N30 Q=1

0 10 1

N10

N21

N31 Q=010

Hold 1 Failure Hold 0 Failure

N3N1

VDD Q

VDD (V) VDD (V)

N3N1

VDD

Q

Vol

tage

(V)

Vol

tage

(V)

Measured Sub-VT Operation

300mV Clock/1024

Data

0.2 0.4 0.6 0.8 1 1.2

10−16

10−15

10−14

10−13

10−12

VDD (V)

Mea

sure

d T

otal

Ene

rgy

per

Cyc

le (

J)Minimum Energy Measurements

VDDopt = 330mVf = 50kHz

9XTotal Energy

Leakage Energy

0.2 0.4 0.6 0.8 1 1.2

10−16

10−15

10−14

10−13

10−12

VDD (V)

Mea

sure

d T

otal

Ene

rgy

per

Cyc

le (

J)Minimum Energy & Temperature

VDDopt insensitiveto temperature

EL increases becauseVT decreases

VT(T)=VT(T0)-KTµ(T)=µ(T0)(T/T0)-M

ILEAK increases by same amount that TD decreases due to VT

T = 25,50,70,85oC

Measured Standby Power Savings

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.110

−10

10−9

10−8

10−7

VDD (V)

MeasuredExtrapolated

Leakage Current

Standby Power 107X

Measured Flip-flop Retention Voltage: 110mV

35X

Local Voltage Dithering (LVD)

0 0.2 0.4 0.6 0.8 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Rate (normalized frequency)

Nor

mal

ized

Ene

rgy

per

sam

ple

(mea

sure

d)

0.2 0.4 0.6 0.8 110

3

104

105

106

107

108

109

VDD

(V)

Mea

sure

d rin

g os

cilla

tor

freq

uenc

y (H

z)

T = 25,50,70,85oC

340MHz, 1.1V

50kHz, 330mV

7kHz, 250mV

Timing Overhead for LVD

ThresholdCounter<Threshold

Counter ClockGating

Start

Gate

Dither

Dither Dither

Clock

Clock/1024Clock/1024

VDDL=0.9V, rate=0.5 VDDL=0.6V, rate=0.04

Switching Energy

For test chip,CNORM=3.7

LVD Circuit Issues

01

VDDH=1.0VVDDL=0.3V

1.0V

01

VDDH=1.0VVDDL=0.3V

1.0VTie header bulks to VDDH

VDDHVDDL CNORM normalizes ESW to E of circuit at VDDH

N is number of cycles spent at VDDL to break-even: 222

DDHNORMDDLDDH VCNVNV +≥

)( 22

2

DDLDDH

DDHNORM

VVVCN−

≥

UDVS Results

10−5

10−4

10−3

10−2

10−1

100

10−6

10−5

10−4

10−3

10−2

10−1

100

Rate (normalized frequency)

Nor

mal

ized

Ene

rgy

per

sam

ple

(mea

sure

d)

No ditheringideal DVSDithered

2X

9X

Dithering close to ideal

Dither during high performance operation and switch to sub-threshold minimum energy operation when speed is not important

1.1V, 340MHz

0.8V, 100MHz

0.33V, 50kHz

10−5

10−4

10−3

10−2

10−1

100

10−6

10−5

10−4

10−3

10−2

10−1

100

Rate (normalized frequency)

Nor

mal

ized

Ene

rgy

per

sam

ple

(mea

sure

d)No ditheringideal DVSDithered

10−5

10−4

10−3

10−2

10−1

100

10−6

10−5

10−4

10−3

10−2

10−1

100

Rate (normalized frequency)

Nor

mal

ized

Ene

rgy

per

sam

ple

(mea

sure

d)

No ditheringideal DVSDithered

UDVS Flexibility1.1V, 340MHz

Closer to ideal over high performance range

1.1V, 340MHz

0.8V, 100MHz

0.5V, 2.4MHz

0.8V, 100MHz

0.6V, 13MHz

Closer to ideal over full range

Choose dithered voltages to match application of interest

Providing UDVS Voltages

Can implement UDVS with 3 headers OR two headers and an adjustable voltage supply

VDDH

VDDL- adjustable

UDVS Block

VDDHVDDL VDDM

UDVS Block

UDVS System Example

Different blocks can voltage dither based on their own workload for optimal efficiency

VDDH

VDDL (adjustable)

UDVS Block UDVS BlockUDVS Block

Level conversion

Level conversion

Level conversion

Bus

Conclusions

• Local voltage dithering allows near-optimum savings for high performance, variable rate systems

• Sub-threshold allows minimum energy operation• UDVS allows performance and energy scaling

over the full operational range of VDD

Acknowledgements: Funded by Texas Instruments and DARPA through a subcontract with MIT Lincoln Labs