vvs esglsi designce.sharif.ir/courses/91-92/1/ce353-1/resources/root...topics pseudo-nmos gates....

VLSI DesignV S es gLecture 9: MOS Logic Familiesg

ShaahinShaahin HessabiHessabiShaahinShaahin HessabiHessabiDepartment of Computer EngineeringDepartment of Computer Engineering

Sharif University of TechnologySharif University of TechnologySharif University of TechnologySharif University of TechnologyAdapted with modifications from lecture notes prepared Adapted with modifications from lecture notes prepared by the by the

book’s author book’s author (from Prentice Hall PTR)(from Prentice Hall PTR)

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Topics

Pseudo-nMOS gates.DCVS logic.Domino gatesDomino gates.Design-for-yield.G IPGates as IP.

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Pseudo-NMOS

Uses a p-type transistor as a resistive pullup, n-type network for pulldowns.

Consumes static power.Has much smaller pullup network than static gate.gPulldown time is longer because pullup is fighting.pullup is fighting.

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Output voltages

Logic 1 output is always at VDD.g p y VDD

Logic 0 output is above Vss.VOL = 0.25 (VDD - VSS) is one plausible choice.VOL 0.25 (VDD VSS) is one plausible choice. Pull-down resistance ≤ (1/3 to 1/4 pull-up resistance)

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Producing output voltages

For logic 0 output, pullup and pulldown form a voltage divider.Must choose n/p transistor sizes to create effective presistances of the required ratio.Effective resistance of pulldown network must beEffective resistance of pulldown network must be comptued in worst case; series n-types means larger transistorstransistors.

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Transistor ratio calculation

For creating logic 0 output, (initially): pullup is in linear region,Vdsp = Vout - (VDD - VSS) ; pulldown is in saturation Vdsn = (VDD – VSS )Pullup and pulldown have same current flowing through them; i.e., - Idp = Idndp dn

For equal noise margins, using 0.5 m parameters, 3.3V power supply:3.3V power supply: (Wp/Lp) / (Wn/Ln) = 3.9

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DCVS logicg

DCVSL = differential cascode voltage switch logicDCVSL differential cascode voltage switch logic.Static logic.C i (lik d d CMOS)Consumes no static power (like standard CMOS)Uses latch to compute output quickly.Requires true/complement inputs, produces true/complement outputs.p p

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DCVS structure and operation

Exactly one of true/complement pulldown networks will complete a path to the power supply.Pulldown network will lower output voltage, turning on other p-type, g p yp ,which also turns off p-type for node which is going g gdown.

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DCVS Example

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Precharged logic

Precharged logic uses stored charge to help evaluation.Precharge node, selectively discharge it.g y gTake advantage of higher speed of n-types.Requires multiple phases for evaluationRequires multiple phases for evaluation.

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Domino logicg

Uses precharge clock to compute output in two phases:Uses precharge clock to compute output in two phases:

h precharge; evaluate.

Not a complete logic family; cannot invert.

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Domino phasespControlled by clock .Precharge:: p-type pullup precharges the storage node; inverter ensures that output goes low.Evaluate:: storage node may be pulled down, so output goes up.p g p

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Domino operation

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Domino effect

Gate outputs fall (rise) in sequence:

gate 1 gate 2 gate 3gate 1 gate 2 gate 3

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Monotonicity

Domino gates inputs must be monotonically g p yincreasing: glitch causes storage node to discharge.

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Output buffer

Output inverter is needed for two reasons:1. make sure that outputs start low, go high so that domino

output can be connected to another domino gate;» Can it be avoided by using an NMOS (controlled by ø)

in series with the pull-down (footed domino)? • (consider two cascaded gates)

2. protects storage node from outside influence.

Storage node and inverterStorage node and inverter have correlated values.

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Using domino logic

Can rewrite logic expression using DeMorgan’s Laws:g p g g (a + b)’ = a’b’ (ab)’ = a’ + b’ (ab) a b

Add inverters to network inputs/outputs as required.

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Charge-Storage Principle

Node X holds charge for “long” periodstH: time to bring node X from Vdd to 0.5 Vdd

Cx: dynamic node capacitance = Cox WLFor 0.25 micron technology:

tclk << tH for dynamic circuits to work.Future trends: Cx decreases; Vdd decreases; Ileakage increases. This implies tH decreases but so does tclk.

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Use a keeper transistor

Domino and stored charge

Charge can be stored in source/drain connections between pulldowns.Stored charge can be sufficient to affect prechargeg p gnode.Can be averted by precharging the internal pulldownCan be averted by precharging the internal pulldownnetwork nodes along with the precharge node.

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Charge-sharing

S l iSolution:– Make C1 >> C2

– Reduce Vt of the output inverter– Use a keeper/bleeder transistor– Use Multiple precharge transistors

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Dynamic logic vs. static logic

Faster Used in data-paths of high performance microprocessors.

Smaller areaSmaller area.Extra clock signal. C t Consumes extra power.

Dynamic power depends upon probability of logic l h h b bili f i ivalues rather than probability of a transition.

Susceptible to noise. Careful physical design required.

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Design-for-yield

Design processes that improve chip yield in very deep submicron/nanometer technologies.Must treat design and manufacturing as a unified g gprocessing to maximize yield in nanometer technologies.g

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Variations in manufacturing

Three types of variations:1. Systematic variations: can be predicted based on design and

mask information plus manufacturing equipment.2. Random variations: include variations in parameters, etc.3. Environmental variations: include temperature, etc.

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Trends in manufacturing

Larger variations in process and circuit parameters.Higher leakage currents.Patterning problems caused by specific combinations ofPatterning problems caused by specific combinations of geometric features.Metal width and thickness variationsMetal width and thickness variations.Stress in vias.

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Design-for-yield examples

Lithographic simulation to find yield problems not covered by standard design rules.Extra vias added to increase the reliability of yconnections.Statistical timing analysis to identify problems causedStatistical timing analysis to identify problems caused by variations in wiring.

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Gates as IP

The standard cell library was one of the first forms of IP. Reusable across many chips. Portable from one process to another.

Standard cell compatibility issues:S d d ce co p b y ssues: Layout: cell size, pin placement. Delay: driving specified load. Delay: driving specified load. Power consumption.

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Standard cell physical design

Basic cell organization is dictated by placement and routing system.All cells are the same height.g May be one of a set of standard widths.

Pins must be placed on routing grid usually determinedPins must be placed on routing grid, usually determined by wiring layers used.

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Standard cell logical design

Must support a Boolean complete set of functions.Should support enough gate types for good logic synthesis results.yNeed several electrical variations of each function: Low power Low power. High speed.

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Cell verification and qualification

Cells are verified by layout extraction and circuit simulation. Simulate a variety of process parameter combinations.

Qualification requires fabrication of cells on the target process.p

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