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An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget Represented by: Majid Malaika Authors: Canturk Isci†, Alper Buyuktosunoglu†, Chen-Yong Cher†, Pradip Bose† and Margaret Martonosi

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An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for

a Given Power Budget

Represented by: Majid Malaika

Authors: Canturk Isci†, Alper Buyuktosunoglu†, Chen-Yong Cher†, Pradip Bose† and Margaret Martonosi

Computer Science and Engineering

Agenda

Background Motivation Contribution Overview of the global power management policy Core Power Modes Global Power Management Policies Independent Per-Core Power Management Simulation Evaluation Q&A

Computer Science and Engineering

Background

Power Management are desired for many reasons: For portable devices For Desktop systems For Supercomputers

P = V^2 * F Power is proportional to voltage squared Current is also proportional to voltage

Computer Science and Engineering

Cont. Background

Multicore architecture has become more important than ever due to the Famous “Walls”

With more cores on the dice, Power and temperature problems are becoming more and more crucial

Computer Science and Engineering

Motivation

How to enforce a power budget through global power manager? How to minimize power given a performance target?

Computer Science and Engineering

Contributions

Introduced the concept of Global Power Manager (PM) Developed a fast static power management analysis tool Evaluated different PM policies (with different focus such as

prioritization, fairness, throughput)

Computer Science and Engineering

Global CMP Power Management Overview

To exploit the widely known variability in demand and characteristics of the input workloads

Adaptive response to “Phases” for power-efficient computing.

Computer Science and Engineering

Cont. Global CMP Power Management Overview

Computer Science and Engineering

Cont. Global CMP Power Management Overview

the loop of PM’s work PM periodically collects power-performance data from local monitors PM reports it to OS OS returns power budget, thread affinities, high-level scheduling and

load-balancing plan to PM PM decides the power-mode of each core based on those info

Computer Science and Engineering

Cont. Global CMP Power Management Overview

Preconditions Each core has its own dynamic controller has its power-performance monitor (e.g. current monitor,

perf monitoring counter hw) can be running in multiple power modes

Computer Science and Engineering

Core Power Modes

Three Power Modes: Turbo Efficient1(Eff1) Efficient2(Eff2)

The target is to achieve

PowerSavings : PerformanceDegradation ratio of 3 : 1

Computer Science and Engineering

Cont. Core Power Modes

Target

Computer Science and Engineering

Cont. Core Power Modes

Transition overhead between Power Modes The duration of each monitored interval is called “Explore

time” and is set to 500 MS. Low overhead (1 to 4%)

Computer Science and Engineering

Global Power Management Policies

Introduced three policies for different objectives:

Priority PullhiPushLo MaxBIPS

Computer Science and Engineering

Cont. Global Power Management Policies

Priority Assigns Different Priority to different tasks Highest Priority to highest Core (Example Core4) Lowest Priority to Lowest Core (Example Core1) In policy implementation it tries to run the highest AFAP Prefer to slow down the first core in case of budget

overshoot

Computer Science and Engineering

Cont. Global Power Management Policies

PullhiPushLo Tries to balance the power consumption of each core It slows down the highest core in case of a budget

overshoot And by speeding up the lowest power core when there

is available

Computer Science and Engineering

Cont. Global Power Management Policies

MaxBIPS Targets at optimizing the system throughput Predicts and choose the Power Mode that Maximizes

the throughput at each explore time

MaxBIPS does that by predicting the corresponding power and BIPS values for each power mode

It then chooses the combination with the highest throughput that satisfies the current power budget

Computer Science and Engineering

Independent Per-Core Power Management

Chip-Wide DVFS Simpler alternative No Synchronization across cores Simplified OS and Hardware All cores transition together into Turbo, Eff1, Eff2 at

each explore time based on budget constraints

Computer Science and Engineering

Simulation

Based on IBM Turandot simulator Power statistics from IBM PowerTimer The list of core parameter

Computer Science and Engineering

Cont. Simulation

Target 3:1

Estimation

Computer Science and Engineering

Evaluation

Computer Science and Engineering

Cont. Evaluation

Computer Science and Engineering

Cont. Evaluation

Computer Science and Engineering

References

C. Isci et al., "An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget"

Computer Science and Engineering

Q&A

The End