Living in a 3D World: Why not Make 3D Integrated Circuits?

Yang (Cindy) YiElectrical Engineering and Computer Science

University of Kansas

Outline• Introduction• Advantages of 3D IC• 3D IC Development and Challenges • Through Silicon Via (TSV) Modeling and

Design• 3D Stacking for Neuromorphic Computing • Summary

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Living in a 3D World

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Why not Make 3D Circuit?

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What is 3D Integrated Circuit• A chip with active

electronic components stacked on one or more layers.

• Each block placed on a separate layer of Si.

• Each die is stacked on top of another and communicated by Through-Silicon Vias (TSVs).

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Source: ITRI

3D IC is like a 3D Hamburger

Source: Terahertz Interconnection and Package Lab at KAIST

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3D IC is also like a 3D Skyscrapers

New York City in 1800 New York City in 2000

3D space with skyscrapers

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Package FunctionProvides mechanical, electrical, and thermal connections necessary for system functionality.

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Traditional Technologies

Wire bonding Flip Chip

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Device Packaging – Changing Landscape

Critical performance metrics are shiftingfrom CMOS Scaling and Package Form Factor to SYSTEM LEVEL Power Consumption and Bandwidth.

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Communication Bottleneck• Architectural issues

– Traditional shared buses do not scale well – bandwidth saturation

– Chip IO is pad limited• Physical issues

– On-chip Interconnects become increasingly slower w.r.t. logic

– IOs are increasingly expensive• Consequences

– Performance losses– Power/Energy cost– Design closure issues or

infeasibility

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Vertical IntegrationOne solution: Go vertical!• Dies with different functions fabricated with

different technologies are integrated.

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Schematic of a System-on-a-Chip design using a planar (2-D) IC

Schematic of a 3-D chip showing integrated heterogeneous technologies

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Example• Apple A4 Chip (for 1st Gen iPad and iPhone 4)

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Off-chip vertical connectionsSource: Apple Inc.

3D IC Market Drivers

Form factor driven

Density Achieving the highest capacity / volume ratio “Short term”

driver: > 2008

Cost driven

3D vs. “More Moore” Can 3D be cheaper than going to the next lithography node?

“Long term” driver: > 2012

3D ICOptimum Market

Access Conditions

CPU GPU

MEMS

CIS

DRAM

Flash

RF

Performance driven

Heterogeneous integration Co-integration of RF + logic + memory + sensors in a reduced space

Electrical performance Interconnect speed and reduced parasitic power consumption

“More than Moore”

Source: Yole Development

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System in Package (SiP)

Long Interconnection Long RC Delays High Impedance for Power Distribution

Network High Power Consumption Poor Heat Dissipation (Thick Substrate)

Bonding Wire located in Chip Perimeter Low Density Chip Wiring Limited Number of I/O Limited I/O Pitch Large Area Package

Wire Bonding Stacked Chip Package

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3D IC with TSVs

Short Interconnection Reduced RC Delays Low Impedance for Power

Distribution Network Low Power Consumption Heat Dissipation Through Via

No Space Limitation for Interconnection High Density Chip Wiring No Limitation of I/O Number No Limitation of I/O Pitch Small Area Package

First Chip

Second Chip

Bottom Chip

TSV

Bump to TSV

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Benefit of 3D IC with TSVs3D IC is considered one of the most promising alternatives at the limit of device scaling:

• Reduced interconnect length• Reduced delay• Comparable with current technology• Heterogeneous integration

Through-silicon vias (TSVs) for vertical signal link

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Example

Source: Samsung

Source: Samsung Inc.

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Manufacturing Cost Reduction

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Source: Market trends & Cost analysis for 3D ICs, JC Eloy

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3D IC Applications

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Source: QUALCOMM Inc.

Market Evolution

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Challenges & Opportunities in EDA

Challenges

Design3D IC EDA Tool Environment3D IC Design Flow from IC to System

ElectricalTSV Modeling and Characterization System-level Signal Integrity/Power Integrity

Thermal3D IC Thermal ModelsThermally Aware Design & Management

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3D IC Modeling and Design

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TSV Structures• TSVs are fabricated by high aspect ratio deep silicon etching, lining

with dielectric layer, and super conformal filling with copper.

• A metal insulator semiconductor (MIS) device in which a dielectriclayer SiO2 is deposited to isolate the metals from the substrate.

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TSV MIS Interface• TSV MIS interface can be in

accumulation, depletion, inversion regions.

• Flat Band Voltage VFB

• if V < VFB, the positively charged holes in silicon are dragged to Si-SiO2 interface, and an accumulation layer is formed.

• if V > VFB, holes are pushed away and a depletion region is formed.

SFB m si

ox

QVC

ϕ ϕ= − −

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TSV Capacitance Table

High Frequency Effect• Skin/Proximity effects

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Proximity effect:opposite currents in nearby conductors attract each other

Skin effect:high frequency currents crowd toward the surface of conductors

Simple Example

Resistance increases

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Skin Effect The field amplitude decreases exponentially into the

thickness of the conductor – skin depth Defined as the penetration depth at a given frequency

where the amplitude is attenuated 63% (e-1) of initial value

µπρδf

=

Skin Depth In Copper

0

1

2

3

4

5

6

7

8

9

10

0.E+00 1.E+09 2.E+09 3.E+09 4.E+09 5.E+09 6.E+09

Frequency, Hz

Skin

Dep

th, m

icro

ns

X

Ampl

itude

Penetration into conductor

Electromagnetic Wave

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TSV Rough Surface• Mainly occurred due to the etching of TSV and the poor

polymer deposition during passivation.

• At ultra high frequency, TSV skin depth and root-mean-square (rms) height of the rough surface are comparable.

• Badly impact on current flowing through TSV in highfrequency range.

Figure courtesy: Tomoji Nakamura et al28DASS 2016

Small Perturbation Method• Analyze the effect of surface roughness at millimeter wave

frequencies by using analytic small perturbation method.• Analytical expression of modeling and associated

equivalent circuit are based on these structures.

Signal TSV Ground TSV

TSV pair with surface roughness

Signal TSV Ground TSV

TSV pair without surface roughness

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Skin Effect and Surface Roughness ModelingConsidering the skin effect in high frequency TSV, additional

resistance and inductance occurs.

Using Gaussian distribution function, an increased in conductorresistance due to the roughness of TSV.

𝐿𝐿0 =𝜇𝜇𝜇2𝜋𝜋

𝑙𝑙𝑙𝑙 1 +2.84𝜇𝜋𝜋𝜋𝜋

+𝑅𝑅02𝜋𝜋𝜋𝜋

𝑅𝑅𝑆𝑆 =𝑎𝑎 𝜇 − 𝑎𝑎𝜎𝜎𝑔𝑔3 2𝜋𝜋

𝑒𝑒− ℎ−𝑎𝑎 2

2𝜎𝜎𝑔𝑔2𝑘𝑘𝑐𝑐

𝜎𝜎𝑐𝑐𝑐𝑐𝜋𝜋 𝑟𝑟 + ∆𝑥𝑥 2 − 𝑟𝑟2

𝑅𝑅0 =𝜇

𝜎𝜎𝜋𝜋 𝑟𝑟2 − 𝑟𝑟 − 𝜎𝜎𝐶𝐶𝑐𝑐 2

=𝜇𝜋𝜋𝜎𝜎𝐶𝐶𝑐𝑐

𝑑𝑑 𝜋𝜋𝜋𝜋𝜇𝜇0𝜎𝜎𝐶𝐶𝑐𝑐 − 1

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Pseudo-random data transmitted over wafer level, chip level, and interposer TSV.

Eye Diagram of TSVs

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TSV Design Optimization

• Smaller TSV capacitance -> faster signal response and lower signal distortion.

• Nature of TSV C-V characteristics depends on TSV process and architecture.

• Achieve minimum TSV capacitance in the desired operating voltage region by tuning TSV process and geometry parameters.

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Static C-V Curve of MIS

Eye Diagram of Interposer TSV• Optimize TSV depletion capacitance at 25 Gbps.• Achieved by biasing the TSV into the deep depletion

region with low work function metal for p-type Si.

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Outline• Introduction• Advantages of 3D IC• 3D IC Development and Challenges • Through Silicon Via (TSV) Modeling and

Design• 3D Stacking for Neuromorphic Computing• Summary

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Neuromorphic Computing

• Inspired by the working mechanism of human brain• Use analog, digital, mixed-mode very-large-scale integration

(VLSI) circuits to implement the neural systems

Computers will help people to understand brains better; understanding brains will help people to build better computers.

http://www.economist.com/news/science-and-technology//better-and-understanding-brains

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Who is this Guy?

Albert Einstein

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Brain Inspired vs. Traditional Computing

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Human Brain Traditional Computers(example taken Tianhe-2)

Speed: 10 PFLOPS (Floating-pointOperations Per Second)

Speed: 33.86 PFLOPS

Storage: 3.5 PB (1000 terabytes) Storage: 12.4 PBWeight: 1350 g Weight: 10 Tons (9.07e7 g)Power: 20 W Power:17.6 MegaWatt

Cost: $390 millionSize: 1195 cm3

(1 http://www.thehindu.com/sci-tech/health/medicine-and-research/brain-circuits-behind-hearing-develop-without-sensory-experience/article477048.ece)

Size: 7,750 sq. ft.(2 http://spectrum.ieee.org/techtalk/computing/hardware/chinese-supercomputer-tianhe2-continues-reign-as-worlds-best-super-computer)

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Biological vs. Hardware

“Neuromorphic Architectures” James Kempsell

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3D Stacking is Essential for Neuromorphic IC

IBM TrueNorth Chip:• Neurosynaptic core contains 256

neurons, and a 64k synaptic crossbar. • 4096 neurosynaptic cores in a 2-D array

occupies 4.3 cm. • Consumes 65 mW of power while

running a typical computer vision application.

2

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Source: IBM Inc.

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DARPA SyNAPSE 16 chip board with IBM TrueNorth Source: IBM Inc.

Neuromorphic 3D Stacking

• Provide massive parallelism among neurons that is required for highlydemanding computational task.

• Offer high device integration density using fast and energy efficient link.

• Provide higher bandwidth and lower routing cost between the layers byminimizing the obstacles introduced by 2D circuits.

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2D vs. 3D

The Improbable But Highly Appropriate Marriage of 3D Stacking and Neuromorphic Accelerators

Characteristics and breakdown of (two-layer) 3D circuit.

Characteristics and breakdown of (two-layer) 2D circuit.

2D over 3D ratios for main characteristics: time to process an image, energy per image, energy per spike, power, area.

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Step Response

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Summary• 3D IC is considered one of the most emerging technologies

at the limit of device scaling.• Needs strong EDA tools for automated design.• Our study helps in developing design guidelines for TSVs in

3D IC.– Proposed an accurate broadband circuit model. – Optimized the parameters of TSVs architecture and manufacturing

process to obtain the minimum depletion.

• 3D stacking is essential for neuromorphic IC design.

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IC

Thank you very much!