chapter 16 analog integrated circuit design techniquesee255d3/files/mcd4thedchap16... · chapter 16...

Chapter 16Analog Integrated Circuit

Design Techniques

Jaeger/Blalock 7/28/10

Microelectronic Circuit Design, 4E McGraw-Hill

Chap 16-1

Design Techniques

Microelectronic Circuit DesignRichard C. Jaeger

Travis N. Blalock

Chapter Goals

• Understand bipolar and MOS current mirror operation and mirror ratio errors.

• Explore high output resistance current sources.• Design current sources for both discrete and integrated applications.• Study reference current circuits such asVBE-based reference, bandgap

reference and Widlar current source.• Use current mirrors as active loads in differential amplifiers to increase

voltage gain of single-stage amplifiers.• Study effects of device mismatch on amplifier performance.• Analyze design of classic µA741 op amp.• Increase understanding of SPICE simulation techniques.



Chap 16-2

MOS Current Mirrors: DC Analysis

)1(1 DS1

Vn

KREF

2I

TNVGS1

Vλ+

+=

+−==DS2

VTNVGS2

VnK

D2I

OI λ1

2

2

∴IO

= IREF

1+λVDS2( )

+λ( )≅ IREF



MOSFETs M1 and M2 are assumed to have identical VTN, Kn’ , λ, and W/L ratios.

IREF provides operating bias to mirror.

VDS1= VGS1= VGS2=VGS

O REF1+λV

DS1( ) REF

However, VDS1 is not equal to VDS2and there is slight mismatch between output and reference currents. Mirror ratio is:

MR =IO

IREF

=1+λV

DS2( )1+λV

DS1( )Chap 16-3

MOS Current Mirror (Example)

Problem:Calculate output current for given current mirror.

Given data: IREF = 150 µA, VSS = 10 V, VTN = 1 V, Kn = 250 µA/V 2, λ = 0.0133 V-1

Analysis: (1+ λ VDS1) term is neglected to simplify dc bias calculation.

VDS1=VGS1=VTN +2IREF

K=1V + 2(150µA)

µA= 2.10V



VDS1=VGS1=VTN + REFKn

=1V +250µA

V 2

= 2.10V

∴IO= (150µA)1+ 0.0133

V(10V)

1+ 0.0133V

(2.10V)

=165µA

Actual currents are found to be mismatched by approximately 10%.

Chap 16-4

MOS Current Mirrors: Changing Mirror Ratio

11

=LW'nK

nK

22

=LW'nK

nK

∴IO

= IREF

Kn2

1+λVDS2( )

Kn1

1+λVDS1( )

W

L

1+λV

DS2( )



Mirror ratio can be changed by modifying W/L ratios of the two transistors forming the mirror.

= IREFL

2

1+λVDS2( )

WL

1

1+λVDS1( )

MR =

W

L

2

1+λVDS2( )

W

L

1

1+λVDS1( )

In given current mirror, Io =5IREF. Again mismatch in VDS causes error in MR.

Chap 16-5

Bipolar Current Mirrors: DC Analysis

+=A

VCE

V

TVBE

VS

IC

I 11exp1

+=A

VCE

V

TVBEV

SI

CI 21exp

2

+=A

VCE

V

FOF11

1ββ

+=A

VCE

V

FOF21

2ββ

=VBEVS

I

BI exp

1 β

=TV

BEVSI

BI exp

1 β



BJTs Q1 and Q2 are assumed to have identical IS, VA, βFO, and W/L ratios.

Io = IC2, IREF = IC1 + IB1 + IB2

VBE1= VBE2 =VBE

∴ IO

= IREF

1+(VCE2

/VA

)( )1+

VCE2V

A

+ 2β

FO

Finite current gain of BJT causes slight mismatch between Io and IREF.

)/2(11MR

FOREFIOI

β+==

=TV

FOB

I exp1 β

TV

FOB1 β

Chap 16-6

Current Mirror (Example)

Problem:Calculate and compare mirror ratios for BJT and MOS current mirror.

Given data: IREF = 150 µA, VGS = 2 V, VDS2 = VCE2 = 10 V, λ = 0.02 V-1

VA = 50 V, βFO = 100, VSS = 10 V, M1 = M2, Q1 = Q2.

Analysis: ( )1=

+= DS2

Vλ



( )( ) 15.11

1

MOSMR =+

+=

DS1V

DS2V

λ

λ

( )16.1

21

)/(1

BJTMR =

++

+=

FOAVCE2

VA

VCE2

V

β

Chap 16-7

Bipolar Current Mirrors: Changing Mirror Ratio

Emitter area scaling changes the transport equations using which,

IO

= nIREF

1+(VCE2

/VA

)( )1+

VCE2V

A

+ 1+n

βFO

E1

AE2

An=



Mirror ratio can be changed by modifying the emitter area of the transistor.

AE

A

SOI

SI =

Ideally, MR= n, but for finite gain,

A FO

FO

n1

n

β+

=MR

Chap 16-8

Multiple Current Sources

• Reference current enters diode-connected transistor M1 establishing gate-source voltage to bias M2 through M5, each with different W/L ratio.

• Absence of current gain defect permits large number of MOSFETs to be driven by one reference transistor.



one reference transistor.

• Similar multiple bipolar sources can be built from one reference BJT.

• As base current error term worsens when more BJTs are added, umber of outputs of basic bipolar mirror are limited.

Chap 16-9

Buffered Bipolar Current Mirror

Assuming infinite Early voltage for simplicity,

( )FO3

FO1

CI

n

REFI

B3I

REFI

C1I

β

β

+

+

−=−=1

1)1(



When large mirror ratio is used or if many source currents are generated from one reference BJT, current gain defect worsens.

Current gain of Q3 is used to reduce base current that is subtracted from reference current.

)1()1(1

1

FO3FO1

nREFnIC1

InO

I

ββ +++

==

Thus error term in denominator is reduced.

Chap 16-10

Output Resistance of Current Mirrors

This simplifies the ac model of the current mirror. Similar analysis applies to MOSFET current mirror except that the current gain is infinite. Thus

rR =



For diode connected BJT, from small-signal model,

mgR

gogmg1

iv

v)(i

≅=∴

++= π...If βoand µF >>1

orA2

VCS

VoroutR

≅=

2

2CS

Vλ1=

Chap 16-11

Two-port Model for Current Mirror

Since current mirror has a current input and current

n

mgm

g

rm

g

rm

gh

mgg

mg

h

=≅+

==

=

≅+

==

=

1

2

211

22

02

v1i2

i21

1

1

21

1

02

v1i1

v11

π

π

π0

01i2

v1v

12=

==h

2

1

01i2

v2i

22or

h ==

=



current input and current output, we use h-parameters.

2v

221i

212i

2v

121i

111v

hh

hh

+=+=

For MOS current mirrors,

1

111

mg

h = 012

=h

n

mgm

gh ≅≅

1

221

2

122

or

h =

Chap 16-12

Bipolar Widlar Current Source

Current through R is given by:

If transistors are matched,

=−

=1

2ln212

SIS

I

OIREF

I

RT

V

RBE

VBE

V

EI

==1

2ln2

EAE

A

OIREF

I

RT

V

EIFO

I α



R in Widlar source allows adjustment of mirror ratio.

≅+=1

ln

1

1ln1

SIREF

I

TV

SIREF

I

TVBE

V

≅+=2

ln

2

1ln2

SI

OI

TV

SI

OI

TVBE

V

Typically 1 < K < 10.

1EA

OIR

A2VK

CSV

oKr

SIS

I

OIREF

I

or

Rm

goroutR

≅

=

+=

+≅

21

2ln12

21

2

Chap 16-13

MOS Widlar Current Source

If IO is known, IREF can be directly calculated. If IREF , Rand W/L ratios are known, we can write a quadratic equation in terms of

−=2

)/(1)/(

11

21LW

LW

REFIO

I

nKREFIR

REFI

OI



equation in terms of

Small-signal model for MOS Widlar source represents a C-S stage with resistor R in its source.

Current through R is given by:

−=

−

=−

=

2)/(1)/(

11

21

2

2

1

2

21

LW

LW

REFIO

I

nKREF

I

R

Rn

KO

I

nKREF

I

RGS

VGS

V

OI

+=∴ Rm

goroutR

21

2

REFIO

I /

Chap 16-14

MOS Wilson Current Source

1

2

nKREF

I

TNVGS

V +=where

1v3gsv3xi1

v3

vxv

+−=

+=

or

mg

From small-signal model,



During operation, all transistors are in active region. ID2 = IREF , ID3 = ID1

= I O, VGS3= VGS1=VGS

I D2 = ID1

1+ 2λVGS( )

1+ λVGS( )

IO = I REF

1+ 2λVGS( )

1+ λVGS( )

13gs3x

om

32212

23xixv

or

ffforoutR µµµ ≅++≅=∴

)1

v2

(

1

xi1

v2

vgsvf

mg

µ−−=−=

3

2λ

µf

CSV ≅

Chap 16-15

Bipolar Wilson Current Source

IO

= IREF

1+(VBE

/VA

)( )1+ 2

βFO

(βFO

+2)+

2VBE

VA

Addition of extra BJT can balance the circuit and reduce errors.



During operation, all transistors are in active region. But some current is lost at base of Q3 and current gain error is formed by Q1 and Q2.

IREF = IC2 + IB3

VCE1 = VBE VCE2 = 2VBE 233 o

ro

outRβ

≅2

AVo

CSV

β≅

circuit and reduce errors.

VCE2 = VBE+VBE3 -VBE4

= VBE

Chap 16-16

MOS Cascode Current Source

ID1 = ID3 = IREF Also IO = ID4 = ID2. So current mirror forces output current to be approximately equal to the reference current. If all transistors are matched with equal W/L ratios,

VDS2= VGS1+ VGS3-VGS4 = VGS= VDS1



From the small-signal model,

242414 or

for

mg

oroutR µ≅+=

4

4

2

4λ

µ

λ

µff

CSV ≅≅

Chap 16-17

Bipolar Cascode Current Source

IC1 = IC3 = IREF Also IO = IC4 = IC2. So current mirror forces output current to be approximately equal to the reference current. If all transistors are matched,

VCE2 = VBE1+ VBE3 -VBE4 = VGS= VCE1



From the small-signal model,

244 o

ro

outRβ

≅2

44 AV

oCS

Vβ

≅

Chap 16-18

Electronic Current Source Design Example

Problem: Design IC current source to meet given specifications.Given data: IREF = 25 µA, VSS = 20 V, λ = 0.02 V-1 , VTN = 0.75 V, Kn’ = 50 µA/V2,VA

= 50 V, βFO = 100, ISO = 0.5 fAAnalysis: MR <0.1 % requires output current of 25 µA±25 nA when output voltage is

20 V. Choose 1GΩ for safety margin.

Rout ≥ 20V25nA

= 800 MΩ 25,000V)A(1G25 =Ω=∴ µCS

V



Cascode or Wilson source’s voltage-balanced MOS version must be used to meet this value of VCSand for small MR. We can choose cascode source as it doesn’t involve internal feedback loop.W/L ratios are all same as MR=1.

Using µf =500, λ =0.02/V and ID =25 µA gives value of Kn=1.25 mS. Since Kn = Kn’(W/L) we need a W/L ratio of 25/1 for given technology.

DIDInKormg

CSV

f λλµ 12500V000,25V02.0 ≅====

Chap 16-19

Comparisons of the Basic Current Mirrors



Chap 16-20

Reference Current Generation

• Reference current is required by all current mirrors.

• When resistor is used, source’s output current is directly proportional to VEE.

• Gate-source voltages of MOSFETs can be large and several

RBE

VEE

V

REFI−

=



• Gate-source voltages of MOSFETs can be large and several MOS devices can be connected in series between supplies to eliminate large resistors.

VDD + VSS= VSG4+ VGS3+ VGS1 and ID3 = ID1 = I 4

• Change in supply directly alters gate-source voltage of MOSFETs and the reference current.

• BJTs can’t similarly be connected in series due to small fixed voltage developed across each diode and exponential relationship between voltage and current.

Chap 16-21

Supply-Independent Biasing: VBE -based Reference and Widlar Current Source

11

V4.1ln

2

2

V7.0

21

12

1222

RS

IEE

V

RTV

OI

RRBE

V

BI

RBE

V

FEI

FOI

−≅∴

≅≅+==

αα

Output current is now logarithmically



• Output current is determined by base-emitter voltage of Q1 . For high current gain,

1

V4.1

1

211 R

EEV

RBE

VBE

VEE

V

CI

−≅

−−=

Output current is now logarithmically dependent on supply voltage. However, it is temperature dependent due to temperature coefficients of both VBE and R.

Widlar source also achieves similar supply independence of output current.

==1

2ln2

EAE

A

OIREF

I

RT

V

EIFO

I α

Chap 16-22

Supply-Independent Biasing: Bias Cell Using Widlar Source and Current Mirror

Actual value of output current depends on temperature and absolute value of R. IC1 = IC2 =0 is also a stable operating point and start-up circuits must be included in IC realizations to ensure that circuit reaches desires operating point.

Base-emitter voltages of Q1 and Q4 can be used as



Assuming high current gain, pnpcurrent mirror forces IC1 = IC2. Emitter area ratio for Widlar source is shown to be 20.

∴ IC2

=V

TR

ln 20

= 0.0749 V

R

Base-emitter voltages of Q1 and Q4 can be used as reference voltages for other current mirrors.

In MOS analog of the circuit, ID3 = ID4 and soID1 = ID2.

−=2

)/(1)/(

112

2LW

LW

nK

DI

R

Chap 16-23

Reference Current Design Example

Problem: Design supply-independent current source to meet given specifications.

Given data: output current = 45 µA,T=300 K, total current< 60 µA VCC = VEE= 5 V,VA = 75 V, βFO = 100, ISO = 0.1 fA, VT = 25.88 mV

Analysis:739.1

25.88mV

1kµA452

1

2

2

1ln =Ω

≤=

TV

RC

I

EAE

A

CIC

I



Also . Choose IC2=5 IC1. Then AE2/ AE1 <28.45 Choosing

AE2/AE1 =20,

Finally, AE1=A, AE2=20 A, AE3=A, AE4=5 A with 35.88 mV across R.

69.512

21

12

≤

EAE

A

CIC

ITEC

IC2IC1

≥ 45µA15µA

= 3

R=25.88mVln(4)45µA

1kΩ

45µA= 797Ω

Chap 16-24

Bipolar Transistor Current Source Design Example

• Problem: Design a current source with the largest possible output voltage range that meets the given output resistance specification.

• Given data:VEE = 15 V, Io = 200 µA, IEE < 250 µA, Rout > 2 MΩ, BJTs available with (βo, VA) = (80, 100 V) and (150, 75 V), VB must be as low as possible.

• Assumptions: Active region and small-signal operating conditions. VBE



• Assumptions: Active region and small-signal operating conditions. VBE

= 0.7 V, VT = 0.025 V, choose Vo = 0 V as representative output value.

Analysis:

V2000)MΩ10)(µA200(

21

1

=≥=≤=

≤++

+=

outRoIAVo

AVooutRoICS

V

oroE

RrRRE

RooroutR

ββ

βπ

β

Chap 16-25

Bipolar Transistor Current Source Design Example (contd.)

Both BJTs can satisfy these conditions. But, we choose BJT (150, 75V) with higher βoVA product.

Total current < 250 µA. As output current is 200 µA, maximum of 50 µA can be used by base bias network. Current used by base bias network must be 5 to 10 times base current of BJT (1.33 µA for BJT with a current gain of 150). So bias network



BJT with a current gain of 150). So bias network current =20 µA.

Large RBB reduces output resistance and output compliance range (increase VBB).Trading increased operating current for wider compliance range, choose bias network current of 40 µA.

Ω=≅+∴ k375A40

V1521 µRR

Chap 16-26


• Following set of equations can be used in a spreadsheet analysis to determine design variables. Primary design variable is VBB which can be used to determine other variables.

F

oIBI β

=

Ω=+= k375)( BBV

BBV

RRR 1k375

1)

21(

2RRRRR −Ω=−+=



Ω=+=15

k37515

)21

(1

BBBBRRR 1k375

1)

21(

2RRRRR −Ω=−+=

21RRBBR =

−−=

oIBB

RB

IBE

VBB

V

FER α

)(BB

RB

IBE

VBB

VEE

VCE

V −−−=

oIT

Vorβ

π =oICE

VA

Vor

+=

+++=

ERrRR

ERo

oroutR

π

β

21

1

Chap 16-27


• From spreadsheet, smallest VBB for which output resistance > 10MΩ with some safety margin is 4.5 V, resulting output resistance is 10.7MΩ.

• Analysis of circuit with 1% resistor values gives Io = 200 µA and supply current = 244 µA.

• Final current source design is as shown.



• MOSFET current source design can also be analyzed in similar manner.

Chap 16-28

CMOS Differential Amplifier with Active Load: DC Analysis

−−=−=TP

VpK

SSI

DDVSD

VDDVO

V4

DDVpK

SSI

nKSS

ITPVTNVDDV

DSV ≅−+++=

1



ID3 = ID1 = I D2 =I D4 =I SS/2.Mirror ratio is set by M3 and M4 and is exactly unity when VSD4= VSD3and thus VSD1= VSD2.Differential amplifier is completely balanced at dc when:

TPVpK

SSI

SGV

SDV

DDpKnKTPTNDDDS

−==33

1

Chap 16-29

CMOS Differential Amplifier with Active Load: Differential-Mode Signal Analysis



The differential amplifier can be represented by its Norton equivalent. Total short circuit output current:

idv

22id

v22oi m

gmg

==

Thevenin equivalent output resistance:

Differential-mode voltage gain:

42 or

or

thR =

22

42f

or

or

m2g

thRsci

dmA

µ≅==

Chap 16-30

CMOS Differential Amplifier with Active Load: Output Resistance

Drain current of M2 (vx/2ro2)is replicated by current mirror as drain current of M4. Total current from source is 2(vx/2ro2)= vx/ro2.

Total current is:

xvxviTx +=



Assume RSS>>1/ gm1.

Resistance looking into drain of M2 (C-G transistor) is:

22

1

12

12212 or

mgm

gor

SR

mg

or

o2R =+=+=

Output resistance is:

4

x

2

xiTxor

or

+=

42 or

or

odR =

Chap 16-31

CMOS Differential Amplifier with Active Load: Common-Mode Signal Analysis

From small-signal equivalent:

ssRic

voci

2≅ 2

2or

odR =

SSR

focR µ2=

ocGo

go

gm

goci

3v

+++

−=

2/233

g 1+

ro3

r

v



where it is assumed that gm4 = gm3 and Goc << gm3.

Also

isc=− ioc+gm4

v3

−go22

v3

≅−

ro2

µf 3

vic

2RSS

+

−==42

32

2

31

or

or

SSR

f

oror

icv

thRsci

cmAµ

Chap 16-32

CMOS Differential Amplifier with Active Load: CMRR and Mismatch Contribution

SSR

mg

for

or

SSR

mg

f

cmAdm

A

232

/3

1

232

CMRR µµ

≅+

==

for ro3 = ro2.

With mismatched transistors, assuming vd1=0 and gate-source voltages are equal,

With vgs= vic- vs, vd1=0 and vd2=0,svoggsvmg

di

disci ∆−∆=−=

21



With vgs= vic- vs, vd1=0 and vd2=0,

icvicv

SSRmgSS

Rmgsv ≅

+≅

21

2

icv

fSSRmgicv

SSRmgSS

Roggsv

+≅+

+≅

µ1

21

21

21

CMRR -1 =AcmA

dm

=Acm

gm ro2

ro4( )

=∆gmgm

12gmR

SS

+ 1µ

f

−∆gogo

1µ

f

Chap 16-33

Bipolar Differential Amplifier with Active Load: DC Analysis

EBVCC

VO

V −=

CCVBEVEBV

CCVEV

CV

CEV

CEV ≅−−−=−== )()(

21

Differential amplifier is completely balanced at dc when:

Current gain defect in current mirror upsets dc balance. As longs as BJTs are in forward-active region, VEC4

adjusts to make up for current-gain defect.



IC3 = IC1 = I C2 =I C4 =I EE/2.If βFO is very large, current mirror ratio is set by Q3 and Q4 and is exactly 1 when VEC4

= VEC3=VEB.

adjusts to make up for current-gain defect.

As IC2 =I C4 and IC2

=I C1, MR must be 1.

IC4

= IC1

1+ (VCE4

/VA

)( )1+

VCEV

A

+ 2β

FO4

FO4

AV

EBVEC4

V β2

+= This causes an equivalent input offset voltage of

ddA

EBV

EC4V

ddA

EC3V

EC4V

OSV

−=

−=

Chap 16-34

Bipolar Differential Amplifier with Active Load: Differential-Mode Signal Analysis

Thevenin equivalentoutput resistance:

Differential-mode voltage gain:42 o

ro

rth

R =

Adm

=isc R

LR

th( )vdm

= gm2

ro2

ro4

RL

= g

m2R

L



To eliminate offset error, buffered current mirror active load is used. Total short circuit output current:

idv

22id

v22sci

mgm

g==

dm vdm

m2 o2 o4 L m2 L

With added stages, the resistance at the output of the differential input stage is:

5542 ππ rror

oreqR ≅=

5/

25

2

CI

CIo

eqRm

gdm

A

β==

Chap 16-35

Bipolar Differential Amplifier with Active Load: Common-Mode Signal Analysis

−≅−=EERoro

f2

icv

or

mgEERoroicvsci

211

)2

2(3

12

112 βµβ

1

112

−

Rg

Current forced in differential output resistance is doubled due to current mirror action.



−==oroEERicv

CR

icvccA

oci β1

21

From small-signal equivalent:

22

1

2

1

3

2/

2CMRR

−≅=

EE

Rm

gfooic

vth

Rscith

Rm

g

µββ

−=EERoroo

icvsci2

112ββ

Due to mismatches,

∆−

+

∆+

∆=

fogog

fSSRmgg

g

mgmg

µµππ 11

211-CMRR

Chap 16-36

Active Loads in Op Amps: Voltage Gain

Adm

=vav

id

vb

va

vov

b

= Avt1

Avt2

(1)≅ Avt1

Avt2

=µ

f 2µ

f 54

If Wilson stage is used in first-stage active load, A = µ . If current source M is



25)

52(

2))

10(5(52

22)

42(

21

for

or

mg

or

GGRormg

vtA

for

or

mg

vtA

µ

µ

=≅+=

≅=

Gain of output stage is approximately 1.

load, Avt1 = µf2. If current source M10 is replaced by a Wilson or cascode source, Avt2 = µf5.Overall gain can be raised to:

52 ffdmA µµ=

Chap 16-37

Active Loads in Op Amps: DC Design Considerations

• When op amp with active load is operated in closed-loop configuration, ID5 = I2, the output current of source M10.

• For minimum offset voltage, (W/L)5 must be such that VSG5 = VSD4 = VSG3 precisely sets ID5 = I2



VSD4 = VSG3 precisely sets ID5 = I2

and accounts for VDS and λdifferences between M5 and M10.

• RGG, (W/L)6 and (W/L)7 determine quiescent current in class-AB output stage.

• VGS11 can be used to bias output stage in place of RGG.

Chap 16-38

CMOS Op Amp Analysis

Problem: Find small-signal characteristics of given CMOS op amp.

Given data: IREF = 100 µA, VDD = VSS = 5 V, VTN = 1 V, VTP = -0.75 V, Kn‘ = 25 µA/V 2, Kp‘ = 10 µA/V 2, λ = 0.0125 V-1

Analysis:

ID2

= I1

/2 = IREF

=100µA

I = I = 2I = 200µA

V54.21111

21111

=+=n

KD

ITN

VGS

V

As I = I , V = V = V /2



ID5

= I2

= 2IREF

= 200µA

000,16

5

52

5

1

2

22

2

141

452

==

=

DI

pK

DI

nK

ffdm

A

λλ

µµ

∞== icRid

R

As ID6 = ID7, VGS6 = VSG7= VGS11/2

ID7

= ID6

= 2502

µA

V 2(1.27V− 0.75V)2

= 33.7µAS4103.1

67−×==

mgmg

Ω== k85.3

7

1

6

1

mg

mgoutR

Chap 16-39

Bipolar Op Amps

• Load resistance is driven by class-AB output stage formed by Q6 and Q7 , biased by I2 and diodes Q11

and Q12.

321 vtA

vtA

vtA

dmA =



• Q1 to Q4 form differential input stage with active load.

• First stage is followed by high-gain C-E amplifier, Q5 and its current source load, Q8.

25

55

225

5555

2

)1()16

(85252

fo

CIC

Ior

mgrmg

mgm

gL

Roo

ror

mgr

mg

µβπ

βπ

=≅

+≅

Chap 16-40

Input Stage Breakdown in Bipolar Op Amps

• Input stage of bipolar op amp has no

Early IC op amps used external diode protection across input terminals to limit differential



• Input stage of bipolar op amp has no overvoltage protection and can easily be destroyed by large input voltage differences due to fault conditions or unavoidable transients, such as slew-rate limited recovery.

• In worst-case fault condition, B-E junction of Q1 is forward-biased and that of Q2 is reverse-biased by(VCC + VEE - VBE1). If VCC = VEE =22 V, reverse voltage > 41 V.

terminals to limit differential input voltage to about 1.4 V at the cost of extra components.

Chap 16-41

µA741 Op Amp

• High gain, input resistance and CMRR, low output resistance and good frequency response.

• Fully protected input and output stages and offset adjustment port.

• Input stage is a differential



• Input stage is a differential amplifier with buffered current mirror active load.

• Two stages of voltage gain (emitter-follower driving C-E amplifier) followed by short-circuit protected class-AB output stage buffered from second gain stage by emitter follower.

Chap 16-42

µA741 Op Amp: Bias Circuitry

Assuming VO =0, VCC =15 V and neglecting drop across R7 and R8 ,

VEC23= 15+1.4=16.4 V and VEC24= 15-0.7 =14.3 V

Given VA=60 V, βFO =50,

A666)60/4.16(1mA)733.0(75.02 µ=+=I



mA733.0

5

2=

−+=

RBE

VEE

VCC

V

REFI

=1

ln50001 I

REFI

TV

I

Solving iteratively,

I1 =18.4 µA.

A666)50/2()60/7.0(1

mA)733.0(75.02 µ=++

=I

A216)50/2()60/7.0(1

)60/4.14(1mA)733.0(25.03 µ=++

+=I

Ω=+=+

= k115mA666.0

16.4VV60

2

23232 I

ECV

AV

R

Ω=+=+

= k344mA216.0

14.3VV60

3

24243 I

ECV

AV

R

Chap 16-43

µA741 Op Amp:DC Analysis of Input Stage

4141

2

2222 B

IFO

FO

FOE

IFC

I

++

== ββ

βα

+−−

+×≅∴

4

1

8

2

8

881

121

2

FOFOAV

EBV

ECV

I

CI

ββ



/2IC

I161

≅−

42)

8/

8()

8/2(1

)8

/8

(1

221 BI

AV

EBV

FO

AV

ECV

CII +

++

+=

β

214

4

2

12

444 CI

FO

FO

FO

FOE

IFC

I+

+==

β

β

β

βα

CCV

BEV

EBV

CCV

CEV

CEV ≅+−== 2921

V1.2

V)4.1(--V7.0333−=

+−=−=

EEVEEV

CV

EV

ECV

V7.07

V4.18−=+=

EEVCE

VCC

VEC

V

Chap 16-44

µA741 Op Amp: Input Stage Bias Currents Example

Problem: Calculate bias currents in the 741 input stage with given parameters.

Given data: I1 = 18 µA,VCC = VEE= 15 V,VAnpn = 75 V, βFOnpn= 150, VApnp = 60 V, βFOpnp= 60

Analysis:

A32.71)60/4.16(1

12

A1821

V4.16318

µµ =++==

≅++=

CI

CI

EBV

BEV

CCV

ECV



)160)(151/150(1

)60/7.0()50/2(1)60/4.16(1221

++

+++CC

A25.735

A25.72151

1506160

214

4

2

12

2

2444436

µ

µ

β

β

β

β

ααα

=≅

==

+

+=====

CI

CI

CI

CI

FO

FO

FO

FO

F

CI

FEI

FCI

CI

CI

Chap 16 - 45

µA741 Op Amp: AC Analysis of Input Stage

Using symmetry of the input stage differential-mode half circuit can be drawn.

24

idv

4)1(

2/id

v

4)1

2(

2

2/id

v

bi

bi

2bi)1

2(

4ei4oi

ππβπβπ

ββαα

rrrin

Ro

r

oooo

≅

++

=++

=

≅+==



21

4

4)12

(2

422 πβ

πβππ

oo

rino+

++

idv

42

24

idv

2oim

g

ro=≅∴

πβ

24

biid

v

id πrR ==

42

41

4 orR

mg

oroutR =+≅

Chap 16-46

µA741 Op Amp: Voltage Gain (Input Stage Norton Equivalent)



io=−2i= -gm2

vid

2=−20I

C2vid

= (−1.46×10−4S)vid

Rth

= Rout6

Rout4

≅ ro6

1+ gm6

R2( )2r

o4

=1.3ro6

2ro4

= 0.79ro4

= 6.54 MΩ

Based on values in Norton equivalent, open-circuit voltage gain of first stage is -955.

Chap 16-47

µA741 Op Amp: Voltage Gain (Second Stage)

IC10

≅ IE10

=IC11

βF11

+V

B1150kΩ

=19 .8µA

Rin11

= rπ11+ β

o11+1

100= 20.7kΩ

y11

−1

= rπ10+ β

o10+1

50 kΩ R

in11

= 2.4M Ω

ve= v1

βo10

+1( )50kΩ Rin11( )

+ β +( ) Ω( )



C10 E10 βF11

50kΩ

rπ10 =β

o10IC10

=189 kΩ rπ11

= 5.63kΩ

To find y11 and y21:

ve= v1rπ10

+ βo10

+1( )50kΩ Rin11( )

= 0.921v1

1v006701.0100)

11/1(

ev2i =

Ω+=

mg

mS70.621

=∴ y

Chap 16-48

µA741 Op Amp: Voltage Gain (Second Stage cont.)

To find y12 and y22:

Ω=+=

k40710011

11111 ER

mg

or

outR



Open-circuit voltage gain for the first two stages is:

Ω=

=

−

k1.8911222

1

outRRy

v2

=−0.00670(89.1kΩ)v1

=−597v1

v1

=−1.46×10−4 6.54MΩ 2.4MΩ

v

id =−256v

idv2

=−597(−256vid

)=153,000vid

Combined model for first and second stages is:

Chap 16-49

µA741 Op Amp: Voltage Gain (Output Stage)



From simplified output stage without short-circuit protection:

Ω=++=

Ω=++=

Ω=++=

M27.81

1121212

k1622313141

k304115152

eqR

or

inR

eqRR

dr

dr

eqR

LRo

req

R

βπ

βπ

Req3

= R3

rd14

+ rd13

+rπ12

+ y22

−1

βo12

+1

= 2.08 kΩ

Ro =rπ15

+ Req3

βo15

+1= 26 .2Ω

Actual op amp output resistance is:Ω=+= 537RoRoutR

Chap 16-50

µA741 Op Amp Characteristics



Chap 16-51

End of Chapter 16



Chap 16-52

End of Chapter 16

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