analog vlsi

1Dr. Navakanta Bhat

E3-238 : Analog VLSI Circuits

Dr. Navakanta Bhat

Associate Professor, ECE DepartmentIndian Institute of Science, Bangalore-560012

Email: [email protected]: http://ece.iisc.ernet.in/~navakant/Navakant_Bhat.html

August 2006

Lecture # 1

2Dr. Navakanta Bhat

Logistics• Instructor : Navakanta Bhat

• Class timings : Monday, Wednesday and Friday 8:00am-9:00am

• Lab session : • Involves circuit design, simulation and analysisusing any circuit simulator (Spice3f5, WinSpice, T-Spice, P-Spice, H-Spice, Spectre, Eldo…)

• Grading : • Home work (lab assignments) : 20%• Class tests : 20 % • Course project : 20 %• Final exam : 40%

3Dr. Navakanta Bhat

List of Reference booksDue to the advent of mixed signal SOCs, numerous books have been published on Analog Design. A partial list :

1. Analog CMOS DesignRazavi, McGraw Hill Publication

2. CMOS: Circuit Design, Layout , and SimulationBoise, Baker, Lee, Prentice Hall Publication

3. Analog VLSI : Signal and Information ProcessingIsmail and Feiz, McGraw Hill Publication

4. Analysis and Design of Analog Integrated CircuitsGray and Meyer, Wiley Publication

5. Trade-offs in Analog Circuit Design: The Designer’s Companion, Ed: C. Toumazou and other, Kluwer

4Dr. Navakanta Bhat

Scope of the Course notes

“This course material has been developed to supplement the the discussions during the lectures in class. You can use thisas the principal reference material. However, this coursematerial is not a text book. You may still want to read up some of the books listed in the reference list to gain moreinsight or to get alternate explanation for a given topic.”

Your feedback is welcome in terms of any corrections or any additions to be done to the course notes to improve its utility.

Note: The emphasis in this course is to designs analog circuitson a digital CMOS technology. Some of the discussions should be viewed and appreciated with this context in mind.

URL: http://ece.iisc.ernet.in/~navakant/E3-238/2006/analog.html

5Dr. Navakanta Bhat

Course details

Small signal parameters, Cut-off frequency, Concept of poles and zeros, Miller’s approximation

Source follower, Input and output impedance, Common gate amplifier, Cascode amplifier, Folded cascode

Single stage amplifiers, Common source amplifier with resistive load, diode load, constant current load, Source degeneration

SPICE simulator, Transistor models, BSIM3 models, Model extraction, Models for : Vt, I-V, Capacitance, Substrate current, S/D parasitics, Temp dependence, NQS effect, Noise, RF Modeling, Gate leakage

Sub-micron transistor theory, SCE, NWE, DIBL, Sub-threshold conduction, Reliability, Digital metrics, Analog metrics

Logistics, Technology trend, Need for Analog design, Simple long channel MOSFET theory

6Dr. Navakanta Bhat

Course details

Gilbert cell and applications, Basic 2 stage OPAMP, 2-pole system response, active current mirror, common mode and differential gainFrequency response of OPAMP, pole splitting, zero cancellation, slew rate, PSRR, random offset, systematic offset, Noise, Output stage, OTA and OPAMP circuits

Differential Amplifier: differential and common mode response, Input swing, gain, diode load and constant current load

Bandgap voltage reference, supply and temperature independent reference, curvature compensation, trimming

Current mirrors: Cascode, Nagative feedback, Wilson, Regulated cascode, Layout issues

7Dr. Navakanta Bhat

Course details

Correcting OPAMP non idealities: Auto zeroing, Correlated double sampling, Chopper stabilization

Transistor mismatch / Variability, Statistical design Effect of mismatch on sense amplifier

Passives in CMOS: Capacitors and Varactors, Inductors, Resistor, Quality factor of passives

Data Converters : DAC and ADC

Low voltage design, Wide common mode OPAMP, Complementary input stage, Body driven input, Lateral BJTs, Subthreshold analog circuits,

Sense Amplifier, Effect of transistor mismatch in analog design, Mismatch compensation, Statistical design

Sample and Hold, Switched capacitor circuits, Comparator

8Dr. Navakanta Bhat

Why Analog ?Interaction with the Physical World

Computing Platform

Physical Environment

Physical Environment

Input Output

Sensing Actuation

Human perception is inherently analog in nature

9Dr. Navakanta Bhat

Why Analog ?An Interesting Comparison…

• Neural networks outperform the digital computers, in certain class of applications such as speech recognition, pattern recognition

• The architecture and massive parallelism are distinguishing features

Analog (Adaptive learning)Digital (RISC/CISC …)Architecture~ 1 Trillion~1 BillionIntegration2m/sec108m/secWire / Fibre

100mS1psTransistor / Neuron

Biological Neural SystemCMOS Digital Computer

10Dr. Navakanta Bhat

The First Transistor : 1947

• First transistor was point contact Ge bipolar junction transistor, whereas the VLSI today is neither based on Ge nor on BJT!

Bardeen, Brattain, Schokley @ Bell LabsThe baby is born!

• The Bell Labs team was in fact trying to make MOS transistor,but got stuck with surface states and ended up with BJT!

Analog Circuit Design predates the semiconductor transistors!


The First IC : 1958First IC demonstrated by J.S.Kilby of Texas Instruments in 1958

First IC using planar process and photolithography was demonstrated by Robert Noyce at Fairchild semiconductors

Phase shift oscillator, an analog circuit!A thin slice of germanium with

1 bipolar transistor (under the large bar of aluminum in the center),

1 capacitor,

3 resistors (the germanium functioned as its own so-called bulk resistor)

4 input/output terminals (the small vertical aluminum bars)

ground pad (the large bar on the far right), and wires of gold.

Connected together with wax

Actual size: 0.040 x 0.062 inchesBlue tinge was created by a light shown on the chip.


Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

• Field effect transistor concept proposed in 1930s by Lilienfeld

• First MOSFET fabricated in 1960 by Kahng and Atalla

oxidemetal

Silicon

p+ p+n

PMOSFET

oxidemetal

Silicon

n+ n+p

NMOSFET

• Early MOS technology was based on PMOSFETs

MOSFETS were thought to be unfriendly for Analog circuits!


CMOS (Complementary MOS) technology•Both NMOSFETs & PMOSFETs are used•No static power consumption

•Very high integration density

CMOS Inverter

IN OUT

PMOS

NMOS

•Very good isolation

•Very low cost


CMOS market share

• CMOS captures more than 90% of electronics market share


Moore’s law

“Cramming more Components onto Integrated Circuits” Gordon E. Moore, Electronics 1965, p. 114.

“VLSI: some fundamental challenges” Moore, IEEE Spectrum 1970, p.30.

“Moore’s law governs the Silicon revolution”Bandyopadhyay, Proc. of IEEE, 1998, p.78

The bold extrapolation in 1965 by Moore was a challengeto the industry to show the determination to lead a revolution

The implicit assumption behind Moore’slaw is the feature size scales continuously

Moore proved his vision, by guiding INTEL along his predicted trajectory

Moore who studied Chemistry in college is yet another example to reiterate the fact that thereare no hard barriers between different fields


Evolution from SSI to VLSI

• In the the Digital world, MOSFET completely displaced BJTdue to all the advantages offered by CMOS


CMOS Technology Today (2006)

• 65nm digital technology in volume production

• Technology scaling for future is more challenging and expensive

• State of the art fab set-up costs more than US$2 billion

• Recovering the fab cost requires a modular process technologyapproach capable of producing diverse products

• Number of transistors per chip is ~ 1 billion( DRAMs),~ 100 million (microprocessors)

What do we do with the technology capable of making millions of transistor on a tiny area in Si? :

Mixed Signal Systems On Chip (SOC)


BJT versus MOSFET speed

p

ppn-pn+

oxidemetal

Silicon

n+ n+p

Base width defined by diffusion process

Channel length defined by Photolythography process

•Historically BJT used to be faster than MOSFET

•CMOS scaling has brought MOSFET on par with BJT


Cut-off frequency, fT

•MOSFET fT has increased considerably with scaling

Cut-off frequency trend

020406080100120

0 0.2 0.4 0.6 0.8 1 1.2

Channel length

ft ft


Analog Design on Digital Technology

• Microprocessors are today’s technology drivers

• The most elegant analog designs make use of the existing digital technology

• Every modification to the baseline technology adds on to the manufacturing cost

• Design For Manufacturability (DFM)

• CMOS analog circuits are logical choice


Long channel MOSFET Theory


Transistor abstraction

schematic switch model

n+ n+

Sicross section

gate

P-well

G

D

S

B

lay out

A A’


Simple 3-D picture of MOSFET

Lg = Length of the gateWg = Width of the gate

The 2 important dimensional parameters of MOSFET under circuit designer’s control are:

n+ gate

Oxiden+ source n+ drain

p substrate

Lg

Wg

Tox

xj

Doping concentration = Na


Simple MOS TheoryVgs < Vt, MOSFET is in cut off region

Vgs > Vt, Vds < Vgs-Vt, MOSFET is in linear region

Vgs > Vt, Vds > Vgs-Vt, MOSFET is in saturation region

where µ is mobility, εox is permittivity of the oxide, and Vt is the threshold voltage of the MOSFET

( )2

2VtVgsLTW

Idsox

ox −=µε

( )

−−=

2

2VdsVdsVtVgsLTW

Idsox

oxµε

Ids = 0

ox

basoxbfbt

qNTVV

εφε

φ4

2 ++=


I-V characteristics

Ids

Vds

Vg1

Vg2

Vg3

•Ids is constant and independent of Vds in saturationVgs

Ids

LinearVds~0.1V

SaturationVds=Vdd

Output Characteristics Transfer Characteristics

•Ids is zero in sub-threshold regionBoth of these idealities are incorrect especially for the sub-micron MOS transistor


Channel length modulation

p-substrate

n+ drainn+ source

Vg > Vt Vd > Vg - Vt

electron channel

∆L

Effective channel length is Leff = L - ∆L, where ∆L=f(Vds)

Ids increases slightly in saturation region with increasing Vds

( )2

2VtVgsLTW

Ieffox

oxds

−=µε

This limits the AC output resistance for analog applications

Vds

Ids

Vds=Vgs-Vt

ds

dsout I

VR∆∆

=

( ) ( )dsox

oxds VVtVgs

LTW

I λµε

+−

= 12

2

λ is channel length modulation parameter in SPICE


Body effect

• Vt increases due to body effect

γ = body effect factor (γ = 0.3-0.7)

Vsn+

Vbs

Vg

n+

Vd

ox

basoxbfbt

qNTVV

εφε

φ4

20 ++=

( )bbbstt VVV φφγ 220 −++=

ox

asox NqTεε

γ2

=

• This results in a transconductance term

p-substrate


Summary• Analog design is indispensable in a variety of applicationsinvolving interaction with the physical world

• The semiconductor technology is dominated by Si CMOS

• The system performance continues to increase as predicted by Moore

• Analog circuit designer should choose W & L of the MOSFET depending on the application requirement

• Channel length modulation impacts the output resistance : Out put resistance can be increased by choosing large L

• Body effect gives rise to a trans-conductance term

analog vlsi

Documents

analog design

body effect

diode load

navakanta bhat

large bar

qn ab

moores law

vgs vt