analysis and comparison of full adder block in 180 nm technology

8/2/2019 Analysis and Comparison of Full Adder Block in 180 Nm Technology

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Analysis and comparison of Full Adder Block in 180 nm Technology

INTRODUCTION: In this work main goal was to design and implement one of the most

popular adder circuit (one bit full adder) known as MIRROR ADDER and compare itsperformance with an adder designed in complementary cmos logic.

SIMPLE CMOS FULL ADDER: One way to implement full adder is to take the logic equationand translate them directly into complement cmos circuitry. Some logic manipulation was done

to reduce the transistor count. It is advantageous to share some logic between the carry and sum

generation sub-circuits until this does not slow down the carry generation process, which is the

most critical path in adder circuit.

Following is our reduced logic expressions

=AB+BCin+ACin

And

S= ABCin+(A+B+Cin)

Figure: Implemented full adder circuit in CMOS logic


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Some observation about the circuit:

1.The pmos transistor stacks are present in both sum and

carry generation circuits.

2.The intrinsic load capacitance of the carry_out signal is

large and it consist of two diffusion and 6 gate capacitances plus the wiring capacitance.So thesignal propagation delay is not optimum for this adder circuit.

MIRROR ADDER:An improved adder circuit also called the MIRROR ADDER will be

analyzed now

A B Cin S Co Carry Status

0 0 0 0 0 Delete

0 0 1 1 0 Delete

0 1 0 1 0 Propagate0 1 1 0 1 Propagate

1 0 0 1 0 Propagate

1 0 1 0 1 Propagate

1 1 0 0 1 Generate/propagate

1 1 1 1 1 Generate/propagate

Figure: TRUTH TABLE OF FULL ADDER

Circuit has been designed by realizing the fact that SUM(S) and Cout are functions of some

intermediate signals known as

1. GENERATE (G)2. PROPAGATE (P)3. DELETE (D)

The logic expression for the above three signals are as bellows

G=ABD=P=A XOR B

Now using these above three intermediate signals SUM and Cout expression can be written as

(G,P)=G+PCin

S(G,P)=P XOR Cin.


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Figure: FULL MIRROR ADDER

Some observation about this circuit:

1. The transistors connected to the Cin are placed closestto the output.

2. Only the transistors in carry stage have to beoptimized for speed. All the transistors in the sum side

can be of minimum size. So effective load capacitanceof the carry stage can be reduced to some extent.

Delay and power consumption calculation of the above two circuits:

Name of the

architecture.

Dynamic power

consumption(after

layout)(w)

Static power

consumption(after

layout)(pw)

Worst case delay(ps)

CMOS Full Adder 4.6 53.45 1. 187 (between Cin

and Cout).

2. 280 (between Cin

and SUM).

MIRROR Full Addder 4.64 55.152 1. 174 (between Cinand Cout).

2. 230 (between Cin

and SUM)


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Conclusions: 1.Both circuits performed well in this 180 nm technology.

2.Supply voltage was 1.8 volt.

3. All the transistor has been sized considering two things mainly

i).Inversion threshold will be .9 volt

ii). Longest path delay of circuit should be minimum.

4. Experimental result shows that delay performance of the MIRROR ADDERis better while consuming the same amount of power as CMOS adder.

analysis and comparison of full adder block in 180 nm technology

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