“brings visibility for software and hardware engineers into … · 2014. 5. 13. · •software...
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“Brings Visibility for Software and Hardware Engineers into registers, software and embedded instruments”
© 2013, ASSET InterTech, Inc.
ASSET Confidential
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July 2013
© 2013, ASSET InterTech, Inc.
ASSET Confidential 2
“More Visibility…
That’s exciting!”
ASSET & Arium
Merge
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Technology and Challenges
Trends
Cores and software embedded in-
system growing exponentially
SerDes I/O above 5 Gb/s plus fast
memory growing
Packaging technology more
integrated with less I/O access
© 2013, ASSET InterTech, Inc.
ASSET Confidential 3
Challenge
Software debug of in-house code, SoC vendor code and other software (OS, drivers, etc.) plus revision mgmt a big challenge
Signal integrity validation can no longer be done via probes, test points add capacitance, external instruments DON’T see what silicon sees
Packaging technology removing access for design validation and structural test in production
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Market Trends to Address Challenges
© 2013, ASSET InterTech, Inc.
ASSET Confidential 4
“Software Solutions to SW/HW Problems”
Transition of external hardware to chip IP + software
“Market Trends in Instrumentation”
Boxes/Knobs to Modules/Software to IP/Software
• µP emulation
• Structural & Functional
Test for printed circuit brds
• Instrumentation for
Validation
• Structural & Functional
Test & Debug for ICs
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Value to Customers
More visibility into your system for quicker debug of both hardware and software issues
By joining forces, we totally align with the Intel strategies of Intel® Silicon View Technology and “Shift Left” product development acceleration that is unique to only ASSET
Investing in new ARM technologies like 64-bit ARM and System Trace Module
Accelerating the development-to-production process via our ScanWorks platform for embedded instruments
One environment
Life-cycle re-use
Embedded solutions
© 2013, ASSET InterTech, Inc.
ASSET Confidential 5
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ASSET/Arium: 85+ people to serve YOU!
© 2013, ASSET InterTech, Inc.
ASSET Confidential 6
ASSET InterTech HQ - Dallas , TX Arium Development – Irvine, CA
US Field Offices: CA, MN, MA, GA, NC
ASSET Europe HQ – Ireland
Europe Field Offices: Gavle, Sweden; Stoke, UK ASSET APAC HQ – Taipei, Taiwan APAC Field Offices: Shanghai, China; Malaysia
International Distributors – Sweden, Turkey, Israel, and Japan
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Arium adds SDT to ScanWorks® Platform
© 2013, ASSET InterTech, Inc.
ASSET Confidential 7
Arium – ScanWorks Software Debug and Trace Tools
Validation
Test
Debug
Application One Environment
• Multiple technologies
• Multiple applications
• Software & Hardware
Visibility via
• Access standards
• Validation/Test IP
• Debug ports/architectures
Software
• Worldwide licensing
• 24/7 availability
Automation
• Mouse-click development
• Robust Software Debug
• Product life-cycle reuse
Benefits
“Brings Visibility for Software and
Hardware Engineers
into registers, software and
embedded instruments”
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© 2013, ASSET InterTech, Inc.
ASSET Confidential 8
BST Boundary-
Scan Test
Verify
interconnects and
provide access
to ICs on
a board
PCT Processor-
Controlled Test
Control the
µProcessor to
enable functional
at-speed test and
debug a board
FCT FPGA-
Controlled Test
Insert temporary
test IP blocks into
on-board FPGAs
to test board
functions
IJTAG Internal
JTAG Test
Control embedded
instruments with
the standard IJTAG
interface on SoCs
and ASICs
HSIO High-Speed
I/O Validation
Validate high-
speed serdes
links between ICs
and chipsets
e.g. Intel®
SDT Software
Debug and Trace
Debug embedded
software and trace
tools for Intel® and
ARM®
µprocessors
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Arium Software Debug & Trace Standalone
© 2013, ASSET InterTech, Inc.
ASSET Confidential 9
SourcePoint is Arium’s Premier Source Level Debugger
SourcePoint interfaces with Arium run-control products which may support Intel, ARM or both!
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ScanWorks® FPGA-Controlled Test
The FPGA-Controlled Test tools allow the tester to be inserted into an FPGA that's already part of your board design to validate, test and debug your board.
© 2014, ASSET InterTech, Inc., Confidential
10 © 2013, ASSET InterTech, Inc. ASSET Confidential
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Value of FPGA-Controlled Test
Increases Board Test Functional Coverage
Reusable IP library
Test Time Reduction with at-speed IP
Leverage on-board FPGA (or off board…)
Automated Instrument Insertion
Automated Drag and Drop Development
Parallel Testing of Interfaces
© 2013, ASSET InterTech, Inc. ASSET Confidential
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Standard* IP Library in ScanWorks
IP Examples
Clock and Frequency test
SPI, I2C, UART Masters
SPI Flash Programming
NOR, NAND at customer request
Standard PatGen and CaptBuff
Memory Test
* IP Customization for customer application may be necessary.
© 2013, ASSET InterTech, Inc. ASSET Confidential
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ASSET IP Library
The ASSET IP Library is reusable
IP can be reused in supported FPGAs
IP functions can be reused against the same functions
IP Masters (SPI, I2C, etc) are reusable (see example)
Application specific IP is reusable on supported
FPGAs against the same endpoint function/device
IP specific IEEE1687 PDL and ICL is reusable
© 2013, ASSET InterTech, Inc. ASSET Confidential
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The FPGA is an Embedded Tester
© 2013, ASSET InterTech, Inc. ASSET Confidential
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Embedded Tester for Board Test
FPGA IP Library for board test
Standard Interfaces
IEEE 1149.1 (JTAG)
IEEE P1687 (IJTAG)
For common FPGAs
© 2013, ASSET InterTech, Inc. ASSET Confidential
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FCT SPI Flash IP
Program the SPI Flash from the FPGA
16
JTAG
© 2013, ASSET InterTech, Inc. ASSET Confidential
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FCT SPI Flash IP
At-speed SPI Flash Programming
SPI IP instantiated in FPGA
SPI data streamed over the TAP port and
programmed as fast as the SPI device can take it.
17 © 2013, ASSET InterTech, Inc. ASSET Confidential
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FCT SPI Flash IP
Example:
M25P16 - 16Mb
Configure time: 7 seconds
(With BST ~ 30 mins)
18
JTAG
© 2013, ASSET InterTech, Inc. ASSET Confidential
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FCT Flash IP Customer Example
Example: Reduced Scan Chain IP
Xilinx Spartan 6 FPGA
Targeted Freescale K20/60 SOC - 1Mb
EZ Port programming interface (SPI Like)
Configure time: 11 seconds
(With BST ~ 10 mins)
19
JTAG
© 2013, ASSET InterTech, Inc. ASSET Confidential
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FCT ROI Examples
Reduced need for multiple
Programming Stations
Increased line throughput
No need for off line device
programming
Easy configuration management
Use at ICT or Functional Test
20
JTAG
© 2013, ASSET InterTech, Inc. ASSET Confidential
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ASSET InterTech Medalist ICT Solutions
External Application can run all
ScanWorks test action types
Can use ICT PC or Standalone PC
Any ScanWorks Hardware
PCI410, PCI200ej
PCIe1000, PCIe410
Ethernet RIC1000, RIC4000
© 2013, ASSET InterTech, Inc. ASSET Confidential
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Externally and Internally Integrated Medalist
ICT Solutions – ASSET ScanWorks®
Ethernet
linked PC
with
ScanWorks
ScanWorks®
Card
UNIX or PC
Controller
ScanWorks® Pod connects to UUTs
•For Medalist family
with UNIX or PC
controllers
•PC-based ScanWorks
Manufacturing Station
•ScanWorks tests
applied under control
of Agilent Test Plan
•Simple API calls
added to ICT test
program Easy to setup and use. Ready for high-volume test. © 2013, ASSET InterTech, Inc.
ASSET Confidential
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+ = …
© 2013, ASSET InterTech, Inc.
ASSET Confidential 23
Arium is now part of the ScanWorks platform to address hardware and software integration challenges
Arium continues as a standalone product for the firmware/software engineer that needs best-in-class software debug and trace for Intel & ARM
Delivering design, manufacturing and field service solutions globally for chips, boards and systems
Customer is supported by experts in enabling customers adoption of new DFx technologies to address many issues - multi-processors, dense packaging, IO speeds over 5 Gb/s, SoCs, FPGAs, and more
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ASSET Confidential 24
“Brings Visibility for Software and Hardware Engineers into registers, software and embedded instruments”