KONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY, THOTTIAM.

AP 7102 ADVANCED DIGITAL LOGIC SYSTEM DESIGN L T P C3 0 0 3OBJECTIVES: To analyze synchronous and asynchronous sequential circuits To realize and design hazard free circuits To familiarize the practical issues of sequential circuit design To gain knowledge about different fault diagnosis and testing methods To estimate the performance of digital systems To know about timing analysis of memory and PLDUNIT I SEQUENTIAL CIRCUIT DESIGN 9Analysis of Clocked Synchronous Sequential Networks (CSSN) - Modeling of CSSN State Assignment and Reduction Design of CSSN Design of Iterative Circuits ASM Chart ASM Realization, Design of Arithmetic circuits for Fast adder- Array Multiplier.UNIT II ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 9Analysis of Asynchronous Sequential Circuit (ASC) Flow Table Reduction Races in ASC State Assignment Problem and the Transition Table Design of ASC Static and Dynamic Hazards Essential Hazards Design of Hazard free circuits - Data Synchronizers Designing Vending Machine Controller Mixed Operating Mode Asynchronous Circuits. Practical issues such as clock skew, synchronous and asynchronous inputs and switch bouncing.

UNIT III FAULT DIAGNOSIS & TESTING 9Fault diagnosis: Fault Table Method Path Sensitization Method Boolean Difference Method Kohavi Algorithm Tolerance Techniques The Compact Algorithm. Design for testability: Test Generation Masking Cycle DFT Schemes. Circuit testing fault model, specific and random faults, testing of sequential circuits, Built in Self Test, Built in Logic Block observer (BILBO), signature analysis.

UNIT IV PERFORMANCE ESTIMATION 9Estimating digital system reliability, transmission lines, reflections and terminations, system integrity, network issues for digital systems, formal verifications of digital system: model-checking, binary decision, theorem proving, circuit equivalence.

UNIT V TIMING ANALYSIS 9ROM timings, Static RAM timing, Synchronous Static RAM and its timing, Dynamic RAM timing, Complex Programmable Logic Devices, Logic Analyzer Basic Architecture, Internal structure, Data display, Setup and Control, Clocking and Sampling.

TOTAL: 45 PERIODSREFERENCES:1. Charles H.Roth Jr Fundamentals of Logic Design, Thomson Learning 2004.2. Nripendra N Biswas Logic Design Theory Prentice Hall of India, 2001.3. Parag K.Lala An introduction to Logic Circuit Testing Morgan and claypool publishers, 2009.4. Stephen D Brown, Fundamentals of digital logic, TMH publication, 2007.5. Balabanian, Digital Logic Design Principles, Wiley publication, 2007.6. Stalling, Computer Organization & Architecture, Pearson Education India, 2008.7. J.F.Wakerly, Digital Design, Pearson Education India, 2012.8. J.F.Wakerly, Digital Design principles and practices, PHI publications, 2005.9. Charles J. Sipil, Microcomputer Handbook McCrindle- Collins Publications 1977.

UNIT ISEQUENTIAL CIRCUIT DESIGN 9

Analysis of Clocked Synchronous Sequential Networks (CSSN) - Modeling of CSSN- State Assignment and Reduction- Design of CSSN- Design of iterative circuits-ASM chart- ASM Realization, Design of arithmetic Circuits for Fast adder-Array Multiplier.Session No.Topics to be coveredTimeRefTeaching Method

1. Analysis of Clocked Synchronous Sequential Networks- Introduction.50m1BB

2. Design of a Sequential parity checker, Analysis of Moore and Mealy sequential circuit by signal tracing and timing charts.50m1BB

3. Method of constructing state table and state graphs for Moore and Mealy machines.50m1BB

4. General Models for a clocked Mealy and Moore sequential circuits. 50m1BB

5. Guidelines for state assignments and reduction of state table using state assignment.50m1BB

6. Different types of State Assignment- Shared row, Multiple row and One hot state assignment.50m1BB

7. Determination of state equivalence and circuit equivalence using an implication table.50m1BB

8. Design of iterative circuits, Design of a n-bit comparator.50m1BB

9. Algorithmic State Machine (ASM) Charts- Derivation and realization of ASM Chart.50m1BB

10. Design of Arithmetic circuits for Fast adder- Carry look ahead adder.50m4BB

11. Array Multiplier Structure of an 4 X 4 Multiplier circuit.50m4BB

UNIT IIASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 9

Analysis of Asynchronous Sequential Circuit (ASC) - Flow Table Reduction-Races in ASC- State Assignment Problem and the Transition Table- Design of ASC-Static and Dynamic Hazards- Essential Hazards- Design of Hazard free circuits- Data Synchronizers- Designing Vending Machine Controller- Mixed Operating Mode Asynchronous Circuits. Practical issues such as clock skew, synchronous and asynchronous inputs and switch bouncing.Session No.Topics to be coveredTimeRefTeaching Method

12.Analysis of Asynchronous Sequential Circuit - Design of Fundamental mode sequential circuit - Primitive state table, state table reduction and state assignment.50m4BB

13.Design of Pulse mode sequential circuit- Primitive state table, state table reduction and state assignment.50m4BB

14.Problems in Asynchronous Sequential Circuits Cycles, Critical race and Non- Critical race.50m2,5BB

15.Hazards- Static, Dynamic and Essential Hazards.50m2,5BB

16.Design of Hazard free switching circuits- Static Hazard and Essential Hazard elimination.50m2,5BB

17.Working principle of Data synchronizer.50m7BB

18.Design of Vending machine controller- Description/ Specification, FSM design steps, State diagram and state table.50m4BB

19.Design of mixed operating mode asynchronous circuit. 50m4BB

20.Practical issues: Clock skew, synchronous and asynchronous inputs and switch bouncing.50m7BB

UNIT IIIFAULT DIAGNOSIS & TESTING 9

Fault diagnosis: Fault Table Method- Path Sensitization Method- Boolean Difference Method- Kohavi Algorithm -Tolerance Techniques- The Compact Algorithm. Design for testability: Test Generation- Masking Cycle - DFT schemes. Circuit testing fault model, specific and random faults, testing of sequential circuits, Built in self test, Built in Logic Block observer (BILBO), Signature analysis.

Session No.Topics to be coveredTimeRefTeaching Method

21.Fault Models- Stuck-at fault, Bridging fault, stuck-open fault and Temporary faults.50m3BB

22.Fault Diagnosis of Digital systems- Test generation for combinational logic circuits- Fault Table Method and Path Sensitization method.50m2BB

23.Boolean Difference method.50m3BB

24.Kohavi and Compact Algorithm.50m2BB

25.Tolerance techniques- Static redundancy, Dynamic redundancy and Hybrid redundancy.50m3BB

26.Self- purging redundancy, Sift-out modular redundancy50m3BB

27.Fault in PLAs, Test generation and Masking cycle.50m2BB

28.Design for Testability (DFT), DFT schemes, Circuit testing fault model: Specific and random faults. 50m4BB

29.Testing of sequential circuits and Built In Self Test (BIST).50m4BB

30.Built In Logic Block Observer (BILBO) and Signature analysis.50m4BB

UNIT IV PERFORMANCE ESTIMATION 9

Estimating digital system reliability, transmission lines, reflections and terminations, system integrity, network issues for digital systems, formal verifications of digital system: model- checking, binary decision diagram, theorem proving, circuit equivalence.Session No.Topics to be coveredTimeRefTeaching Method

31.Estimating Digital System Reliability- Failure rates, Reliability and MTBF, System Reliability. 50m9BB

32.Transmission lines with infinite and finite length terminated with characteristic impedance, Logic signal terminations. 50m9BB

33.Network issues for digital systems: Noise, Time margin, Parasitic inductance and capacitances.50m9BB

34.Digital System Integrity to minimize Noise Margin, Transmission Line effects, Signal Path Return currents and power distribution.50m9BB

35.Design and Verification of Digital Systems: Design flow and RTL Verification.50m9BB

36.Binary Decision Diagrams with an example.50m9BB

37.Model for Design Verification, Functional Validation.50m9BB

38.Formal Verification and Challenges in Symbolic Simulation. 50m9BB

UNIT VTIMING ANALYSIS 9ROM timings, Static RAM timing, Synchronous Static RAM and its timing. Dynamic RAM timing, Complex Programmable Logic devices, Logic Analyzer Basic Architecture, Internal Structure, Data display, Setup and Control, Clocking and Sampling. Session No.Topics to be coveredTimeRefTeaching Method

39. Read Only Memory (ROM) Timing diagram. 50m7BB

40.Static RAM Internal Structure and Timing parameters for Read and Write operation of static RAM.50m7BB

41.Synchronous SRAM- Internal Structure and its read and Write operation.50m7BB

42.Dynamic RAM Structure, Write and burst read cycle Timing.50m7BB

43,44Complex Programmable Logic Devices general architecture, Function block architecture, Input/output block architecture and Switch Matrix.100m7BB

45.Logic Analyzer- Basic Architecture and Internal Structure.50m6BB

46.Logic Analyzer- Clocking, Triggering, Acquisition and Capturing Glitches.50m6BB

47.Logic Analyzer- Data display, Setup and Control50m 6 BB