adsd fall2015 01 designspaceexploration designmthodologies
DESCRIPTION
VLSI Signal Processing Systems, ParhiTRANSCRIPT
Dr. Rehan Hafiz <[email protected]>Lecture # 01
Course Information
Couse Websitehttp://lms.nust.edu.pk/
Lectures: Monday (1700-1750), Wednesday (1800-1950)Contact: By appointment/Email, or 1700-1900 hrs MondayOffice: A116- Faculty Block, SEECS, Building
Acknowledgement: Material from the following sources has been consulted/used in these
slides:
1. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan
2. [SAM] Samir Palnitkar, “Verilog HDL”, Prentice Hall, ISBN: 0130449113. , Latest Edition
3. [STV] Advanced FPGA Design, Steve Kilts
4. [PAR] VLSI Signal Processing Systems, Parhi
Material/Slides from these slides CAN be used with following citing reference:
Dr. Rehan Hafiz: Advanced Digital System Design 2015
Creative Commons Attribution--ShareAlike 3.0 Unported License.
Today’s Lecture
Introduction
What are Digital Systems ?
What shall you learn in this course ?
Where you can apply the learned knowledge?
Will this course open any new job horizon for you ?
Introduction - Mine4
Area
PhD in Reconfigurable System Design for Optical Tomography form The University of Manchester (2008)
Digital System Design for complex algorithms
Digital Image Processing, Video Registration, Immersive Displays
Activities
Group Director : VISpro Vision Imaging & Signal Processing Research Group
Head: Digital Systems & Signal Processing Knowledge Group (Summer 2009-2011)
Projects
Ultra High Definition Panorama Generation & Rendering (with ETRI Korea)
Digital Image Calibration for Multi Projector Displays (with Epic Technologies)
A Multi View Imaging (MVI) Processing Platform: FPGA based Real Time Panoramic Mosaic Generation (Funded by ICT R&D Fund)
Have been part of the project “Design and Verification of Low-Power, High-Speed IP Suite for Universal Serial Bus (USB 3.0)” with Dr. Nazar (Funded by ICT R&D Fund)
[http://vispro.seecs.nust.edu.pk/]
5
Vision System Design
Image Processing
Digital System Design
Low Level Computer
Vision
VISpro Vision Image & Signal Processing LabSEECS-NUST
In 2009 founded the
LL L C RRR
Stitching SystemGeometric Warping | Color Correction | Blending
Rendering SystemAutomatic Geometric Alignment | Projector Color Matching | Warping
Demonstration of the developed system
Ultra High Definition (UHD)Panorama Generation &
Rendering System
VISproVision Image & Signal
Processing Lab, SEECSSouth Korea
A system capable of performing Ultra High Definition (UHD) panoramic stitching & multi-
projection rendering.
Applications• Planetarium Displays• Tele-Broadcasting• Dome Displays for Museums• Wide Display Screens for Control
Rooms
Technical Outcomes• 1 International Patent Accepted• 7 International Patents Pending• 5 Journal Papers• 1 Conference Paper
Stitched Panoramic Frame
Similar Ladybug System that is being used for Google Street View
VISproVision Image & Signal
Processing Lab, SEECS
A hardware based standalone system for panorama generation
Applications• Video & Geological Surveillance• Armed Personal Vehicles (APVs)• Surveys
Innovation & Commercialization• 2 Journals + 1 Conference• Developed IP for real time
Stitching
Real Time Panorama Generation System
National ICT R&D Fund
Ministry of IT
Epic Technologies, Pakistan
• Developed a Verilog IP for Panoramic Stitching• Verilog IP evaluated on a standalone FPGA board
COPRO VISION – (JOINT MS THESIS)
8
Vision System Design
Image Processing
Digital System Design
Low Level Computer
Vision
VISpro Vision Image & Signal Processing LabSEECS-NUST
Chair of Embedded SystemsKarlsruhe Institute of Technology, Germany
Designing of Approximate Circuits for Image Processing & Computer Vision
Co-processor designing for image and computer vision algorithms
9
1. M. Shafique, W. Ahmad, R. Hafiz, Jörg Henkel, A low latency Generic Accuracy Configurable Adder in ACM/EDAC/IEEE 52nd Design Automation Conference (DAC), San Francisco, CA, USA, June 8-12, (2015)
2. M. Ahmad, A. Kamboh & R. Hafiz, "Power & Throughput Optimized Lifting Architecture for Wavelet Packet Transform", IEEE International Symposium on Circuits and Systems ISCAS 2014 (June 2014, Melbourne)
3. R. Bilal, R. Hafiz, M. Shafique, S. Shoaib, A. Munawar, and Jorg Henkel. "ISOMER: Integrated selection, partitioning, and placement methodology for reconfigurable architectures." In Computer-Aided Design (ICCAD), 2013 IEEE/ACM International Conference on, pp. 755-762.
Published in Top 3 conferences in the area of Hardware & Architecture in 2013, 2014 & 2015
*Only paper from a Pakistani university in DAC 2015
Need for Approximate Computing
• “Minimum Computational Effort” for“Acceptable Computational Goal”
𝐴 =1000
10𝐵 =
1000
916
( A > 1 ) ? ( B > 1.102 ) ?
Both Computations Require Same Computational Effort?
Gave an invited talk on “Approximate Computing ” in University of Malaya, Malaysia in March 2015
11A low latency Generic Accuracy Configurable Adder, DAC 2015
Start looking through various
SEECS Research Group NOW
What are Digital Systems ?
A digital system[1] is a data technology that uses discrete (discontinuous) values – No Analogue
^ Tocci, R. 2006. Digital Systems: Principles and Applications (10th Edition). Prentice Hall. ISBN 0-13-172579-3
http://www.youwall.com/index.php?ver=NDAwNg==
Digital Life Starts from ADC…or is inherently Digital
So what --- What’s the use ?
Where can I apply the learned
knowledge?
Can I see “Digital System Design” in
action ?
Digital Systems….
Wherever – you have discrete values to process… Micro-Processors….. Core i5, Core i7 Digital Signal Processing
Audio Processing – MP3 Players, Equalizers Image Processing – Cameras, Loads of Processing Sensing --- Medical Equipment Video Processing – Display Technologies, UHD
Resolution, Disparity Tracking….. Simple example : Face Focusing
Communication – Mobile Phones, Smartphones…
Endless List
[SHO]
What shall I learn in this course ?
The Course…20
After successful completion of this course the students shall be
able to port complex algorithms to hardware by designing efficient
data-paths and controllers; handle cross clock domain issues and
shall have the desired knowledge to optimize design for meeting
design specifications (speed, area, timings)
The related relevant courses in your stream are:
ASIC Design Methodology
Advanced VLSI System Design
The course has NO associated LAB credit hours. However, interested
students can contact me.
Course Outline
Week Topic Description/ Lecture Breakdown
1 Introduction Outline & Introduction
Initial Assessment of students
Digital design methodology & design flow
2 Verilog+
Combinational Logic
Combinational Logic Review + Verilog Introduction
Combinational Building Blocks in Verilog
3 Verilog + Sequential
Logic
Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS)
Sequential Logic in Verilog
4 Synthesis in Verilog Synthesis of Blocking/Non-Blocking Statements
5 Micro-Architecture
Controllers
Design Partitioning + RISC Microprocessor
Micro-programmed & State machine based controllers. A case study of
object tracking
6 Optimizing Speed Architecting Speed in Digital System Design: [Throughput, Latency,
Timing]
7 Optimizing Area Architecting Area in Digital System Design: [Area Optimization]
8 FIR Implementation FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs
Course Outline
Week Topic Description/ Lecture Breakdown
10 Cross Clock Domain (CDC)
Issues
Cross-Clock Domain Issues & RESET circuits
11 Fixed-Point Arithmetic &
Addition
Q-Format Arithmetic, Fast Adders, Multi-Operand Addition
12 Multipliers Multiplication , Multiplication by Constants + BOOTH Multipliers
13 Approximate Computing Approximate Arithmetic Units : Adders, Multipliers
13 CORDIC CORDIC (sine, cosine, magnitude, division, etc)
CORDIC implementation in HW
14 Algorithmic Transformations
for Recursive DFGs
15 High Level Design, HW-SW Co-Design
Paper Reading
16 Algorithmic Transformations
for Recursive DFGs
DFG representation of DSP Algorithms, Iteration Bound, Retiming
, Unfolding, Look ahead transformations
17 Project Project Presentations
1 Introduction: Course Overview, Design Space Exploration, Digital design methodology
2 Understanding FPGAs, (Xilinx FPGA Architecture) Verilog Introduction : Combinational
Building Blocks in Verilog
3 Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS)
4 Synthesis of Blocking/Non-Blocking Statements
Design Partitioning & Micro Architectures
5 Micro-Coded Controllers TERM PROJECT-START
7 Understanding Throughput, Latency &Timing & Architecting Speed/Area
8 Representation of Non Recursive DFGs & Optimizations for Non Recursive DFGs
9 FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs
10 Cross-Clock Domain Issues & RESET circuits
11 Arithmetic Operations, Adders & Fast Adders, Multi-Operand Addition
13 Multiplication , Multiplication by Constants + BOOTH Multipliers
14 Approximate Computing
15 CORDIC (sine, cosine, magnitude, division, etc) & HW- TERM PROJECT-END
16 Hardware Software Co-Design, The selection, partitioning & placement problem
17 Selected Topics, DFG representation of Recursive DSP Algorithms, Iteration Bound &
Optimization
With Much Respect & Gratitude to Dr. Shoab Ahmed Khan
Relevant Books
(Sho) Digital Design of Signal Processing Systems, Shoab A Khan
(Stv) Advanced FPGA Design, Steve Kilts
(Par) VLSI Signal Processing Systems, Parhi
25
Reference/Related Books
(Sam) Verilog HDL, Samir Palnitkar
(Cil) Advanced Digital Design with the Verilog HDL, M D. Ciletti
Synthesis of Arithmetic Circuits
26
Distribution
Quizzes 10%
Assignment 10%
Research Project 15%
OHT1 15%
OHT2 15%
Final 35%
27
*There can be slight modifications & shall be notified earlier
Relevant Conferences28
IEEE/ACM ICCAD
FPL (International Conference on Field- Programmable Logic and Applications)
FPL – FPGA (http://www.fpl.uni-kl.de/fpl/)
ES Week : International Conference on Hardware - Software Codesign and System Synthesis
DATE - Design, Automation, and Test in Europe
IEEE Symposium on Computer Arithmetic – ISCA
Applied Reconfigurable Computing – ARC
Engineering of Reconfigurable Systems and Algorithms – ERSA
Design Automation Conference – DAC
International Symposium on High-Performance Computer Architecture - HPCA
Relevant Journals29
IEEE Transactions on Circuits and Systems for Video Technology – TCSV
IEEE Transactions on Very Large Scale Integration Systems – VLSI
ACM Transactions on Architecture and Code Optimization – TACO
Journal of Systems Architecture - Elsevier Microprocessors and Microsystems – Elsevier Journal of Signal Processing Systems - Springer AIP – Review Scientific Instruments ACM Transactions on Design Automation of Electronic
Systems (TODAES)
An Excellent Verilog Tutorial30
Verilog Tutorial http://www.asic-world.com/verilog/veritut.html
Writing Technical Paper http://www1.cs.columbia.edu/~hgs/etc/writing-style.html
Class Ethics31
Class Ethics &.. Other stuff
Attendance Respect for all & classroom discipline Quizzes
Anytime
“Never cheat” Better fail NOW or else will fail sometime LATER in life
Hard work “always” pays…. Assignments
References (IEEE Indexing [1],[2],…)
Plagiarism No copying
32
PLAGIARISM
Adapted from What is Plagiarism PowerPointhttp://mciu.org/~spjvweb/plagiarism.ppt33
34
“…Oh ! I forgot to
replace-all the variable names..”
… or even more
… hum nay mil ker kaam kia tha
Questions….
Please do fill in the GOOGLE Survey form that I shall be sharing with you !
AssessmentStatus quo – Where we stand?
37
What’s the difference between
software & hardware ?
H/W vs. S/W
What do you mean when you say your design is S/W or H/W based?
S/W is where we have instructions. Executed on programmable H/W unit
H/W is where we have a dedicated data-pathdefined
Example- Add 8 numbers
Result myfunc (a,b,c,d,e,f,g,h)
int a,b,c,d,e,f,r1,r2,r3,r4,rr1,rr2
//a-h get values from somewhere
r1= a+b;
r2 = c+d;
r3 = e+f;
r4 = g+h
rr1 = r1+r2
rr2= r3 + r4;
Result = rr1 + rr2;
my_verilog_module (inputs: a,b,c,d,e,f,g,hOutputs: Result)
wire a,b,c,d,e,f,r1,r2,r3,r4,r5
----------
r1= a+b;
r2 = c+d;
r3 = e+f;
r4 = g+h
rr1 = r1+r2
rr2= r3 + r4;
Result = rr1 + rr2
C Code Verilog Code
Ignore syntax in this slide !!
What happens actually
Gets sequentially executed on a processor
A datapath is created
& its parallel & this is where H/W benefit comes
C Code Verilog Code
Controller
Instructions Queuer1= a+b;r2 = c+d;r3 = e+f;r4 = g+hrr1 = r1+r2rr2= r3 + r4;Result = rr1 + rr2;
ALU
Memory
a,b c,d e,f g,h
What is the design space for a
digital system designer ?
More & Powerful design options are getting available to the developer.
Design Space Options : GPPs, DSPs, FPGAs, Application Specific Processors, ASICs
Design Space Exploration deals with deciding the best from the available options for the design
For Further Reading : [SHO] Chapter-1
Design Space Exploration44
Moore’s Law (1965) is fueling the DSP Market
45
The number of transistors on a chip was doubling every 18 to 24 months and made the prediction for future
32nm => Sandy Bridge (2011) 11 nm => approx. 2015
More & Powerful Design Options are now available
[SHO]
Design Options/Space46
Programmable Processors (& Microcontrollers) [General purpose Instruction Set Processors ]
Programming flexibility
Optimized - Architectures with so much design effort put in their designs
Examples: Intel, Atmel, ARM Processors
Digital Signal Processors / [Application Specific Instruction Set Processors (ASIPs)]
Programming flexibility. Optimized Architectures for DSP Applications e.g. dedicated MAC units
Examples: DSP from Texas Instruments, Array/Vector instructions
FPGA – Field Programmable Gate Arrays
Reconfigurable Hardware
Typically Fully dedicated design ----- Longer Development cycle
ASIC – Application Specific Integrated Circuits
Fully dedicated design, Lower cost, low power, No flexibility
Custom ASIPS such as DIGIC 4
Hybrid Architectures
HW/SW combined designs
FPGAs containing Processors Soft Processors [Microblaze, NIOS, Power PC]
Processors Containing (tightly coupled with) reconfigurable (coarse/fine) logic
Canon DIGIC 5+Application Specific Instruction Set Processor
http://thenewcamera.com/wp-content/uploads/2012/01/Canon-1D-X-processing-syste.jpghttp://www.dancewithshadows.com/tech/wp-content/uploads/2009/03/canon-eos-t1i-photo.jpg
Application Specific Processors are typically combination of an instruction programmable core with specialized hardware units.
The most recent version, DIGIC 5, wasco-designed by Texas Instruments andbased on the Texas Instruments OMAP,a System-on-Chip (SoC) that includesan ARM architecture processor.[1][2] Sincethese processors are based aroundthe ARM CPUs, custom firmware forthese units have been developed to addfeatures to the cameras.
Source Wikipedia
Hybrid Architectures
Hybrid Architectures combine both : Instruction Programmable Processors & FSM based Dedicated Designs
Previous Trend Soft Processor Cores embedded inside an FPGA. Example : Micro-Blaze in Xilinx
Hard Processor Cores embedded inside an FPGA. Example : Power PC
New Trend
Pre-Fabrication Customization For example Xtensa Customizable Processor from a company called Tensilica.
Tensilica allows you to add custom instructions of your choice to the processor. Once you are done they fabricate the processor for you.
Post Fabrication reconfigurable Enhancements For example Xilinx ZYNQ architecture where you have a dual core ARM processor
closely coupled with reconfigurable logic that can be used as a hardware accelerator.
The future…..Hybrid Architectures
Xtensia from Tensillica
Pre-Fabrication Compile Time Customization
Hybrid Architectures
Hybrid Architectures combine both : Instruction Programmable Processors & FSM based Dedicated Designs
Previous Trend Soft Processor Cores embedded inside an FPGA. Example : Micro-Blaze in Xilinx
Hard Processor Cores embedded inside an FPGA. Example : Power PC
New Trend
Pre-Fabrication Customization For example Xtensa Customizable Processor from a company called Tensilica.
Tensilica allows you to add custom instructions of your choice to the processor. Once you are done they fabricate the processor for you.
Post Fabrication reconfigurable Enhancements For example Xilinx ZYNQ architecture where you have a dual core ARM processor
closely coupled with reconfigurable logic that can be used as a hardware accelerator.
The future…..Hybrid Architectures
Xilinx ZYNQ 7000
Post Fabrication reconfigurable Enhancements
Cash the benefit of both…• Easy & Rapid Development• Customized H/W only for compute intensive units
Design Space Options53
[SHO]
Application Specific Custom
Dedicated Design
How to select the best from
the design space ?
Design Decision depends on the nature & complexity of applications
55
Applications are characterized by amount of data, parallelism, real time requirements.
And.. Time to market
Cost
Complexity to port to H/W
Quantity
Power Requirements
Analyzing your application for design space exploration
56
Computationally intensive (‘number crunching’) tasks
Standard Tasks/Protocols/Interfaces/Encoding
Commercial off the shelf ASICs are available
Memory Controllers, Firewire interfaces, Audio interface (AC97), DVI interface
Non Standard Structured Tasks (Less Decisions, Straightforward Datapath)
Consist of code that has loops with no/less dependencies. For example array operations
Suitable for FPGAs/custom ASICs
Examples: FFT Butterflies , Long arithmetic chains,
Non Standard Non Structured Sequential Tasks
More Code intensive & complex to port to H/W. due to Dependencies
Suitable for DSP Processors
Adaptive Algorithms with multiple IF/Else such as Motion Vector Estimation, Matrix^Power
Control Oriented Tasks
User interfaces, control processes, system controllers and other code intensive protocols are usually mapped on GPPs or microcontrollers.
Multiple interrupts & Complex Scheduling are conveniently handled by Operating Systems so better handled by instruction based Processors
A typical system57
For complex systems HW/SW co design may be the only optimal choice.
Soft processors like NIOS even allow you to make custom instructions !
Use a processor with FPGA/ASICS as Hardware Accelerators
Where are we focusing ?58
[SHO]
Application Specific Custom
Dedicated Design
A little exercise…59
Display- 480 x 640 pixels, VGA, resistance type touch
User Interface Navigation
Touch screen on LCD
Control Buttons : Power on and OFF
Wifi, Bluetooth,
Supports camera & JPEG compression
Built-in GPS Radio
Need support to run Mobile Applications
What components you shall be using for your system ?
Group of 3-4 – On a paper & submit
http://www.openmoko.com/freerunner.html
An examples60
..& you need an OS too
Memory
Of-the-shelfASIC
Custom Design
In a modern architecture…Everything on a single system on chip (SoC)
Reading Assignment62
Relevant sections of Chapter-1 [SHO]
LECTURE-2
DIGITAL DESIGN METHODOLOGY
What we learned in the Last Lecture ?
What’s Design Space Exploration ?
Difference between HW & SW ?
How Moore’s Law is fueling the miniaturization
GPPs, DSPs, FPGAs, ASICs & Hybrids
That FPGAs are based on LUT (Look Up Tables) & ASICS on actual gates.
80/20 Rule & the motivation for HW/SW Co-Design
HW is desirable where we have the opportunity to process things in parallel since we have no dependencies
Digital Design Methodology66
From concept to reality
A long tiring process
http://nigamanth.net/vlsi/category/asic-design-flow/
Design Methodology: Big Picture
67
MRD Marketing Requirement
Document
Arch. Spec.
(Macro Architecture)
Micro-Architecture Document
(Detailed Design , Design Partition)
(Design Entry)
HDL
SimulationFunctional Verification
Design Integration & Verification
Pre synthesis Sign-Off
Synthesize & Map Gate-Level
Netlist
Post synthesis Design
Verification
Test Generation & Fault
Generation
Clock Trees
Cell Routing
Verify Physical & Electrical Design
RulesExtract ParasiticsDesign Sign-Off
Design Methodology
A list of desirable features
Studies
Customer’s expectations
Competing Products
Add-ons
Market opportunities
Time to market
Profit Margins
Quantity
Impacts design decision
Architecture at a very high and abstract level
Block diagrams
Usually a transaction level model (TLM)
How data is moving across different blocks
State machines that control the flow of data
Typically a long boring document
Marketing Requirement Document (MRD)
Architecture Specification
(Macro Architecture)
SampleArchitecture
69
Architectural Spec : Another Example….
Design Methodology
Design Partitioning
Control vs. datapath separation
Interconnection structures (modules) within datapath
Partitioning of functions into blocks
Going deeper into design
Interface definition for each module
Clock/reset requirements,
Optimizations
Memory buffers
Implementation State Machines
Timing Charts
Top-down design method
Exploiting hierarchy
This document is crucial, for a
large team working on various modules of the same design.
Design Specification
Micro Architecture
Typically an even longer document as compared to Architecture
Specification Document
Design Methodology
Take design to a deeper level where each register is known and code it using HDL (Hardware Description Languages)
HDL De-burdens gate level
optimizations
Allows this stage to be technology independent (e.g., FPGA LUTs or ASIC standard cell libraries)
Behavioral descriptions
Simulation vs. Formal Methods
Test Plan Development
What to test & how ?
E.g: Instruction set for a range of data, Corner cases for ALUs,
Testbench Development
Testing of independent modules
Does your design meets specification
72
RTL HDL Design
(Register Transfer Level)
Simulation and Functional Verification of each module
Design Methodology
Integrate
Bugs lurking in the interface behavior among modules
The Testbench
I/O interfacing with top level module
Monitor port & bus activity across module boundaries
Test Vectors
Full functionality Demonstrated
Make sure that the behavior specification (HDL) meets the design specification (coded in HDL or system verilog)
73
Design Integration and Verification
Pre synthesis sign-off
Design Methodology
Synthesize the design from the behavior description
Map onto target technology
Optimizations Minimize logic Reduce area Reduce power Balance speed vs. other
resources consumed
Produces netlist of standard cells(for ASICS) or database to configure LUTs (for FPGAs)
Comparing Synthesized gate-level description to the verified behavioral model
A testbench that instantiates both models & drive them via common stimulus
74
Gate-Level Synthesis and Technology Mapping
Post-synthesis Design Validation
Design Methodology
Are the timing specifications met?
Are the speeds adequate on the critical paths?
Re-synthesis may be required to achieve timing goals
Modify architecture
Choose a different target device or technology
Test Generation and Fault Simulation
Placement and Routing
Clock distribution trees to minimize skew
Physical and Electrical Design Rule Check
Determining Parastics / Interference
75
Post synthesis Timing Verification
ASIC Specific
Design Methodology: Big Picture
76
MRD Marketing Requirement
Document
Arch. Spec.
(Macro Architecture)
Micro-Architecture & Design Partition
Design Entry
HDL
SimulationFunctional Verification
Design Integration & Verification
Pre synthesis Sign-Off
Synthesize & Map Gate-Level
Netlist
Post synthesis Design
Verification
Test Generation & Fault
Generation
Clock Trees
Cell Routing
Verify Physical & Electrical Design
RulesExtract Parasitic
Design Sign-Off
ASIC Specific
Reading Assignment77
Relevant sections of Chapter-1 [SHO]
All Excluding : 1.3.2,1.3.3,1.8.1,1.8.2,1.8.3
http://www.design-reuse.com/articles/9010/fpga-s-vs-asic-s.html
FPGA's vs. ASIC's
Questions….
HDLs, Verilog HDL, VHDL
Related Reading
Verilog Basics & Dataflow Verilog Level
Chapter 2 [Dr. Shoab’s Book]
Till before Section 2.6.4 & Excluding the following Section 2.5.2
2.5.3.1
2.5.3.2
Verilog Basics81
Today’s Lecture
Modules in Verilog
Instantiating a Module
Gate Level Modeling in Verilog
Data Flow Level Modeling in Verilog
Conditional Operation & Operators
Behavioral Level
CASE, IF-ELSE
Verilog83
HW or SW ?
Verilog --- Programming language ?
Verilog
HW Description
In H/W Everything is always active
Creates your Datapath/Circuit
Its simulation is Event Based
The synthesis tool understands only a subset of Verilog, the part of Verilog called ‘RTL Verilog’
Is Verilog Simulation event
based ?
Is the synthesized H/W also
event based ?
Verilog
Data Types
85
net Connection between hardware elements
Default value Z High Impedance [not driven by circuit, the signal is neither driven to a logical high nor low level ]
Declared as Wire
reg Can act as A variable that holds a value … (need to be careful)?
Synthesizable to register or latch
Declared as reg
Initial state is Unknown (X) in Verilog Simulation
Vectors wire [7:0] data_bus; // A bus of width 8
//8 bit bus, with bit-7 as the most significant
Memories reg mem1bit [0:1023]; // 1K 1 bit words
reg [7:0] membyte [0: 1023]; // 1K 8 bit words
Others Integer, Real, Time, Arrays, Strings, Parameters
Word Size
Examples
wire [low# : high#] or wire [high# : low#]
The first # defines the MSB
Example
Wire [2:0] a = 3’b001; // Bit 2 is the MSB (Use This)
Wire [0:2] a = 3’b001; // Bit 0 is the MSB
Assigning value to a part-select of vector
wire [31:0] a,b,c;
a[31] = 1’b1
//Above means we are making the MSB of a equal to 1
You can’t change the order of MSB after declaration
Leave : Variable Vector Part Select
Verilog 2001 allows Multi-Dimensional Arrays
87
Xilinx allows upto 3D arrays (Correct for 2011 )
Declaring 3D array //////////////// 3 D Array reg [7:0] d [0:3][0:1][0:1];
Accessing 3D Array d[1][0][0] = data; d[1][0][0] [3:0]= 4’b1010;
Accessing parts of an element of 3D Array e = d[3][1][0][3:0];
http://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf
Constants
Verilog89
Comments //
Number Specification 2’b11 // 2 bit binary number
Without base format decimal numbers e.g. 11 is a decimal no. Without size simulator/machine specific, e.g: ‘h11 is a 32 bit no.
12’hCDF // 12 bit hex number
-3’d1 // 3 bit 2’s complement of 1
Keywords & Identifiers wire Write_enable; // wire is a keyword & Write_enable is an identifier
Logic Values: 0,1 & ..X,Z Unknown Value: X, e.g. Un-initialized value, A net driven by two primitives
High Impedance: Z, e.g. Tristate Buffer, Bi-directional I/O
It is important to remember that there is no X (unknown value) in a real circuit [SHO]
What shall be the value of
a, b and c
wire a = 4’d11;
wire b = 4’b0011;
wire c = 4’b11;
Tri-State Buffer for IO-Ports
FPGA Outside
inout IO_Pad;
wire Input_Data;
wire Output_Data;
wire Output_Enable;
assign Input_Data = IO_Pad;
assign IO_Pad = Output_Enable ? Output_Data : 1’bz
& assign the IO type in your ucf (User Constrained File)
IO_PAD
Output_Enable
Output_Data
Input_Data
Verilog Module
Consider a very simple design
We want to make a Full Adder
FA
HA
HA
Verilog HALF Adder & FULL Adder
[CIL]
module HA_GateLevel(input a, b ,output c_out, sum
);
xor x1 (sum,a,b);and and1 (c_out,a,b);
endmodule
gate(out,in1,in2)
module HA_GateLevel (a,b,c_o,s_o);input a,b;output c_o, s_o;
xor (s_o,a,b);and (c_o,a,b);
endmodule
Basic Verilog Module
module HA_GateLevel(input a, b ,output c_o, s_o
);
xor (s_o,a,b);and (c_o,a,b);
endmodule
Module Declaration & Port Listing
Intermediate Connections, Wire
Declarations
Module LogicComb./Seq.
End Module
Verilog 1995Verilog 2001
module FA(input a,b,c_in,output sum, cout);
wire s1,c1,c2;
HA_GateLevel HAB1 (.a(a), .b(b), .c_o(c1), .s_o(s1));
HA_GateLevel HAB2 (.a(c_in), .b(s1), .c_o(c2), .s_o(sum));
or(cout,c2,c1);
endmodule
module HA_GateLevel(input a, b ,output c_o, s_o
);xor (s_o,a,b);and (c_o,a,b);endmodule
Module Declaration & Port Listing
Intermediate Connections, Wire
Declarations
Instantiation of
Lower Level Modules &
Port Connection
(2001)
Module LogicComb./Seq.
End Module
module HA_GateLevel(input a, b ,output c_o, s_o
);xor (s_o,a,b);and (c_o,a,b);endmodule
module FA(input a,b,c_in,output sum, cout);
wire s1,c1,c2;
HA_GateLevel HAB1 (.a(a), .b(b), .c_o(c1), .s_o(s1));
HA_GateLevel HAB2 (.a(c_in), .b(s1), .c_o(c2), .s_o(sum));
or(cout,c2,c1);
endmodule
Module Declaration & Port Listing
Intermediate Connections, Wire
Declarations
Instantiation of
Lower Level Modules &
Port Connection
(2001)
Module LogicComb./Seq.
End Module
//1995 Instantiation Style
HA_GateLevel HAB1 (a, b, c1, s1);
// Second Half AdderHA_GateLevel HAB2 (c_in, s1, c2, sum );
module Parent_Module (….)……….
97
reg or net
wire
wire
wireInput InOut
Output out is a reg or wire
wire
Intermediate Connections, Wire Declarations, regs
Instantiation of lower modules
Dataflow Statements assign out = in1 & in2
wire out = in1 & in2
Procedural blocksAlways/initial blocks
(Behavioural statements)
module Sample_Name (in1, in2, out)input wire in1,in2;output reg out;
endmodule
Rule: Input inside a module is always a wire
Signal_From_Sample_Name must be a wire
Example
Port Listing Styles
Verilog 95 vs Verilog 2001 style
[SHO]
Port Connection StylesInstantiating a Module in another block
Verilog 95 vs Verilog 2001 style
Lets use the previous FA to make a 3 bit Ripple Carry Adder
[SHO]
This method is better for block with greater no.
of ports